Contacting Diversely Doped Semiconductive Regions (e.g., P-type And N-type Regions, Etc.) Patents (Class 438/621)
  • Publication number: 20010029097
    Abstract: A bulk semiconductor substrate is provided which has an active area received between at least two undoped silicon dioxide comprising substrate isolation regions. The substrate includes at least two transistor gate constructions received at least partially over the active area. The gate constructions include gates having their sides and tops covered with insulating material comprising at least one of undoped silicon dioxide and silicon nitride. A doped silicon dioxide layer is formed over the active area, the isolation regions and the gate constructions. A patterned masking layer is formed over the doped silicon dioxide layer. The patterned masking layer has a mask opening formed therein which overlaps at least one of the gate constructions and the active area. The substrate is placed within a high density plasma etcher. The etcher has a directly coolable top power electrode, a biasable electrostatic chuck, a focus ring, and directly heatable chamber sidewalls.
    Type: Application
    Filed: May 17, 2001
    Publication date: October 11, 2001
    Inventors: Kei-Yu Ko, Dave Pecora
  • Patent number: 6297120
    Abstract: To provide a method of manufacturing a semiconductor device in which an epitaxial growth film is formed on a semiconductor substrate having a buried layer, which is capable of reducing the manufacturing time of the semiconductor device or reducing the IC chip area. The method of manufacturing a semiconductor device is characterized by including a process of selecting the concentration of the p-type conductive impurities which put the surface of the silicon semiconductor substrate into a full amorphous state and conducting doping with the impurities.
    Type: Grant
    Filed: June 4, 1999
    Date of Patent: October 2, 2001
    Assignee: Seiko Instruments Inc.
    Inventor: Sumio Koiwa
  • Patent number: 6284591
    Abstract: A method of forming an interconnection by using a landing pad is disclosed. In a semiconductor device having a memory cell portion and a peripheral circuit portion, a refractory metal is used for the bitline instead of the usual polycide, to concurrently form a contact on an active region of an N-type and a P-type substrate. A landing pad is formed on the peripheral circuit portion at the same time as a bitline is formed on the memory cell portion. In such a process, a substantial contact hole for the interconnection is formed on the landing pad so that an aspect ratio of the contact can be lowered. Accordingly, when forming a metal interconnection, the contact hole for the interconnection is easily filled by Al-reflow so that the step coverage of the metal being deposited in the contact hole for the interconnection is enhanced, and the contact resistance is reduced. As a result, the reliability of the semiconductor device is improved.
    Type: Grant
    Filed: April 27, 1999
    Date of Patent: September 4, 2001
    Assignee: Samsung Electromics Co., Ltd.
    Inventor: Sang-in Lee
  • Publication number: 20010016413
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device with reduced contact failures are provided. The device includes a semiconductor substrate on which a first insulating layer is formed, the first insulating layer having a first contact hole. A conductive plug is formed in the first contact hole. A second interlevel insulating level is formed on the first insulating layer, the second interlevel insulating layer having a second contact hole with a predetermined width different from the width of the first contact hole. The second contact hole is formed so as to be integrally connected to the first contact hole. A second conductive plug is formed in the second contact hole, and a metallization is formed on a predetermined portion of the second interlevel insulating layer such that it is connected to the second conductive plug.
    Type: Application
    Filed: April 24, 2001
    Publication date: August 23, 2001
    Inventors: Kyung-Tae Lee, Young-Wug Kim
  • Patent number: 6277720
    Abstract: A method of fabricating an integrated circuit, and an integrated circuit so fabricated, is disclosed. A silicon dioxide layer (14) that is doped with both boron and phosphorous, typically referred to as BPSG, is used as a planarizing layer in the integrated circuit structure, above which conductive structures (46, 52, 54) are disposed. A silicon nitride layer (30) is in place below the BPSG layer (14), and serves as a barrier to the diffusion of boron and phosphorous from the BPSG layer (14) during high temperature processes such as reflow and densification of the BPSG layer (14) itself. Contact openings (PC, BLC, CT) are etched through the BPSG layer (14) and the silicon nitride layer (30) using a two-step etch process.
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: August 21, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Vikram N. Doshi, Takayuki Niuya, Ming Yang
  • Publication number: 20010012669
    Abstract: A field oxide film is provided in the surface of a semiconductor substrate. An interlayer insulating film is provided on the semiconductor substrate so as to cover an active layer. A contact hole exposing the surface of the active layer is provided in the interlayer insulating film. A conductor fills the contact hole so as to be electrically connected to the surface of the active layer. The end portion of the field oxide film has a surface perpendicular with respect to the surface of the semiconductor substrate. As a result, a dynamic random access memory can be obtained which is improved so that leakage current is reduced, which in turn increases a hold time of information.
    Type: Application
    Filed: August 13, 1999
    Publication date: August 9, 2001
    Inventor: TSUKASA OOISHI
  • Publication number: 20010009806
    Abstract: According to the present invention, a contact hole is formed by using a contact formation mask until portions of a first and a second impurity areas are respectively exposed, so that contact holes are formed. The size of the contact hole formed over the first impurity area (P-type impurity) is relatively larger than that of the contact hole formed over the second impurity area (N-type impurity). As a result, the size of the contact hole formed over an N-type impurity area decreases and that of the contact hole formed over a P-type impurity area increase to a corresponding degree, thereby reducing contact resistance generated on the P-type impurity area without increasing a chip size.
    Type: Application
    Filed: March 7, 2001
    Publication date: July 26, 2001
    Inventor: Soon-Kyou Jang
  • Patent number: 6261908
    Abstract: A method of fabricating a buried local interconnect in a substrate and an integrated circuit incorporating the same are provided. The method includes the steps forming a trench in the substrate and forming a first insulating layer in the trench. A conductor layer is formed on the first insulating layer. A portion of the conductor layer is removed to define a local interconnect layer and a second insulating layer is formed in the trench covering the local interconnect layer. The method provides for a local interconnect layer buried beneath a dielectric layer of an integrated circuit, such as a shallow trench isolation layer. Areas of a substrate above the silicon-silicon dioxide interface formerly reserved for local interconnect layers in conventional processing may now be used for additional conductor lines.
    Type: Grant
    Filed: July 27, 1998
    Date of Patent: July 17, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frederick N. Hause, Mark I. Gardner, Charles E. May
  • Patent number: 6258647
    Abstract: A method of fabricating a semiconductor device includes the steps of: forming a well of first conductivity type and well of second conductivity type in a substrate; forming a field oxide layer and gate oxide layer on the substrate; forming first and second polysilicon layers on the field oxide layer and gate oxide layer, the first polysilicon layer being doped with impurities of second conductivity type, the second polysilicon layer being doped with impurities of first conductivity, the first and second polysilicon layers coming into contact with each other; patterning the first and second polysilicon layers to be isolated from each other, to thereby forming first and second gates; and forming a conductive layer between the first and second gates. Accordingly, isolation of N-type and P-type polysilicon layers from each other, and patterning of them for the purpose of forming a gate are carried out using one mask, effectively simplifying the etching process during a gate patterning process.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: July 10, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Chang-Jae Lee, Jong-Kwan Kim
  • Publication number: 20010006847
    Abstract: The present invention provides a method for providing an interconnect in a flash memory device. A first embodiment includes forming at least one contact hole in a peripheral area of the device; bombarding a bottom of the at least one contact hole with ions, where the ions break down undesired oxide residing at the bottom of the at least one contact hole; depositing a barrier metal layer into the at least one contact hole, where the barrier metal layer breaks down remaining undesired oxide at the bottom of the at least one contact hole, and where bombarding with the ions and the depositing of the barrier metal layer minimize an undesired widening of the at least one contact hole; and depositing a contact material into the at least one contact hole. With the first embodiment, both the ions and the titanium break down the undesired oxide while neither breaks down the desired oxide at the sides of the contact hole to a significant degree.
    Type: Application
    Filed: February 1, 2001
    Publication date: July 5, 2001
    Applicant: Advanced Micro Devices, Inc.
    Inventors: John JianShi Wang, Kent Kuohua Chang, Hao Fang, Kelwin King Wai Ko, Mark S. Chang, Angela T. Hui
  • Patent number: 6245658
    Abstract: Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigration performance by removing the inter-layer dielectrics and supporting the interconnection system with a metal silicide lining. Embodiments include depositing a dielectric sealing layer, e.g., silicon nitride, before forming the first metallization level, removing the inter-layer dielectrics after forming the last metallization level, electroplating or electroless plating a metal, such as cobalt or nickel, to line the interconnection system, depositing a thin layer of polycrystalline silicon on the metal, heating to form the metal silicide lining on the interconnection system, and forming dielectric protective layers, e.g. a silane derived oxide bottommost protective layer, on the uppermost metallization level.
    Type: Grant
    Filed: February 18, 1999
    Date of Patent: June 12, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Matthew S. Buynoski
  • Patent number: 6242330
    Abstract: A process for breaking silicide stringers extending between silicide regions of different active regions on a semiconductor device is provided. Consistent with an exemplary fabrication process, two adjacent silicon active regions are formed on a substrate and a metal layer is formed over the two adjacent silicon active regions. The metal layer is then reacted with the silicon active regions to form a metal silicide on each silicon active region. This silicide reaction also forms silicide stringers extending from each silicon active region. Finally, at least part of each silicide stringer is removed. During the formation of the silicide stringers at least one silicide stringer may be formed which bridges the metal silicide over one of the silicon regions and the metal silicide over the other silicon region. In such circumstances, the removal process may, for example, break the silicide stringer and electrically decouple the two silicon regions.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: June 5, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jon Cheek, Derick J. Wristers, Fred Hause
  • Patent number: 6239015
    Abstract: A doped polysilicon layer is used to form interconnections in a semiconductor device through contact holes. The doped polysilicon layer reaches through contact holes formed in an interlayer insulation layer to reach a suicide layer formed in exposed portions of respective impurity regions.
    Type: Grant
    Filed: December 4, 1998
    Date of Patent: May 29, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hoon Jung
  • Patent number: 6232220
    Abstract: A method for fabricating a semiconductor component having a low contact resistance with respect to heavily doped or siliconized zones in a semiconductor body. Fluorine ions are implanted into the heavily doped or siliconized zone in the vicinity of a contact hole before a titanium layer is applied to the heavily doped or siliconized zone in the vicinity of the contact hole. As a result of the fluorine, any oxide layers present in the contact hole region can be broken up by less titanium, with the result that a thinner titanium layer is sufficient. In addition, the formation of titanium silicide in the contact hole is promoted.
    Type: Grant
    Filed: January 15, 1999
    Date of Patent: May 15, 2001
    Assignee: Infineon Technologies AG
    Inventors: Volker Penka, Reinhard Mahnkopf, Helmut Wurzer
  • Patent number: 6222267
    Abstract: A semiconductor device has: a silicon substrate; a plurality of impurity doped regions formed in a surface layer of the silicon substrate; contact layers each in contact with a surface of associated one of the plurality of impurity doped regions, the contact layer being made of an alloy selected from a group consisting of TiMo, TiV, TiW, TiMoNb, TiMoTa, TiMoV, TiMoW, TiNbV, TiNbW, TiMoNbTa, TiMoNbV, TiMoNbW, TiMoTaW, TiMoVW, TiNbTaW, TiNbVW, TiMoNbTaW, TiMoNbVW, and the like; barrier layers each disposed on associated one of the contact layers and made of refractory metal nitride or refractory metal oxynitride; and a metal wiring layer disposed on each of the barrier layers. The semiconductor device capable of lowering contact resistances between the metal wiring layers and n-type and p-type impurity doped regions of the silicon substrate, as well as its manufacture method are provided.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: April 24, 2001
    Assignee: Yamaha Corporation
    Inventor: Masayoshi Omura
  • Patent number: 6174807
    Abstract: A method of forming a multi-layered dual-doped polysilicon structure that minimizes Boron penetration into the n+ polysilicon during formation of the p+ polysilicon. The method of the present invention also reduces the migration of Boron (p+ gate dopant) from the p+ polysilicon and the migration of Arsenic and/or Phosphorous (n+ gate dopant) from the n+ polysilicon during subsequent fabrication processing steps. The present invention is also directed to a semiconductor device having a gate dopant barrier that minimizes gate dopant penetration and migration.
    Type: Grant
    Filed: March 2, 1999
    Date of Patent: January 16, 2001
    Assignee: Lucent Technologies, Inc.
    Inventors: Isik C. Kizilyalli, Joseph Rudolph Radosevich
  • Patent number: 6169025
    Abstract: A method of fabricating a self-align-contact is provided. A first gate and a second gate are formed on a semiconductor substrate. A spacer is formed on the sidewalls of the first gate and the second gate, and a source/drain region is formed between the first gate and the second gate. A dielectric layer is formed on the first gate, the second gate, the source/drain region, the spacer, and the semiconductor substrate. A self-align-contact opening is formed in the dielectric layer to expose the source/drain region. A metal silicide layer is formed on the source/drain region. A first conductive layer, such as doped polysilicon, is formed on the metal silicide layer and in the self-align-contact opening. A second conductive layer is formed on the first conductive layer, and the first conductive layer and the second conductive layer are patterned.
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: January 2, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Chien-Li Kuo
  • Patent number: 6162669
    Abstract: To obtain a semiconductor device which prevents an increase in the resistance of a source/drain region; which operates fast and stably; and which provides a high manufacturing yield, and to obtain a method of manufacturing the semiconductor device. A recess 8 is formed on a first low impurity-concentration region 5 with the exception of the area immediately below side wall insulating material 6y, and a layer damaged as a result of formation of the side wall insulating material 6y is removed. Further, a second low impurity-concentration region 10 is formed below the recess 8.
    Type: Grant
    Filed: April 9, 1999
    Date of Patent: December 19, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuyuki Horita, Takashi Kuroi, Yoshinori Okumura
  • Patent number: 6150254
    Abstract: A perimeter gate wiring 52 comprises a contact portion 54 and an interconnecting portion 56 having narrower width than the contact portion 54 which connects the contact portion 54 mutually. And the perimeter gate wiring 52 is connected electrically with the gate perimeter portion 66 at the contact portion 54. A source wiring perimeter portion 58 comprises a contact portion 60 and an interconnecting portion 62 having narrower width than the contact portion 60 which connects the contact portion 60 mutually. And the source wiring perimeter portion 58 is connected electrically with a perimeter diffusion layer 74 in the contact portion 60. The contact portion 54 of the perimeter gate wiring 52 and the interconnecting portion 62 of the source wiring perimeter portion 58 are provided adjacently. Also, the interconnecting portion 56 of the perimeter gate wiring 52 and the contact portion 60 of the source wiring perimeter portion 58 are provided with one another adjacently.
    Type: Grant
    Filed: August 12, 1999
    Date of Patent: November 21, 2000
    Assignee: Rohm Co., LTD
    Inventor: Takayuki Kito
  • Patent number: 6150214
    Abstract: A method of fabricating a DRAM integrated circuit structure (30) and the structure so formed, in which a common interconnect material (42, 48) is used as a first level interconnection layer in both an array portion (30a) and periphery portion (30p) is disclosed. The interconnect material (42, 48) consists essentially of titanium nitride, and is formed by direct reaction of titanium metal (40) in a nitrogen ambient. Titanium silicide (44) is formed at each contact location (CT, BLC) as a result of the direct react process. Storage capacitor plates (16, 18) and the capacitor dielectric (17) are formed over the interconnect material (42, 48), due to the thermal stability of the material. Alternative processes of forming the interconnect material (42, 48) are disclosed, to improve step coverage.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: November 21, 2000
    Assignee: Texas Instruments Incorporated
    Inventor: Toshiyuki Kaeriyama
  • Patent number: 6124189
    Abstract: A method for forming a metal-strapped polysilicon gate and for simultaneously forming a strapped-metal polysilicon gate and a metal contact filling includes the steps of forming a gate dielectric layer on a surface of a silicon substrate; forming a polysilicon layer on the gate dielectric layer; forming a first insulating layer on the polysilicon layer; forming insulating spacers on either side of the polysilicon layer and the first insulating layer; and forming ion implantation regions in the surface of the silicon substrate. Next, a second insulating layer is deposited on the silicon substrate, and the second insulating layer is polished using chemical mechanical polishing to planarize the upper surface of the second insulating layer with the upper surface of the first insulating layer as a polishing stopper. Then, a contact hole is formed in the second insulating film, wherein the contact hole is laterally spaced from the polysilicon layer and the first insulating layer.
    Type: Grant
    Filed: March 14, 1997
    Date of Patent: September 26, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toru Watanabe, Katsuya Okumura, Katsuhiko Hieda
  • Patent number: 6110818
    Abstract: According to one aspect of the invention, a method of fabricating N+ and P+ silicided gates limits diffusion when using a Tungsten, Titanium or Cobalt silicide in the gate fabrication. An example method involves doping a polysilicon structure in first and second dual gate regions and on either side of an undoped polysilicon region, forming a silicide is over the polysilicon structure, and then stuffing the undoped polysilicon region with a species selected to inhibit lateral diffusion of dopant from the polysilicon in the silicide. Subsequently, each gate is completed so that is includes a dielectric layer arranged over the silicide and one of the doped gate poly regions. Applications include logic circuits having embedded-DRAM, and circuits directed to stand-alone logic or stand-alone DRAM.
    Type: Grant
    Filed: July 15, 1998
    Date of Patent: August 29, 2000
    Assignee: Philips Electronics North America Corp.
    Inventor: Jacob Daniel Haskell
  • Patent number: 6107187
    Abstract: An opening (24) is formed in a substrate (20). A first layer (30) is formed over the substrate (20) and the feature opening (24). A second layer (40) is formed over the first layer (30) and then the second layer is removed until exposing portions (50) of the first layer (30). The exposed portions (50) of the first layer (30) are then optionally removed using remaining portions (52) of the second layer (40) as a patterning mask to form a cavity (60) in the first layer (30). The remaining portions of the second layer (52) are then removed and the first layer (30) is polished to form a semiconductor device structure (80). In one embodiment, the first layer is dielectric layer, and in an alternative embodiment, the first layer is a conductive layer.
    Type: Grant
    Filed: June 17, 1999
    Date of Patent: August 22, 2000
    Assignee: Motorola, Inc.
    Inventors: Keith Q. Lao, Yuri Y. Karzhavin, Patrick Michael Kelly
  • Patent number: 6096639
    Abstract: A local interconnect (LI) structure is formed by forming a silicide layer in selected regions of a semiconductor structure then depositing an essentially uniform layer of transition or refractory metal overlying the semiconductor structure. The metal local interconnect is deposited without forming in intermediate insulating layer between the silicide and metal layers to define contact openings or vias. In some embodiments, titanium a suitable metal for formation of the local interconnect. Suitable selected regions for silicide layer formation include, for example, silicided source/drain (S/D) regions and silicided gate contact regions. The silicided regions form uniform structures for electrical coupling to underlying doped regions that are parts of one or more semiconductor devices. In integrated circuits in which an etchstop layer is desired for the patterning of the metal film, a first optional insulating layer is deposited prior to deposition of the metal film.
    Type: Grant
    Filed: April 7, 1998
    Date of Patent: August 1, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robert Dawson, Mark I. Gardner, Frederick N. Hause, H. Jim Fulford, Jr., Mark W. Michael, Bradley T. Moore, Derick J. Wristers
  • Patent number: 6093629
    Abstract: A method for forming n- and p-type contacts for CMOS integrated circuits is described wherein the contact openings are ion implanted after being etched to provide supplemental doping to the exposed device elements in order to secure a reliable low resistance interface with subsequently deposited contact metallurgy The p-type contact openings and the n-type contact openings are patterned, etched, and ion implanted separately, thereby requiring only two photolithographic steps. By etching and implanting the p-contacts and n-contacts separately, the method eliminates one highly complex and contaminative photolithographic step and introduces a less complex etch step with reduced contamination risk, thereby achieving a cost saving by improving yield and reducing process time. It is optional which contacts are processed first.
    Type: Grant
    Filed: February 2, 1998
    Date of Patent: July 25, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Sen-Fu Chen
  • Patent number: 6077778
    Abstract: An improved and new method for forming a metal conductor interconnection structure on a semiconductor substrate containing DRAM devices has been developed. The method utilizes a thermal anneal in a flowing gas mixture of nitrogen and hydrogen following patterning of the metal conductor interconnection structure and results in DRAM devices having improved mean refresh time (time between refresh cycles).
    Type: Grant
    Filed: April 17, 1997
    Date of Patent: June 20, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yung-Kuan Hsiao, Min-Hsiung Chiang, Yuan-Chang Huang
  • Patent number: 6071799
    Abstract: The present invention relates to a method of forming a contact of a semiconductor device, and more particularly, to a method of forming a contact of a semiconductor device that can improve the process yield of the device and reliability by simplifying the process of forming the contact hole of the top conductive layer without removing the etching barrier layer of the portion on which the contact hole of the top conductive layer is to be formed when a storage electrode contact is formed, where the contact hole of the top conductive layer is formed on the top of the bottom conductive layer, which refers to a process of forming the self-alignment contact.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: June 6, 2000
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Cheol Soo Park, Chi Sun Hwang, Chang Hun Han
  • Patent number: 6063680
    Abstract: The method of the present invention includes forming a silicon dioxide layer, a first conductive layer and a first oxide layer on a silicon substrate to define a gate region of transistors. Then, a pad oxide layer is formed on the silicon substrate and a second oxide layer is formed on a side of the first conductive layer. Subsequently, a nitride spacer and a third oxide layer are formed, respectively. Then, the third oxide layer and the first oxide layer are removed. Next, a first metal layer is deposited on the silicon substrate and a source/drain/gate implantation is performed via ion implantation. Subsequently, a silicidation process is used to convert portions of the first metal layer into a silicide layer and then unreacted portions of the first metal layer and the nitride spacer are removed. Next, an ion implantation is performed to form an extended source/drain junction. Then, a fourth oxide layer is formed.
    Type: Grant
    Filed: February 19, 1998
    Date of Patent: May 16, 2000
    Assignee: Texas Instruments - Acer Incorporated
    Inventor: Shye-Lin Wu
  • Patent number: 6051884
    Abstract: The invention provides a method for producing wiring and contacts in an integrated circuit including the steps of forming insulated gate components on a semiconductor substrate; applying a photo-reducible dielectric layer to cover the substrate; etching holes and forming contacts; photo-reducing the dielectric to increase its conductivity; covering the resulting structure with an interconnect layer; etching the interconnect layer to define wiring in electrical contact with the contacts; and oxidizing the dielectric to reduce its conductivity.
    Type: Grant
    Filed: July 17, 1998
    Date of Patent: April 18, 2000
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Constantin Papadas
  • Patent number: 6048785
    Abstract: Each region of multiple regions on a semiconductor substrate is imaged in an exposure field defined by a reticle. The regions are separated and electrically isolated within the semiconductor substrate by an isolation such as a field oxide or trench isolation. The regions are interconnected by imaging using a stitching reticle having an exposure field overlapping a plurality of the regions. The combination of reticle-imaged fields effectively increases the size of a field formed using a step and repeat technique while achieving high imaging resolution within the combined regions. Similarly, a plurality of integrated chip sets, including microprocessor, memory, and support chips, are constructed on a single semiconductor wafer using separate reticle imaging of each of the plurality of integrated chip sets. The different circuits are interconnected using a stitch mask and etch operation that combines the regions.
    Type: Grant
    Filed: June 16, 1997
    Date of Patent: April 11, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: H. Jim Fulford, Jr., Robert Dawson, Mark I. Gardner, Frederick N. Hause, Mark W. Michael, Bradley T. Moore, Derick J. Wristers
  • Patent number: 6033978
    Abstract: Amorphous silicon layers are formed on an n-type single-crystal/poly-crystal layer and a p-type single-crystal/poly-crystal layer, and titanium is sputtered on the amorphous silicon layers; although the n-type dopant impurity are piled on the n-type single-crystal/poly-crystal layers, the amorphous silicon layers takes the piles of n-type dopant impurity thereinto, and promote the silicidation of the titanium layer.
    Type: Grant
    Filed: November 21, 1996
    Date of Patent: March 7, 2000
    Assignee: NEC Corporation
    Inventors: Kunihiro Fujii, Hirohito Watanabe
  • Patent number: 6020239
    Abstract: According to the present invention, a method for fabricating vertical circuit devices which include a body contact is disclosed. During the fabrication process, the body of a transistor is formed from a pillar of single crystal silicon. The silicon pillar is formed over a butted junction of N+ and P+ diffusions. This fabrication process results in a pillar structure which has an n+ diffusion contacting a portion of the base of the transistor body and a P+ diffusion contacting the remainder of the base of the transistor body. The proportion of N+ and P+ area at the base of the silicon pillar depends on the overlay of the opening to the butted junction. Gate oxide is grown over the entire pillar and a polysilicon gate material is then deposited and etched to form the transistor gate. Metal contact studs are formed, preferably via deposition. After fabrication, the entire surface of the device can be planarized by using any standard Chemical Mechanical Planarization (CMP) process.
    Type: Grant
    Filed: January 28, 1998
    Date of Patent: February 1, 2000
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey Peter Gambino, Jack Allan Mandelman, Stephen Anthony Parke, Matthew Robert Wordeman
  • Patent number: 6015741
    Abstract: A method for forming a self-aligned contact window such that the method is compatible with the process of forming a self-aligned titanium silicide layer on the same device, and hence capable of miniaturizing device dimensions. Furthermore, this invention utilizes the thicker etching stop layer thickness above the gate region than above the source/drain region to protect the titanium silicide layer in the gate region against electrical contact with the self-aligned contact.
    Type: Grant
    Filed: April 13, 1998
    Date of Patent: January 18, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Tony Lin, Water Lur, Shih-Wei Sun
  • Patent number: 6008115
    Abstract: Disclosed are a method for forming a structure of wires for a semiconductor device in which pads are formed for contact in cell regions as well as core regions and periphery regions where cell aspect ratios are very high, and a structure of wires so formed. The semiconductor device includes a semiconductor substrate arranged into cell regions and periphery and/or core regions, the periphery and/or core regions having a well formed in the semiconductor substrate, the semiconductor substrate being arranged into active regions and field regions, the semiconductor device also having field insulating layers in the field regions, plural gate structures on portions of the semiconductor substrate in the active regions, and impurity regions in the semiconductor substrate between the gate structures.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: December 28, 1999
    Assignee: LG Semicon Co., Ltd.
    Inventor: Hyuck-Chai Jung
  • Patent number: 5989996
    Abstract: A method for manufacturing a semiconductor device includes the steps of: forming a laminated film by forming an aluminum film and a titanium film in this order on P-type and N-type electrically conductive regions of a silicon substrate and forming a silicide layer containing a titanium silicide as a major component on the electrically conductive region by allowing the laminated film to react with silicon constituting the silicon substrate by a first heat treatment.
    Type: Grant
    Filed: February 11, 1998
    Date of Patent: November 23, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Akira Kishi
  • Patent number: 5981372
    Abstract: A metal utilized for forming a silicide film is left even after completion of the reaction to produce silicide. A conductive film made of a material other than the metal is grown on the metal. A local interconnection overlapping the silicide layer is formed by the conductive film and the metal remaining after formation of silicide.
    Type: Grant
    Filed: December 5, 1996
    Date of Patent: November 9, 1999
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Goto, Hiromi Hayashi
  • Patent number: 5972768
    Abstract: In a method of manufacturing a semiconductor device, an insulating film is formed on a surface of a p-type semiconductor region, and then removed from a selected portion of the p-type semiconductor region. An n-type region having a high concentration of arsenic atoms is formed in a surface layer of the selected portion of the p-type semiconductor region from which the insulating film is removed. Subsequently, boron ions are implanted over an entire surface of the device in a concentration that is lower than that of the n-type region and higher than that of the p-type semiconductor region, to a smaller depth than that of the n-type region, and heat treatment is then effected to form a high-concentration boron diffused region in a surface layer of the p-type semiconductor region.
    Type: Grant
    Filed: February 19, 1997
    Date of Patent: October 26, 1999
    Assignee: Fuji Electric Co. Ltd.
    Inventors: Yoshihiko Nagayasu, Tatsuhiko Fujihira, Kazutoshi Sugimura, Yoichi Ryokai
  • Patent number: 5970334
    Abstract: In a method of manufacturing a semiconductor device having a first conductive layer of a first conductive type and a second conductive layer of a second conductive type opposite to the first conductive type, an intermediate layer of a predetermined element selected from the group V is formed on the first and second conductive layers to a preselected thickness of several atomic layers. Next, a metal film is deposited on the intermediate film. The intermediate layer is absorbed in the metal film and vanishes during the deposition of the metal film. The metal film may be formed of tungsten or molybdenum, while the thickness of the intermediate layer may be equal to one or two atomic layers.
    Type: Grant
    Filed: September 26, 1997
    Date of Patent: October 19, 1999
    Assignee: NEC Corporation
    Inventor: Hiroshi Tsuda
  • Patent number: 5945350
    Abstract: A method for use in the fabrication of semiconductor devices includes forming a titanium nitride film and depositing a silicon hard mask over the titanium nitride film. The silicon hard mask is used to pattern a titanium nitride interconnect from the titanium nitride film and the silicon hard mask is also used as a contact etch stop for forming a contact area. In forming the interconnect, the silicon hard mask is dry etched stopping selectively on and exposing portions of the titanium nitride film and the exposed portions of the titanium nitride film are etched resulting in the titanium nitride interconnect. In using the silicon hard mask as a contact etch stop, an insulating layer is deposited over the silicon hard mask and the insulating layer is etched using the silicon hard mask as an etch stop to form the contact area. The silicon hard mask is then converted to a metal silicide contact area. Interconnects formed using the method are also described.
    Type: Grant
    Filed: September 13, 1996
    Date of Patent: August 31, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Michael P. Violette, Sanh Tang, Daniel M. Smith
  • Patent number: 5930662
    Abstract: A method of making ohmic contact between a thin film polysilicon layer of a first conductivity type and a subsequently provided conductive layer includes: a) providing a semiconductor substrate having an outer region; b) providing a first insulating layer outwardly of the outer region; c) etching a first contact opening of a first diameter through the first insulating layer to the substrate outer region; d) providing conductivity enhancing dopant impurity of the first conductivity type into the substrate outer region to render the outer region electrically conductive; e) providing a thin film polysilicon layer of the first conductivity type into the first contact opening and in ohmic electrical connection with the substrate outer region; f) providing a second insulating layer outwardly of the thin film polysilicon layer and the first insulating layer; g) etching a second contact opening of a second diameter into the second insulating layer, the second contact opening overlapping with the first contact opening
    Type: Grant
    Filed: June 18, 1996
    Date of Patent: July 27, 1999
    Assignee: Micron Technology, Inc.
    Inventor: Monte Manning
  • Patent number: 5913139
    Abstract: A first metal silicide film is formed on an exposed silicon region of a substrate on which the silicon region and an insulating region are exposed. A metal film is deposited over the whole surface of the substrate covering the first metal silicide film, the metal film capable of being silicidized. A silicon film is deposited on the surface of the metal film. The silicon film and metal film are patterned to form a lamination pattern of the silicon film and metal film continuously extending from a partial area of the exposed silicon region to a partial area of the insulating region. The lamination pattern is heated to establish a silicidation reaction and form a second metal silicide layer.
    Type: Grant
    Filed: August 8, 1997
    Date of Patent: June 15, 1999
    Assignee: Fujitsu Limited
    Inventors: Koichi Hashimoto, Hiromi Hayashi
  • Patent number: 5909631
    Abstract: A method of making ohmic contact between a thin film polysilicon layer of a first conductivity type and a subsequently provided conductive layer includes: a) providing a semiconductor substrate having an outer region; b) providing a first insulating layer outwardly of the outer region; c) etching a first contact opening of a first diameter through the first insulating layer to the substrate outer region; d) providing conductivity enhancing dopant impurity of the first conductivity type into the substrate outer region to render the outer region electrically conductive; e) providing a thin film polysilicon layer of the first conductivity type into the first contact opening and in ohmic electrical connection with the substrate outer region; f) providing a second insulating layer outwardly of the thin film polysilicon layer and the first insulating layer; g) etching a second contact opening of a second diameter into the second insulating layer, the second contact opening overlapping with the first contact opening
    Type: Grant
    Filed: July 16, 1996
    Date of Patent: June 1, 1999
    Assignee: Micron Technology, Inc.
    Inventor: Monte Manning
  • Patent number: 5888895
    Abstract: In order to form an ohmic contacts to both the n+ and the p+ doped regions of complementary metal oxide semiconductor substrate regions of the an integrated circuit device, wells (contact holes) are formed in the insulating using a hard mask poly-Si layer on an insulating region exposing the doped substrate regions. A TiSi.sub.x layer is formed on the walls and base of the well either by physical vapor deposition or is formed by combining a layer of poly-Si with a layer of Ti. The TiSi.sub.2 is diffused into the doped region during an annealing step. In addition, the TiSi.sub.2 layer is converted into the low resistivity C54 configuration in an annealing step.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: March 30, 1999
    Assignee: Texas Instruments Incorporated
    Inventor: Koichi Mizobuchi
  • Patent number: 5888889
    Abstract: A process for manufacturing an integrated structure pad assembly for wire bonding to a power semiconductor device chip including a chip portion having a top surface covered by a metallization layer which has a first sub-portion wherein functionally active elements of the power device are present. The chip portion has at least one second sub-portion wherein no functionally active elements of the power device are present. The top surface of the at least one second sub-portion is elevated with respect to the first sub-portion to form at least one protrusion which forms a support surface for a wire.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 30, 1999
    Assignee: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Ferruccio Frisina, Marcantonio Mangiagli
  • Patent number: 5880020
    Abstract: A process of production of a semiconductor device comprising the steps of forming a first interlayer insulating film for covering a transistor formed on a substrate; forming a contact hole which will be connected to the transistor and a contact hole for local connection which will connect locations near each other simultaneously; and filling the contact holes with a conductor to form conductive plugs.
    Type: Grant
    Filed: October 20, 1997
    Date of Patent: March 9, 1999
    Assignee: Sony Corporation
    Inventor: Michio Mano
  • Patent number: 5874328
    Abstract: CMOS transistors are formed by a damascene process resulting in field oxide regions exhibiting essentially no bird's beak portions. A trench isolation is also formed in a source/drain region each transistor between adjacent junctions.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: February 23, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yowjuang W. Liu, Kuang-yeh Chang
  • Patent number: 5869391
    Abstract: A semiconductor processing method of making electrical connection between an electrically conductive line and a node location includes, a) forming an electrically conductive line over a substrate, the substrate having an outwardly exposed silicon containing node location to which electrical connection is to be made, the line having an outer portion and an inner portion, the inner portion laterally extending outward from the outer portion and having an outwardly exposed portion, the inner portion having a terminus adjacent the node location, and b) electrically connecting the extending inner portion with the node location. An integrated circuit is also described. The integrated circuit includes a semiconductor substrate, a node location on the substrate, and a conductive line over the substrate which is in electrical communication with the node location. The conductive line includes an outer portion and an inner portion.
    Type: Grant
    Filed: August 20, 1996
    Date of Patent: February 9, 1999
    Assignee: Micron Technology, Inc.
    Inventor: Monte Manning
  • Patent number: 5861676
    Abstract: A conducting trench in a dielectric layer can function as both (a) a plurality of contacts and (b) an interconnect in a semiconductor device. The conducting trench may be made by depositing a conductor in a trough formed in a dielectric layer of the device.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: January 19, 1999
    Assignee: Cypress Semiconductor Corp.
    Inventor: Ting Yen
  • Patent number: 5851910
    Abstract: A method of fabricating a bonding pad window, includes providing a substrate, which is metallized with a first metallization layer; forming a dielectric layer over the first metallization layer; defining the dielectric layer with a first mask to form a via; forming a plug in the via; forming a second metallization layer over the plug and the dielectric layer; patterning the second metallization layer to expose the dielectric layer; forming a passivation layer over the second metallization layer; and defining the passivation layer with the first mask to form the bonding pad window. This improves and simplifies the formation of a bonding pad window. For example, the process of forming a mask, which is used to form the bonding pad window, can be omitted. The previous via mask is used to form the bonding pad window and the internal circuit probing window at the same time.
    Type: Grant
    Filed: September 11, 1997
    Date of Patent: December 22, 1998
    Assignee: United Microelectronics Corp.
    Inventors: Chen-Chung Hsu, Larry Lin
  • Patent number: 5851912
    Abstract: An method for the fabrication of an ohmic, low resistance contact to heavily doped silicon is described using a CVD deposited tungsten plug provided with Ti/TiN barrier metallurgy. The method provides for surface planarization using a borophosphosilicate glass insulator deposited on the silicon. After the glass is flowed to planarize its surface, contact holes are patterned in the glass and the exposed silicon substrate contacts are implanted. Instead of activating the implant with a rapid-thermal-anneal at this point the Ti/TiN barrier metallurgy is applied first followed by the anneal. This provides support for the glass at the upper corners of the contact opening during the anneal and thus prevents them from deforming and encroaching into the contact hole opening.
    Type: Grant
    Filed: March 10, 1997
    Date of Patent: December 22, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhon-Jhy Liaw, Jin-Yuan Lee, Ming-Chang Teng