Insulator Formed By Reaction With Conductor (e.g., Oxidation, Etc.) Patents (Class 438/635)
  • Patent number: 10319616
    Abstract: An untreated semiconductor wafer is transferred from an indexer unit to a treatment chamber via a first cool chamber and a transfer chamber in this order. A treated semiconductor wafer subjected to heating treatment in the treatment chamber is transferred to the indexer unit via the transfer chamber and the first cool chamber in this order. For a predetermined time after an untreated semiconductor wafer is transferred into the first cool chamber, nitrogen gas is supplied into the first cool chamber at a large supply flow rate and exhausting from the first cool chamber is performed at a large exhaust flow rate. An oxygen concentration in the first cool chamber sharply decreases to enable the semiconductor wafer after the heating treatment to be prevented from being oxidized.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: June 11, 2019
    Assignee: Screen Holdings Co., Ltd.
    Inventor: Akitsugu Ueda
  • Patent number: 9368602
    Abstract: Methods for fabricating an IGZO layer and fabricating TFT are provided in the present invention. The method for fabricating TFT includes the following steps: (1) depositing an IGZO layer and forming a surface oxidizing gas protective layer on the IGZO layer; (2) coating the IGZO layer with a photoresist, and then subjecting the photoresist to an exposing and developing process to form a photoresist pattern; and (3) subjecting the IGZO layer to an etching process, and then removing the photoresist. By forming an oxidizing gas protective layer, the present methods for fabricating an IGZO layer and fabricating TFT can effectively reduce the effect of hydrogen atom on IGZO layer and avoid the change of IGZO layer from semiconductor to conductor, thereby improving the stability of the IGZO layer and thus the TFT, and reducing the negative bias of threshold voltage generated by the long-term continuous use of the device.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: June 14, 2016
    Assignee: EverDisplay Optronics (Shanghai) Limited
    Inventors: Chia-chi Huang, Min-ching Hsu, Hsueh-ming Tsai, Wen-xia Zuo
  • Patent number: 9337036
    Abstract: Effects of copper oxide formation in semiconductor manufacture are mitigated by etching with sulfide plasmas. The plasmas form protective copper sulfide films on copper surfaces and prevent copper oxide formation. When copper oxide formation does occur, the sulfide plasmas are able to transform the copper oxide into acceptable or more conductive copper compounds. Non-oxide copper compounds are removed using clear wet strips.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: May 10, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Zusing Yang, Hong-Ji Lee
  • Patent number: 9224686
    Abstract: A single damascene interconnect structure which includes a first layer of a first dielectric material having a first filled opening that has a sidewall layer which includes a compound of a metal, O, and Si such that the metal is Mn, Ti and Al, and with Cu filling the first filled opening. The compound is in direct contact with the first dielectric material. Also included is a second layer that includes a second dielectric material having a second filled opening that has a barrier layer of a refractory material with Cu filling the second filled opening. The first layer is adjacent to the second layer and the first filled opening is aligned with the second filled opening so that one of the first and second filled openings is a via and the other of the first and second filled openings is a trench.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: December 29, 2015
    Assignee: International Business Machines Corporation
    Inventors: Shyng-Tsong Chen, Daniel C. Edelstein, Takeshi Nogami
  • Patent number: 9184296
    Abstract: The semiconductor device includes an oxide semiconductor film having a first region and a pair of second regions facing each other with the first region provided therebetween, a gate insulating film over the oxide semiconductor film, and a first electrode overlapping with the first region, over the gate insulating film. The first region is a non-single-crystal oxide semiconductor region including a c-axis-aligned crystal portion. The pair of second regions is an oxide semiconductor region containing dopant and including a plurality of crystal portions.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: November 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Shinji Ohno, Yuichi Sato, Masahiro Takahashi, Hideyuki Kishida
  • Patent number: 9108351
    Abstract: An anodized layer formation method of an embodiment of the present invention includes the step a of providing an aluminum film which is formed on a first principal surface of a support and the step b of anodizing a surface of the aluminum film to form a porous alumina layer which has a plurality of minute recessed portions. In the step a, a second principal surface of the support which is opposite to the first principal surface is provided with a low heat conduction member that has a predetermined pattern. According to an embodiment of the present invention, a porous alumina layer can be formed which includes regions of different minute structures in the predetermined pattern.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: August 18, 2015
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kenichiro Nakamatsu, Hidekazu Hayashi, Kiyoshi Minoura, Akinobu Isurugi
  • Patent number: 9064802
    Abstract: A method of manufacturing a semiconductor device includes forming a metal oxide on a semiconductor substrate, forming a gate electrode film on the metal oxide, and executing a thermal treatment on the semiconductor substrate provided with the metal oxide and the gate electrode film to crystallize the metal oxide.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: June 23, 2015
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Yukimune Watanabe
  • Patent number: 9040413
    Abstract: A nonvolatile memory device contains a resistive switching memory element with improved device switching performance and lifetime by custom tailoring the average concentration of defects in the resistive switching film and methods of forming the same. The nonvolatile memory element includes a first electrode layer, a second electrode layer, and a resistive switching layer disposed between the first electrode layer and the second electrode layer. The resistive switching layer comprises a first sub-layer and a second sub-layer, wherein the first sub-layer has more defects than the first sub-layer. A method includes forming a first sub-layer on the first electrode layer by a first ALD process and forming a second sub-layer on the first sub-layer by a second ALD process, where the first sub-layer has a different amount of defects than the second sub-layer.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: May 26, 2015
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Randall J. Higuchi, Chien-Lan Hsueh, Yun Wang
  • Publication number: 20150132944
    Abstract: An electronic device includes a semiconductor memory circuit. The semiconductor memory circuit includes a plurality of first conductive lines which includes an anti-oxidation layer on both sides of each first conductive line, an inter-layer dielectric layer suitable for gap-filling a space between the first conductive lines, a material layer formed over the first conductive lines and the inter-layer dielectric layer and including oxygen vacancies, and a plurality of second conductive lines formed over the material layer to intersect with the first conductive lines. A first portion of the material layer where the first conductive lines and the second conductive lines overlap each other has a lower oxygen content than a second portion of the material layer where the inter-layer dielectric layer and the second conductive lines overlap each other.
    Type: Application
    Filed: May 28, 2014
    Publication date: May 14, 2015
    Applicant: SK hynix Inc.
    Inventor: Hae-Chan PARK
  • Patent number: 8980736
    Abstract: A method of manufacturing a semiconductor device may include: forming active patterns of pillar-shapes upward protruding from a substrate, the active patterns fully doped with dopants of one conductivity type; forming a gate electrode extending in one direction, the gate electrode overlapped with sidewalls of the active patterns; and forming a gate insulating layer between the gate electrode and the active patterns.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong Un Kim
  • Patent number: 8946075
    Abstract: One method includes performing a first etching process to form a contact opening in a layer of insulating material that exposes a portion of a gate structure of the transistor, performing a second etching process on the exposed portion of the gate structure to thereby define a gate recess, selectively forming an oxidizable material in the gate recess, converting the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to a source/drain region. A device includes an oxide material that is positioned at least partially in a recess formed in a gate structure, wherein the oxide material contacts a conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: February 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xiuyu Cai, Ruilong Xie, John A. Iacoponi
  • Patent number: 8940633
    Abstract: One method discloses performing an etching process to form a contact opening in a layer of insulating material above at least a portion of a source/drain, region wherein, after the completion of the etching process, a portion of a gate structure of the transistor is exposed, selectively forming an oxidizable material on the exposed gate structure, converting at least a portion of the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to the source/drain region. A novel transistor device disclosed herein includes an oxide material positioned between a conductive contact and a gate structure of the transistor, wherein the oxide material contacts the conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: January 27, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xiuyu Cai, Ruilong Xie, John A. Iacoponi
  • Patent number: 8878364
    Abstract: A method for fabricating a semiconductor device according to an embodiment, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a high melting metal film on a side wall and a bottom surface of the opening; forming a seed film of copper (Cu) on the high melting metal film; performing nitriding process after the seed film is formed; and performing electroplating process, in which a Cu film is buried in the opening while energizing the seed film after performing nitriding process.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: November 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Morita, Akitsugu Hatazaki, Kazumasa Ito, Hiroshi Toyoda
  • Patent number: 8835312
    Abstract: A method of manufacturing a semiconductor device comprises forming an interlayer insulating film on a semiconductor substrate, the interlayer insulating film including a trench, forming a work function metal layer in the trench, forming an insulating film on the work function metal layer, forming a sacrificial film on the insulating film and filling the trench, forming a sacrificial film pattern with a top surface disposed in the trench by etching the sacrificial film, forming an insulating film pattern by selectively etching a portion of the insulating film which is formed higher than the sacrificial film pattern, and forming a work function metal pattern with a top surface disposed in the trench by selectively etching a portion of the work function metal layer which is formed higher than the insulating film pattern.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ju-Yuon Kim
  • Patent number: 8796136
    Abstract: A semiconductor device is provided, which includes an annular insulation separation portion penetrating a semiconductor substrate, and an electrode penetrating the semiconductor substrate in a region surrounded by the annular insulation separation portion, wherein the insulation separation portion includes at least a first film that gives compressive stress in a depth direction on the side of a substrate, a second film that gives tensile stress in the depth direction is formed on the first film, and film thicknesses of the first and second films are adjusted so that the compressive stress and the tensile stress are almost balanced.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: August 5, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Satoru Sugiyama, Yuuta Nishioka
  • Patent number: 8753974
    Abstract: Structures and methods for the dissipation of charge build-up during the formation of cavities in semiconductor substrates.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: June 17, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Brian Griffin, Russ Benson
  • Patent number: 8742586
    Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Mizukami, Takeshi Kamigaichi
  • Patent number: 8737036
    Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: May 27, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Hanhong Chen, Nobumichi Fuchigami, Imran Hashim, Edward L. Haywood, Pragati Kumar, Sandra G. Malhotra, Monica Sawkar Mathur, Prashant B. Phatak, Sunil Shanker
  • Patent number: 8709954
    Abstract: A wafer recycling method comprises varying a temperature and pressure conditions to remove a first semiconductor layer deposited on a wafer, removing a remaining semiconductor layer on the wafer through a chemical or physical process, and washing the wafer.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: April 29, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Kyung Jun Kim, Hyo Kun Son
  • Patent number: 8697565
    Abstract: A method, and an apparatus formed thereby, to construct shallow recessed wells on top of exposed conductive vias on the surface of a semiconductor. The shallow recessed wells are subsequently filled with a conductive cap layer, such as a tantalum nitride (TaN) layer, to prevent or reduce oxidation which may otherwise occur naturally when exposed to air, or possibly occur during an under-bump metallization process.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: April 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lin-Ya Huang, Chi-Sheng Juan, Chien-Lin Tseng
  • Patent number: 8557697
    Abstract: Atomic layer deposition methods as described herein can be advantageously used to form a metal-containing layer on a substrate. For example, certain methods as described herein can form a strontium titanate layer that has low carbon content (e.g., low strontium carbonate content), which can result in layer with a high dielectric constant.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: October 15, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Bhaskar Srinivasan, John Smythe
  • Patent number: 8551851
    Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: October 8, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Hanhong Chen, Pragati Kumar, Sunil Shanker, Edward Haywood, Sandra Malhotra, Imran Hashim, Nobi Fuchigami, Prashant Phatak, Monica Mathur
  • Patent number: 8349725
    Abstract: The present invention is a method of manufacturing a semiconductor device comprising: forming a recess in an interlayer insulating film formed on a substrate surface, the recess being configured to be embedded with an upper conductive channel mainly made of copper to be electrically connected to a lower conductive channel; supplying a gas containing an organic compound of manganese, and forming a barrier layer made of a compound of manganese for preventing diffusion of copper to the interlayer insulating film, such that the barrier layer covers an exposed surface of the interlayer insulating film; after the formation of the barrier layer, supplying organic acid to the barrier layer in order to increase a ratio of manganese in the compound of manganese forming the barrier layer; after the supply of the organic acid, forming a seed layer mainly made of copper on a surface of the barrier layer; after the formation of the seed-layer, heating the substrate in order to separate out manganese from on the surface of
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: January 8, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Hiroshi Sato, Hitoshi Itoh, Kenji Matsumoto
  • Patent number: 8294202
    Abstract: A semiconductor device structure, for improving the metal gate leakage within the semiconductor device. A structure for a metal gate electrode for a n-type Field Effect Transistor includes a capping layer; a first metal layer comprising Ti and Al over the capping layer; a metal oxide layer over the first metal layer; a barrier layer over the metal oxide layer; and a second metal layer over the barrier layer.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: October 23, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko Jangjian, Szu-An Wu, Sheng-Wen Chen
  • Patent number: 8216933
    Abstract: A method of depositing a bilayer of tungsten over tungsten nitride by a plasma sputtering process in which krypton is used as the sputter working gas during the tungsten deposition. Argon may be used as the sputtering working gas during the reactive sputtering deposition of tungsten nitride. The beneficial effect of reduction of tungsten resistivity is increased when the thickness of the tungsten layer is less than 50 nm and further increased when less than 35 nm. The method may be used in forming a gate stack including a polysilicon layer over a gate oxide layer over a silicon gate region of a MOS transistor in which the tungsten nitride acts as a barrier. A plasma sputter chamber in which the invention may be practiced includes gas sources of krypton, argon, and nitrogen.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: July 10, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Wei D. Wang, Srinivas Gandikota, Kishore Lavu
  • Patent number: 8183150
    Abstract: The present invention provides semiconductor device formed by an in situ plasma reducing process to reduce oxides or other contaminants, using a compound of nitrogen and hydrogen, typically ammonia, at relatively low temperatures prior to depositing a subsequent layer thereon. The adhesion characteristics of the layers are improved and oxygen presence is reduced compared to the typical physical sputter cleaning process of an oxide layer. This process may be particularly useful for the complex requirements of a dual damascene structure, especially with copper applications.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: May 22, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Judy H. Huang, Christopher Dennis Bencher, Sudha Rathi, Christopher S. Ngai, Bok Hoen Kim
  • Patent number: 8119524
    Abstract: A first film containing a first metal material having a diffusion preventing function for copper, a second film containing oxygen-contained copper film, a third film containing copper and a second metal material which exhibits a diffusion preventing function for copper by bonding with oxygen, and a fourth film of copper as the main material are formed in an opening formed in an insulating film, and then a barrier layer containing the first metal material, the second metal material and oxygen is formed by thermal processing between the insulating film and the fourth film.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: February 21, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Michie Sunayama, Noriyoshi Shimizu
  • Patent number: 8034705
    Abstract: A plug comprises a first insulating interlayer, a tungsten pattern and a tungsten oxide pattern. The first insulating interlayer has a contact hole formed therethrough on a substrate. The tungsten pattern is formed in the contact hole. The tungsten pattern has a top surface lower than an upper face of the first insulating interlayer. The tungsten oxide pattern is formed in the contact hole and on the tungsten pattern. The tungsten oxide pattern has a level face.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: October 11, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-Hun Choi, Chang-Ki Hong, Yoon-Ho Son, Ju-Young Jung
  • Patent number: 8021989
    Abstract: One inventive aspect is related to a method for isolating structures of a semiconductor material, comprising providing a pattern of the semiconductor material comprising at least one elevated line, defining device regions in the pattern, the device regions each comprising at least said at least one elevated line, and modifying the conductive properties of the semiconductor material outside said device regions, such that the device regions are electrically isolated.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: September 20, 2011
    Assignee: IMEC
    Inventors: Staf Verhaegen, Axel Nackaerts
  • Patent number: 7989339
    Abstract: Embodiments of the invention generally provide methods for depositing and compositions of tantalum carbide nitride materials. The methods include deposition processes that form predetermined compositions of the tantalum carbide nitride material by controlling the deposition temperature and the flow rate of a nitrogen-containing gas during a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. In one embodiment, a method for forming a tantalum-containing material on a substrate is provided which includes heating the substrate to a temperature within a process chamber, and exposing the substrate to a nitrogen-containing gas and a process gas containing a tantalum precursor gas while depositing a tantalum carbide nitride material on the substrate.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: August 2, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Kavita Shah, Haichun Yang, Schubert S. Chu
  • Patent number: 7989342
    Abstract: The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystal orientations, comprises selectively incorporating Si into only a first set of crystallites with at least one first crystal orientation, employing first process conditions, and subsequently selectively forming a first adhesion-layer portion comprising CuSi and a first diffusion-barrier-layer portion only on the first set of crystallites, thus forming a first barrier-cap portion, and subsequently selectively incorporating Si into only the second set of crystallites, employing second process conditions that differ from the first process conditions, and forming a second barrier-cap portion comprising a Si-containing second diffusion-barrier layer portion on the second set of crystallites of the interconnect element.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: August 2, 2011
    Inventors: Joaquin Torres, Laurent Gosset, Sonarith Chhun, Vincent Arnal
  • Patent number: 7968452
    Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: June 28, 2011
    Assignee: Intermolecular, Inc.
    Inventors: Hanhong Chen, Pragati Kumar, Sunil Shanker, Edward Haywood, Sandra Malhotra, Imran Hashim, Nobi Fuchigami, Prashant Phatak, Monica Mathur
  • Patent number: 7892964
    Abstract: Atomic layer deposition methods as described herein can be advantageously used to form a metal-containing layer on a substrate. For example, certain methods as described herein can form a strontium titanate layer that has low carbon content (e.g., low strontium carbonate content), which can result in layer with a high dielectric constant.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: February 22, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Bhaskar Srinivasan, John Smythe
  • Patent number: 7842603
    Abstract: A method for fabricating a semiconductor memory device includes forming an insulation layer including a contact plug over a substrate structure, forming a metal line structure over the insulation layer, the metal line structure including a patterned diffusion barrier layer and a metal line and contacting the contact plug, and oxidizing a surface of the metal line to form a passivation layer over the metal line.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: November 30, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyoung-Sik Han, Young-Jun Kim
  • Patent number: 7833900
    Abstract: The present invention discloses a method of manufacturing an integrated circuit on a semiconductor substrate having a semiconductor device provided thereon, including the steps of forming a copper layer having an overburden of a desired thickness, forming a layer of inert metal on the copper layer, annealing the copper layer and removing the layer of inert metal.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: November 16, 2010
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Lup San Leong, Yong Kong Siew, Liang Choo Hsia
  • Patent number: 7829457
    Abstract: In some embodiments, after depositing conductive material on substrates in a deposition chamber, a reducing gas is introduced into as the chamber in preparation for unloading the substrates. The deposition chamber can be a batch CVD chamber and the deposited material can be a metal nitride, e.g., a transition metal nitride such as titanium metal nitride. As part of the preparation for unloading substrates from the chamber, the substrates may be cooled and the chamber is backfilled with a reducing gas to increase the chamber pressure. It has been found that oxidants can be introduced into the chamber during this time. The introduction of a reducing gas has been found to protect exposed metal-containing films from oxidation during the backfill and/or cooling process. The reducing gas is formed of a reducing agent and a carrier gas, with the reducing agent being a minority component of the reducing gas.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: November 9, 2010
    Assignee: ASM International N.V.
    Inventors: Tatsuya Yoshimi, Rene de Blank, Jerome Noiray
  • Patent number: 7736963
    Abstract: In an embodiment, a method of forming a gate structure for a semiconductor device includes forming a preliminary gate structure on a semiconductor substrate. The preliminary gate structure includes a gate oxide pattern and a conductive pattern sequentially stacked on the substrate. Then, a re-oxidation process is performed to the substrate having the preliminary gate structure using an oxygen radical including at least one oxygen atom, so that an oxide layer is formed on a surface of the substrate and sidewalls of the preliminary gate structure to form the gate structure for a semiconductor device. The thickness of the gate oxide pattern is prevented from increasing, and the quality of the oxide layer is improved.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: June 15, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woong Lee, Young-Sub You, Hun-Hyeoung Leam, Yong-Woo Hyung, Jai-Dong Lee, Ki-Su Na, Jung-Hwan Kim
  • Patent number: 7709349
    Abstract: In one aspect, there is provided a method of manufacturing a semiconductor device that comprises placing a blocking layer, a CMP stop layer and a bulk oxide layer over an oxide cap layer that is located over gate structures and source/drains located adjacent thereto. The bulk oxide layer and the CMP stop layer are removed with a CMP process to expose the top of gate electrodes and are removed from over the source/drain areas with a wet etch. The CMP stop layer has a CMP removal rate that is less than a CMP removal rate of the bulk oxide layer and has a wet etch removal rate that is greater than a wet etch removal rate of the blocking layer.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: May 4, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Mark R. Visokay
  • Patent number: 7674724
    Abstract: An oxidizing method for an object to be processed according to the present invention includes: an arranging step of arranging a plurality of objects to be processed in a processing container whose inside can be vacuumed, the processing container having a predetermined length, a supplying unit of an oxidative gas being provided at one end of the processing container, a plurality of supplying units of a reducing gas being provided at a plurality of positions in a longitudinal direction of the processing container; an atmosphere forming step of supplying the oxidative gas and the reducing gas into the processing container in order to form an atmosphere having active oxygen species and active hydroxyl species in the processing container; and an oxidizing step of oxidizing surfaces of the plurality of objects to be processed in the atmosphere.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: March 9, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Keisuke Suzuki, Toshiyuki Ikeuchi, Kota Umezawa
  • Patent number: 7618891
    Abstract: The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: November 17, 2009
    Assignee: International Business Machines Corporation
    Inventors: Sunfei Fang, Randolph F. Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Renee T. Mo, Balasubramanian Pranatharthiharan, Jay W. Strane
  • Patent number: 7585762
    Abstract: Embodiments of the invention generally provide methods for depositing and compositions of tantalum carbide nitride materials. The methods include deposition processes that form predetermined compositions of the tantalum carbide nitride material by controlling the deposition temperature and the flow rate of a nitrogen-containing gas during a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. In one embodiment, a method for forming a tantalum-containing material on a substrate is provided which includes heating the substrate to a temperature within a process chamber, and exposing the substrate to a nitrogen-containing gas and a process gas containing a tantalum precursor gas while depositing a tantalum carbide nitride material on the substrate.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: September 8, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Kavita Shah, Haichun Yang, Schubert S. Chu
  • Patent number: 7569477
    Abstract: A method for fabricating a fine pattern in a semiconductor device includes forming a first photoresist pattern over an etch target layer, forming a first hard mask layer over a substrate structure, planarizing the first hard mask layer to form a first hard mask pattern and expose the first photoresist pattern, removing the first photoresist pattern, forming a second photoresist pattern enclosing the first hard mask pattern, forming a second hard mask layer over the substrate structure, planarizing the second hard mask layer to form a second hard mask pattern and expose the first hard mask pattern, removing the second photoresist pattern, and etching the etch target layer using the first hard mask pattern and the second hard mask pattern.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: August 4, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jung-Woo Park
  • Patent number: 7569467
    Abstract: A semiconductor device has a multi-layer wiring in which resistance against migration of the semiconductor device is raised to improve the yield. Semiconductor device 100 includes a first interconnect (wiring) 112, formed in a first interlayer insulating film 106 on a semiconductor substrate, not shown, a via 128 provided on the first interconnect (wiring) 112 so that the via is connected to the first interconnect (wiring) 112, and a different element containing electrically conductive film 114. The different element containing electrically conductive film is formed selectively on a site on the top of the first interconnect (wiring) 112 where the first wiring is contacted with the bottom of the via 128. The different element containing electrically conductive film contains a metal of a main component of the first interconnect (wiring) 112 and a different element different from the metal of the main component.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: August 4, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Hiroaki Katou
  • Patent number: 7566643
    Abstract: A programmable resistance, chalcogenide, switching or phase-change material device includes a substrate with a plurality of stacked layers including a conducting bottom composite electrode layer, an insulative layer having an opening formed therein, an active material layer deposited over both the insulative layer and the bottom composite electrode, and a top electrode layer deposited over the active material layer. The device uses a chemical or electrochemical liquid phase deposition process to selectively and conformally fill the insulative layer opening with the conductive bottom composite electrode layer. Conformally filling the conductive material within the opening reduces structural irregularities within the opening thereby increasing material density and resistivity within the device and thereby improving device performance and reducing programming current.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: July 28, 2009
    Assignee: Ovonyx, Inc.
    Inventors: Wolodymyr Czubatyi, Tyler Lowrey, Ed Spall
  • Patent number: 7491638
    Abstract: A new technique is disclosed in which a barrier/capping layer for a copper-based metal line is formed by using a thermal-chemical treatment followed by an in situ plasma-based deposition of silicon nitride and/or silicon carbon nitride. The thermal-chemical treatment is performed on the basis of an ammonium/nitrogen mixture in the absence of any plasma ambient.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: February 17, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joerg Hohage, Matthias Lehr, Volker Kahlert
  • Patent number: 7476605
    Abstract: A method for manufacturing a semiconductor device is provided, which comprises forming a first metal wiring layer above a semiconductor substrate, forming an inorganic insulating film above the first metal wiring layer, forming an organic insulating film on the inorganic insulating film, forming a recess in the organic insulating film, forming a reactive layer on the side surface of the recess, the reactive layer being capable of reaction under heat with the organic insulating film, applying a heat treatment to the reactive layer so as to permit the reactive layer to react with the organic insulating film while leaving an unreacted reactive layer, thereby allowing the reaction layer to grow on the side surface of the recess, the recess being diminished by the growth of the reaction layer, and removing the unreacted reactive layer to obtain a diminished recess.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: January 13, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Yosho
  • Patent number: 7473577
    Abstract: An electronic device includes: at least one electronic chip comprising a first coefficient of thermal expansion (CTE); and a carrier including a top side connected to the bottom side of the chip by solder bumps. The carrier further includes a second CTE that approximately matches the first CTE, and a plurality of through vias from the bottom side of the carrier to the top side of the carrier layer. Each through via comprising a collar exposed at the top surface of the carrier, a pad exposed at the bottom surface of the carrier, and a post disposed between the collar and the pad. The post extends thorough a volume of space.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: January 6, 2009
    Assignee: International Business Machines Corporation
    Inventor: Timothy J. Chainer
  • Patent number: 7425480
    Abstract: A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film, and an oxidation process using ozone is performed to sufficiently round the shape of the lower edge of the gate electrode.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: September 16, 2008
    Assignee: Kabushiki Kaisha Tohisba
    Inventors: Yoshio Ozawa, Yasumasa Suizu, Yoshitaka Tsunashima
  • Patent number: 7413985
    Abstract: By forming a copper/silicon/nitrogen alloy in a surface portion of a copper-containing region on the basis of a precursor layer, highly controllable and reliable process conditions may be established. The precursor layer may be formed on the basis of a liquid precursor solution, which may exhibit a substantially self-aligned and self-limiting deposition behavior.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: August 19, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christof Streck, Volker Kahlert
  • Publication number: 20080122121
    Abstract: A method for fabricating a semiconductor is disclosed. The method includes the steps of forming a porous insulation film and wires on the substrate, the wires embedded in the porous insulation film having a portion adjacent to the wires and a remote portion spaced apart from the wires; and applying an energy beam to the remote portion to change the structure of the porous insulation film such that an Young's modulus of the porous insulation film increased so as to substantially reinforce the strength of the porous insulation film.
    Type: Application
    Filed: November 21, 2007
    Publication date: May 29, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Shoichi Suda, Shino Tokuyo, Yoshihiro Nakata, Azuma Matsuura