Abstract: A device includes a multi-layer stack, a channel layer, a ferroelectric layer and buffer layers. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The ferroelectric layer is disposed between the channel layer and each of the plurality of conductive layers and the plurality of dielectric layers. The buffer layers include a metal oxide, and one of the buffer layers is disposed between the ferroelectric layer and each of the plurality of dielectric layers.

Abstract: A TFT includes an oxide semiconductor layer including a conductive region electrically connected to a source electrode, a conductive region electrically connected to a drain electrode, a channel region being an oxide semiconductor region that overlaps a gate electrode, and at least one resistive region being an oxide semiconductor region provided between the channel region and a conductive region adjacent to the channel region.

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

Abstract: Processes for the localized etching of films on the sidewalls of non-planar 3D features such as a trench or a FinFET array. The etch process has a first step of an angle-directed ion implant beam, with the beam being self-aligned onto a localized region on a sidewall feature, that functionalizes the region for a second step that etches the ion implanted region.

Abstract: A method of positioning nanomaterials includes patterning guiding dielectric features from a single layer of guiding dielectric material, and producing an electric field by at least one electrode disposed on a substrate that is attenuated through the guiding dielectric features to create an attractive dielectrophoretic force that guides at least one nanostructure abutting the guiding dielectric features to be positioned on a deposition surface of the substrate.

Abstract: A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

Abstract: An untreated semiconductor wafer is transferred from an indexer unit to a treatment chamber via a first cool chamber and a transfer chamber in this order. A treated semiconductor wafer subjected to heating treatment in the treatment chamber is transferred to the indexer unit via the transfer chamber and the first cool chamber in this order. For a predetermined time after an untreated semiconductor wafer is transferred into the first cool chamber, nitrogen gas is supplied into the first cool chamber at a large supply flow rate and exhausting from the first cool chamber is performed at a large exhaust flow rate. An oxygen concentration in the first cool chamber sharply decreases to enable the semiconductor wafer after the heating treatment to be prevented from being oxidized.

Abstract: Methods for fabricating an IGZO layer and fabricating TFT are provided in the present invention. The method for fabricating TFT includes the following steps: (1) depositing an IGZO layer and forming a surface oxidizing gas protective layer on the IGZO layer; (2) coating the IGZO layer with a photoresist, and then subjecting the photoresist to an exposing and developing process to form a photoresist pattern; and (3) subjecting the IGZO layer to an etching process, and then removing the photoresist. By forming an oxidizing gas protective layer, the present methods for fabricating an IGZO layer and fabricating TFT can effectively reduce the effect of hydrogen atom on IGZO layer and avoid the change of IGZO layer from semiconductor to conductor, thereby improving the stability of the IGZO layer and thus the TFT, and reducing the negative bias of threshold voltage generated by the long-term continuous use of the device.

Abstract: Effects of copper oxide formation in semiconductor manufacture are mitigated by etching with sulfide plasmas. The plasmas form protective copper sulfide films on copper surfaces and prevent copper oxide formation. When copper oxide formation does occur, the sulfide plasmas are able to transform the copper oxide into acceptable or more conductive copper compounds. Non-oxide copper compounds are removed using clear wet strips.

Abstract: A single damascene interconnect structure which includes a first layer of a first dielectric material having a first filled opening that has a sidewall layer which includes a compound of a metal, O, and Si such that the metal is Mn, Ti and Al, and with Cu filling the first filled opening. The compound is in direct contact with the first dielectric material. Also included is a second layer that includes a second dielectric material having a second filled opening that has a barrier layer of a refractory material with Cu filling the second filled opening. The first layer is adjacent to the second layer and the first filled opening is aligned with the second filled opening so that one of the first and second filled openings is a via and the other of the first and second filled openings is a trench.

Abstract: The semiconductor device includes an oxide semiconductor film having a first region and a pair of second regions facing each other with the first region provided therebetween, a gate insulating film over the oxide semiconductor film, and a first electrode overlapping with the first region, over the gate insulating film. The first region is a non-single-crystal oxide semiconductor region including a c-axis-aligned crystal portion. The pair of second regions is an oxide semiconductor region containing dopant and including a plurality of crystal portions.

Abstract: An anodized layer formation method of an embodiment of the present invention includes the step a of providing an aluminum film which is formed on a first principal surface of a support and the step b of anodizing a surface of the aluminum film to form a porous alumina layer which has a plurality of minute recessed portions. In the step a, a second principal surface of the support which is opposite to the first principal surface is provided with a low heat conduction member that has a predetermined pattern. According to an embodiment of the present invention, a porous alumina layer can be formed which includes regions of different minute structures in the predetermined pattern.

Abstract: A method of manufacturing a semiconductor device includes forming a metal oxide on a semiconductor substrate, forming a gate electrode film on the metal oxide, and executing a thermal treatment on the semiconductor substrate provided with the metal oxide and the gate electrode film to crystallize the metal oxide.

Abstract: A nonvolatile memory device contains a resistive switching memory element with improved device switching performance and lifetime by custom tailoring the average concentration of defects in the resistive switching film and methods of forming the same. The nonvolatile memory element includes a first electrode layer, a second electrode layer, and a resistive switching layer disposed between the first electrode layer and the second electrode layer. The resistive switching layer comprises a first sub-layer and a second sub-layer, wherein the first sub-layer has more defects than the first sub-layer. A method includes forming a first sub-layer on the first electrode layer by a first ALD process and forming a second sub-layer on the first sub-layer by a second ALD process, where the first sub-layer has a different amount of defects than the second sub-layer.

Abstract: An electronic device includes a semiconductor memory circuit. The semiconductor memory circuit includes a plurality of first conductive lines which includes an anti-oxidation layer on both sides of each first conductive line, an inter-layer dielectric layer suitable for gap-filling a space between the first conductive lines, a material layer formed over the first conductive lines and the inter-layer dielectric layer and including oxygen vacancies, and a plurality of second conductive lines formed over the material layer to intersect with the first conductive lines. A first portion of the material layer where the first conductive lines and the second conductive lines overlap each other has a lower oxygen content than a second portion of the material layer where the inter-layer dielectric layer and the second conductive lines overlap each other.

Abstract: A method of manufacturing a semiconductor device may include: forming active patterns of pillar-shapes upward protruding from a substrate, the active patterns fully doped with dopants of one conductivity type; forming a gate electrode extending in one direction, the gate electrode overlapped with sidewalls of the active patterns; and forming a gate insulating layer between the gate electrode and the active patterns.

Abstract: One method includes performing a first etching process to form a contact opening in a layer of insulating material that exposes a portion of a gate structure of the transistor, performing a second etching process on the exposed portion of the gate structure to thereby define a gate recess, selectively forming an oxidizable material in the gate recess, converting the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to a source/drain region. A device includes an oxide material that is positioned at least partially in a recess formed in a gate structure, wherein the oxide material contacts a conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure.

Abstract: One method discloses performing an etching process to form a contact opening in a layer of insulating material above at least a portion of a source/drain, region wherein, after the completion of the etching process, a portion of a gate structure of the transistor is exposed, selectively forming an oxidizable material on the exposed gate structure, converting at least a portion of the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to the source/drain region. A novel transistor device disclosed herein includes an oxide material positioned between a conductive contact and a gate structure of the transistor, wherein the oxide material contacts the conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure.

Abstract: A method for fabricating a semiconductor device according to an embodiment, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a high melting metal film on a side wall and a bottom surface of the opening; forming a seed film of copper (Cu) on the high melting metal film; performing nitriding process after the seed film is formed; and performing electroplating process, in which a Cu film is buried in the opening while energizing the seed film after performing nitriding process.

Abstract: A method of manufacturing a semiconductor device comprises forming an interlayer insulating film on a semiconductor substrate, the interlayer insulating film including a trench, forming a work function metal layer in the trench, forming an insulating film on the work function metal layer, forming a sacrificial film on the insulating film and filling the trench, forming a sacrificial film pattern with a top surface disposed in the trench by etching the sacrificial film, forming an insulating film pattern by selectively etching a portion of the insulating film which is formed higher than the sacrificial film pattern, and forming a work function metal pattern with a top surface disposed in the trench by selectively etching a portion of the work function metal layer which is formed higher than the insulating film pattern.

Abstract: A semiconductor device is provided, which includes an annular insulation separation portion penetrating a semiconductor substrate, and an electrode penetrating the semiconductor substrate in a region surrounded by the annular insulation separation portion, wherein the insulation separation portion includes at least a first film that gives compressive stress in a depth direction on the side of a substrate, a second film that gives tensile stress in the depth direction is formed on the first film, and film thicknesses of the first and second films are adjusted so that the compressive stress and the tensile stress are almost balanced.

Abstract: Structures and methods for the dissipation of charge build-up during the formation of cavities in semiconductor substrates.

Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle.

Abstract: A wafer recycling method comprises varying a temperature and pressure conditions to remove a first semiconductor layer deposited on a wafer, removing a remaining semiconductor layer on the wafer through a chemical or physical process, and washing the wafer.

Abstract: A method, and an apparatus formed thereby, to construct shallow recessed wells on top of exposed conductive vias on the surface of a semiconductor. The shallow recessed wells are subsequently filled with a conductive cap layer, such as a tantalum nitride (TaN) layer, to prevent or reduce oxidation which may otherwise occur naturally when exposed to air, or possibly occur during an under-bump metallization process.

Abstract: Atomic layer deposition methods as described herein can be advantageously used to form a metal-containing layer on a substrate. For example, certain methods as described herein can form a strontium titanate layer that has low carbon content (e.g., low strontium carbonate content), which can result in layer with a high dielectric constant.

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle.

Abstract: The present invention is a method of manufacturing a semiconductor device comprising: forming a recess in an interlayer insulating film formed on a substrate surface, the recess being configured to be embedded with an upper conductive channel mainly made of copper to be electrically connected to a lower conductive channel; supplying a gas containing an organic compound of manganese, and forming a barrier layer made of a compound of manganese for preventing diffusion of copper to the interlayer insulating film, such that the barrier layer covers an exposed surface of the interlayer insulating film; after the formation of the barrier layer, supplying organic acid to the barrier layer in order to increase a ratio of manganese in the compound of manganese forming the barrier layer; after the supply of the organic acid, forming a seed layer mainly made of copper on a surface of the barrier layer; after the formation of the seed-layer, heating the substrate in order to separate out manganese from on the surface of

Abstract: A semiconductor device structure, for improving the metal gate leakage within the semiconductor device. A structure for a metal gate electrode for a n-type Field Effect Transistor includes a capping layer; a first metal layer comprising Ti and Al over the capping layer; a metal oxide layer over the first metal layer; a barrier layer over the metal oxide layer; and a second metal layer over the barrier layer.

Abstract: A method of depositing a bilayer of tungsten over tungsten nitride by a plasma sputtering process in which krypton is used as the sputter working gas during the tungsten deposition. Argon may be used as the sputtering working gas during the reactive sputtering deposition of tungsten nitride. The beneficial effect of reduction of tungsten resistivity is increased when the thickness of the tungsten layer is less than 50 nm and further increased when less than 35 nm. The method may be used in forming a gate stack including a polysilicon layer over a gate oxide layer over a silicon gate region of a MOS transistor in which the tungsten nitride acts as a barrier. A plasma sputter chamber in which the invention may be practiced includes gas sources of krypton, argon, and nitrogen.

Abstract: The present invention provides semiconductor device formed by an in situ plasma reducing process to reduce oxides or other contaminants, using a compound of nitrogen and hydrogen, typically ammonia, at relatively low temperatures prior to depositing a subsequent layer thereon. The adhesion characteristics of the layers are improved and oxygen presence is reduced compared to the typical physical sputter cleaning process of an oxide layer. This process may be particularly useful for the complex requirements of a dual damascene structure, especially with copper applications.

Abstract: A first film containing a first metal material having a diffusion preventing function for copper, a second film containing oxygen-contained copper film, a third film containing copper and a second metal material which exhibits a diffusion preventing function for copper by bonding with oxygen, and a fourth film of copper as the main material are formed in an opening formed in an insulating film, and then a barrier layer containing the first metal material, the second metal material and oxygen is formed by thermal processing between the insulating film and the fourth film.

Abstract: A plug comprises a first insulating interlayer, a tungsten pattern and a tungsten oxide pattern. The first insulating interlayer has a contact hole formed therethrough on a substrate. The tungsten pattern is formed in the contact hole. The tungsten pattern has a top surface lower than an upper face of the first insulating interlayer. The tungsten oxide pattern is formed in the contact hole and on the tungsten pattern. The tungsten oxide pattern has a level face.

Abstract: One inventive aspect is related to a method for isolating structures of a semiconductor material, comprising providing a pattern of the semiconductor material comprising at least one elevated line, defining device regions in the pattern, the device regions each comprising at least said at least one elevated line, and modifying the conductive properties of the semiconductor material outside said device regions, such that the device regions are electrically isolated.

Abstract: The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystal orientations, comprises selectively incorporating Si into only a first set of crystallites with at least one first crystal orientation, employing first process conditions, and subsequently selectively forming a first adhesion-layer portion comprising CuSi and a first diffusion-barrier-layer portion only on the first set of crystallites, thus forming a first barrier-cap portion, and subsequently selectively incorporating Si into only the second set of crystallites, employing second process conditions that differ from the first process conditions, and forming a second barrier-cap portion comprising a Si-containing second diffusion-barrier layer portion on the second set of crystallites of the interconnect element.

Abstract: Embodiments of the invention generally provide methods for depositing and compositions of tantalum carbide nitride materials. The methods include deposition processes that form predetermined compositions of the tantalum carbide nitride material by controlling the deposition temperature and the flow rate of a nitrogen-containing gas during a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. In one embodiment, a method for forming a tantalum-containing material on a substrate is provided which includes heating the substrate to a temperature within a process chamber, and exposing the substrate to a nitrogen-containing gas and a process gas containing a tantalum precursor gas while depositing a tantalum carbide nitride material on the substrate.

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle.

Abstract: Atomic layer deposition methods as described herein can be advantageously used to form a metal-containing layer on a substrate. For example, certain methods as described herein can form a strontium titanate layer that has low carbon content (e.g., low strontium carbonate content), which can result in layer with a high dielectric constant.

Abstract: A method for fabricating a semiconductor memory device includes forming an insulation layer including a contact plug over a substrate structure, forming a metal line structure over the insulation layer, the metal line structure including a patterned diffusion barrier layer and a metal line and contacting the contact plug, and oxidizing a surface of the metal line to form a passivation layer over the metal line.

Abstract: The present invention discloses a method of manufacturing an integrated circuit on a semiconductor substrate having a semiconductor device provided thereon, including the steps of forming a copper layer having an overburden of a desired thickness, forming a layer of inert metal on the copper layer, annealing the copper layer and removing the layer of inert metal.

Abstract: In some embodiments, after depositing conductive material on substrates in a deposition chamber, a reducing gas is introduced into as the chamber in preparation for unloading the substrates. The deposition chamber can be a batch CVD chamber and the deposited material can be a metal nitride, e.g., a transition metal nitride such as titanium metal nitride. As part of the preparation for unloading substrates from the chamber, the substrates may be cooled and the chamber is backfilled with a reducing gas to increase the chamber pressure. It has been found that oxidants can be introduced into the chamber during this time. The introduction of a reducing gas has been found to protect exposed metal-containing films from oxidation during the backfill and/or cooling process. The reducing gas is formed of a reducing agent and a carrier gas, with the reducing agent being a minority component of the reducing gas.

Abstract: In an embodiment, a method of forming a gate structure for a semiconductor device includes forming a preliminary gate structure on a semiconductor substrate. The preliminary gate structure includes a gate oxide pattern and a conductive pattern sequentially stacked on the substrate. Then, a re-oxidation process is performed to the substrate having the preliminary gate structure using an oxygen radical including at least one oxygen atom, so that an oxide layer is formed on a surface of the substrate and sidewalls of the preliminary gate structure to form the gate structure for a semiconductor device. The thickness of the gate oxide pattern is prevented from increasing, and the quality of the oxide layer is improved.

Abstract: In one aspect, there is provided a method of manufacturing a semiconductor device that comprises placing a blocking layer, a CMP stop layer and a bulk oxide layer over an oxide cap layer that is located over gate structures and source/drains located adjacent thereto. The bulk oxide layer and the CMP stop layer are removed with a CMP process to expose the top of gate electrodes and are removed from over the source/drain areas with a wet etch. The CMP stop layer has a CMP removal rate that is less than a CMP removal rate of the bulk oxide layer and has a wet etch removal rate that is greater than a wet etch removal rate of the blocking layer.

Abstract: An oxidizing method for an object to be processed according to the present invention includes: an arranging step of arranging a plurality of objects to be processed in a processing container whose inside can be vacuumed, the processing container having a predetermined length, a supplying unit of an oxidative gas being provided at one end of the processing container, a plurality of supplying units of a reducing gas being provided at a plurality of positions in a longitudinal direction of the processing container; an atmosphere forming step of supplying the oxidative gas and the reducing gas into the processing container in order to form an atmosphere having active oxygen species and active hydroxyl species in the processing container; and an oxidizing step of oxidizing surfaces of the plurality of objects to be processed in the atmosphere.

Abstract: The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.

Abstract: Embodiments of the invention generally provide methods for depositing and compositions of tantalum carbide nitride materials. The methods include deposition processes that form predetermined compositions of the tantalum carbide nitride material by controlling the deposition temperature and the flow rate of a nitrogen-containing gas during a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. In one embodiment, a method for forming a tantalum-containing material on a substrate is provided which includes heating the substrate to a temperature within a process chamber, and exposing the substrate to a nitrogen-containing gas and a process gas containing a tantalum precursor gas while depositing a tantalum carbide nitride material on the substrate.

Abstract: A semiconductor device has a multi-layer wiring in which resistance against migration of the semiconductor device is raised to improve the yield. Semiconductor device 100 includes a first interconnect (wiring) 112, formed in a first interlayer insulating film 106 on a semiconductor substrate, not shown, a via 128 provided on the first interconnect (wiring) 112 so that the via is connected to the first interconnect (wiring) 112, and a different element containing electrically conductive film 114. The different element containing electrically conductive film is formed selectively on a site on the top of the first interconnect (wiring) 112 where the first wiring is contacted with the bottom of the via 128. The different element containing electrically conductive film contains a metal of a main component of the first interconnect (wiring) 112 and a different element different from the metal of the main component.

Abstract: A method for fabricating a fine pattern in a semiconductor device includes forming a first photoresist pattern over an etch target layer, forming a first hard mask layer over a substrate structure, planarizing the first hard mask layer to form a first hard mask pattern and expose the first photoresist pattern, removing the first photoresist pattern, forming a second photoresist pattern enclosing the first hard mask pattern, forming a second hard mask layer over the substrate structure, planarizing the second hard mask layer to form a second hard mask pattern and expose the first hard mask pattern, removing the second photoresist pattern, and etching the etch target layer using the first hard mask pattern and the second hard mask pattern.