Abstract: A method for forming a reduced size contact hole over a structure.

Abstract: A method of manufacturing a semiconductor device comprising the steps of, forming a diffusion-preventing thin film on a substrate, performing a first vapor deposition by supplying a source gas comprising a copper-containing organometallic compound and an oxidizing gas over the diffusion-preventing thin film thereby to allow a first conductive thin film containing copper as a main component and a trace of oxygen to be grown through a chemical vapor deposition, performing a second vapor deposition by supplying the source gas without supplying the oxidizing gas thereby to allow a second conductive thin film mainly containing copper to be grown through a chemical vapor deposition, and heat-treating the first and second conductive thin films at a temperature which is higher than those employed in the first and second vapor depositions.

Abstract: On a semiconductor substrate, an SiO.sub.2 layer as an insulating layer and an intermediate insulating layer are stacked successively. The intermediate insulating layer selectively has an opening portion and a copper wiring is formedwithin the opening portion. The copper wiring is covered with an anti-oxidation layer. The anti-oxidation layer is formed of copper sulfide so that it becomes unnecessary to form another anti-oxidation layer which does not contain copper, the treatment in the vacuum can be simplified or thermal treatment step at high temperatures can be omitted.

Abstract: A process for manufacturing an electronic interconnect structure, the process including the steps of depositing an adhesion metal layer over a dielectric material surface having at least one exposed aluminum surface; depositing a barrier metal layer over the adhesion metal layer; depositing a first layer of aluminum over the barrier metal layer; depositing an intermediate barrier metal layer over the first layer of aluminum; applying a photoresist layer on top of the intermediate barrier metal layer; exposing and developing the photoresist layer; removing the exposed barrier metal and photoresist layer, leaving a layer of barrier metal over the aluminum layer; converting those portions of the layer of aluminum which are not covered by barrier metal to a porous aluminum oxide by porous anodization; removing the porous aluminum oxide; and removing the exposed barrier metal and adhesion metal layers to leave exposed patterned aluminum, and an electronic interconnect structure manufactured by this method.

Abstract: A method of forming minimal gaps or spaces in a polysilicon conductive lines pattern for increasing the density of integrated circuits by converting an area of the size of the desired gap or space in the polysilicon to silicon oxide, followed by removing the silicon oxide. The preferred method is to selectively ion implant oxygen into the polysilicon and annealing to convert the oxygen implanted polysilicon to silicon oxide. As an alternative method, an opening in an insulating layer overlying the conductive line is first formed by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening and using the sidewalls as a mask to blanket implant oxygen through the reduced opening and into the exposed polysilicon conductive line. After annealing, the implanted polysilicon converted to silicon oxide and removed to form a gap or space in the polysilicon conductive line pattern substantially equal in size to the reduced opening.

Abstract: There is disclosed a manufacturing method of highly integrated circuits with thin-film transistors (TFTs) for use as peripheral driver circuitry in active-matrix liquid crystal display (LCD) panel with a pixel array each having a charge transfer control TFT, capable of facilitating formation of contact holes otherwise being difficult in cases where an anode oxide film is formed on gate electrodes of TFTs and lead wires both of which are made of anodizable metal, such as aluminum. The method includes execution of anodization while causing a resist mask to be disposed on part of the lead wire and electrode made of aluminum, thereby partly eliminating formation of the anode oxide film on the lead wire and electrode. At a later step of fabrication, each contact is formed by use of such portion that has no anode oxide film formed thereon. This may allow aluminum to be employed as lead wires while enabling easy fabrication of contacts therefor.

Abstract: A method for fabricating copper-aluminum metallization utilizing the technique of electroless copper deposition is described. The method provides a self-encapsulated copper-aluminum metallization structure.

Abstract: A semiconductor device comprising a thin film transistor, and a process for fabricating the same, the process comprising: a first step of forming an island-like semiconductor layer, a gate insulating film covering the semiconductor layer, and a gate electrode comprising a material containing aluminum as the principal component formed on the gate insulating film; a second step of introducing impurities into the semiconductor layer in a self-aligned manner by using the gate electrode as the mask; a third step of forming an interlayer dielectric to cover the gate electrode, and forming a contact hole in at least one of source and drain; a fourth step of forming over the entire surface, a film containing aluminum as the principal component, and then forming an anodic oxide film by anodically oxidizing the film containing aluminum as the principal component; a fifth step of etching the film containing aluminum as the principal component and the anodic oxide film, thereby forming a second layer interconnection cont

Abstract: A process for forming a multilevel electronic interconnect structure, the electronic interconnect structure having level conductive paths parallel to a substrate and interlevel electrical interconnections perpendicular to the substrate, the process comprising providing a main aluminum layer over the substrate surface, defining level conductive paths by forming a blocking mask on the main aluminum layer, the blocking mask leaving exposed areas corresponding to the level conductive paths, carrying out a barrier anodization process on the main aluminum layer to form a surface barrier oxide over the level conductive paths, removing the blocking mask, providing an upper aluminum layer over the main aluminum layer, defining interlevel interconnections by forming a blocking mask on the upper aluminum layer, the blocking mask covering areas corresponding to the interlevel interconnections, and subjecting the main and upper aluminum layers to porous anodization.

Abstract: In a thin-film insulated gate type field effect transistor having a metal gate in which the surface of the gate electrode is subjected to anodic oxidation, a silicon nitride film is provided so as to be interposed between the gate electrode and the gate insulating film to prevent invasion of movable ions into a channel, and also to prevent the breakdown of the gate insulating film due to a potential difference between the gate electrode and the channel region. By coating a specific portion of the gate electrode with metal material such as chrome or the like for the anodic oxidation, and then removing only the metal material such as chrome or the like together with the anodic oxide of the metal material such as chrome or the like, an exposed portion of metal gate (e.g. aluminum) is formed, and an upper wiring is connected to the exposed portion.

Abstract: It is intended to reduce occurrences of interlayer short-circuiting due to pinholes existing in an interlayer insulating film particularly in a circuit formed on an insulating substrate. A wiring line mainly made of an anodizable metal such as aluminum, tantalum, titanium, or the like is formed on an insulating surface, and an interlayer insulating film is so formed as to cover the metal wiring line. The substrate is then immersed in an electrolyte of, for instance, ammonium tartrate. Portions of the metal wiring line which are exposed by the pinholes of the interlayer insulating film are selectively anodized by allowing a current to flow through the wiring line by using it as one of the electrodes and gradually increasing a voltage difference between the wiring line and the opposed electrode. Thus, insulation performance of the interlayer insulating film is improved.

Abstract: An integrated circuit using conductive interconnects made of aluminum or a material consisting chiefly of aluminum. Defects due to hillocks and whiskers are prevented. The integrated circuit is composed of TFTs. Gate interconnects are made of aluminum. Before a metallization film for forming the gate interconnects is patterned, slits are formed in locations where crosstalks and shorts are likely to occur by generation of hillocks and whiskers. The surfaces inside the slits are anodized. The conductive interconnects are formed, using the locations provided with the slits. In this way, during the anodization, unwanted stress is prevented. Furthermore, it is unlikely that a required electric current cannot be supplied for the anodization because of excessive complexity of the interconnection pattern.

Abstract: A method of forming a side contact in a semiconductor device wherein a first insulating layer, first conductive and second insulating layer are formed over a substrate, and a contact hole through these layers exposes a portion of the substrate and a side edge of the first conductive layer. A refractory metal layer being formed in the contact hole, such that the natural oxide layer is changed into a conductive material by reaction with the refractory metal layer during a subsequent process step.

Abstract: A method for fabricating a capacitor of a semiconductor device, which is capable improving the chemical and thermal stability of lower electrodes.

Abstract: In a semiconductor integrated circuit for forming an offset gate structure by utilizing an anodic oxidation film fabricated around a gate electrode, even when a length of a gate line becomes long, the anodic oxidation film can be made uniform, and also electric characteristics of thin-film transistors can be matched with each other. In a semiconductor integrated circuit manufacturing method, a large number of insulated gate type field-effect transistors are connected with respect to a single gate line.

Abstract: The invention provides a method for producing wiring and contacts in an integrated circuit including the steps of forming insulated gate components on a semiconductor substrate; applying a photo-reducible dielectric layer to cover the substrate; etching holes and forming contacts; photo-reducing the dielectric to increase its conductivity; covering the resulting structure with an interconnect layer; etching the interconnect layer to define wiring in electrical contact with the contacts; and oxidizing the dielectric to reduce its conductivity.

Abstract: A resist mask is formed on an electrode mainly made of aluminum. An anodic oxide film is formed on the electrode excluding the masked region by performing anodization in an electrolyte. A contact hole can easily be formed in the masked region because the anodic oxide film is not formed there. By removing a portion of the gate electrode which corresponds to an opening in forming a contact electrode, the gate electrode can be divided at the same time as the contact electrode is formed.

Abstract: A wiring formed on a substrate is oxidized and the oxide is used as a mask for forming source and drain impurity regions of a transistor, or as a material for insulating wirings from each other, or as a dielectric of a capacitor. Thickness of the oxide is determined depending on purpose of the oxide.In a transistor adapted to be used in an active-matrix liquid-crystal display, the channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.

Abstract: A process for fabricating an electronic circuit by oxidizing the surroundings of a metallic interconnection such as of aluminum, tantalum, and titanium, wherein anodic oxidation is effected at a temperature not higher than room temperature, preferably, at 10.degree. C. or lower, and more preferably, at 0.degree. C. or lower. The surface oxidation rate of a metallic interconnection can be maintained constant to provide a surface free of irregularities.

Abstract: The present invention provides a method of fabrication for semiconductor devices which enables a photolithography technique in a fabrication process to have a maximal effect on the transistor characteristics. Polysilicon film 16 and silicon nitride film 17 are formed to active transistor 11 and field shield isolation transistor 12, with isotropic etching of silicon nitride film 17 carried out using a resist pattern 20 which was patterned within the minimum processing width as the mask. Then, using the pattern of silicon nitride film 17 as a mask, thermal oxidation of polysilicon film 16 is carried out. Next, after eliminating silicon nitride film 17, anisotropic etching of polysilicon film 16 is carried out using silicon oxide film 21 as a mask, silicon oxide film 21 being formed by thermal oxidation of polysilicon film 16. In this way, a contact pad 22 formed of polysilicon film 16 is completed.

Abstract: The present invention relates to a method of forming an aligned opening in a semiconductor device. A polysilicon layer is formed over the device. Then an opening is formed in the polysilicon layer by using patterning and etching. Subsequently, a thermal oxidation is performed to expand the volume of the polysilicon layer thereby narrowing the opening. The opening is smaller than the original opening generated by the patterning and etching, which will increase the accuracy of a opening.

Abstract: A process for creating a MOSFET device, using a polysilicon contact stud, in a sub-micron diameter contact hole, used to interconnect an underlying active device region, in a semiconductor substrate, and an overlying metal structure, has been developed. The process features depositing a polysilicon layer, to fill a sub-micron diameter contact hole, followed by an oxygen ion implantation procedure, into regions of polysilicon that are not used for the contact stud. A subsequent anneal procedure converts the oxygen implanted regions of the polysilicon layer to a silicon oxide layer. Removal of the silicon oxide layer leaves a polysilicon contact stud, in the sub-micron diameter contact hole.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a first insulating layer having a hole on a substrate, selectively forming a conductive layer in the hole, selectively forming a second insulating layer on the first insulating layer, patterning the second insulating layer, and forming an interconnection layer in an opening portion of the second insulating layer formed by patterning so as to be electrically connected to the conductive layer.