Abstract: There is presented a semiconductor device including multiple levels of copper interconnects; wherein the surface of a copper interconnect corresponding to at least one underlying layer of another copper interconnect layer is turned into copper oxide to a thickness of 30 nm or more by oxidation conducted at the oxidation rate of 20 nm/min or less, and thereby the reflection of the exposure light from the lower-level copper interconnect is prevented, in forming by means of photolithography a trench to form a copper interconnect through damascening.

Abstract: A method of isolating an exposed conductive surface. An aluminum layer (130) is selectively formed over the exposed conductive (106) surface (e.g., Cu) but not over the surrounding dielectric (110) surface using a thermal CVD process. The aluminum layer (130) is then oxidized to form a thin isolating aluminum-oxide (108) over only the conductive surface. The isolating aluminum-oxide provides a barrier for the Cu while taking up minimal space and reducing the effective dielectric constant.

Abstract: A method an apparatus for making copper metallic interconnects for semiconductors having an oxide layer deposited in the copper in situ during the deposition of the copper within the via.

Abstract: A semiconductor device is formed by a compound film &agr;&ggr;x made of at least one element &agr; selected from metal elements and at least one element &ggr; selected from the group consisting of boron, carbon, and nitrogen on a base layer containing oxygen (O), and forming a compound film &agr;&ggr;yOz by causing the compound film &agr;&ggr;x to reduce the base layer and thereby oxidizing the compound film &agr;&ggr;x on an interface of the compound film &agr;&ggr;x and the base layer, wherein each of x and y is a ratio of the number of atoms of the element &ggr; to the number of atoms of the element &agr;, and z is a ratio of the number of atoms of the oxygen to the number of atoms of the element &agr;.

Abstract: A combined IC/Mems process forms the IC parts first, and then forms the MEMS parts. One option forms a parylene overlayer, then forms a cavity under the parylene overlayer.

Abstract: In recent years, copper wiring has emerged as a promising substitute for the aluminum wiring in integrated circuits, because copper offers lower electrical resistance and better reliability at smaller dimensions than aluminum. However, use of copper typically requires forming a diffusion barrier to prevent contamination of other parts of an integrated circuit and forming a seed layer to facilitate copper plating steps. Unfortunately, conventional methods of forming the diffusion barriers and seed layers require use of separate wafer-processing chambers, giving rise to transport delays and the introduction of defect-causing particles. Accordingly, the inventors devised unique wafer-processing chambers and methods of forming barrier and seed layers.

Abstract: A method of providing a stable interface between a metallic layer and a dielectric layer in a semiconductor device is provided. The method includes generating a remote nitrogen containing plasma and flowing activated nitrogen species, from the remote site to the location of the metallic layer. The activated nitrogen species are flowed over at least the surface of the metallic layer, where they react with the metallic surface to form a metal nitride. The treated layer can be used to provide a stable bottom electrode in a capacitor stack formation.

Abstract: A method for providing a self-aligned etch stop layer comprises the steps of providing a dielectric layer having a polycrystalline silicon (poly) plug formed therein. An aluminum layer is formed to contact the dielectric layer and the plug, then the structure is heated. Heating the aluminum and the poly results in the absorption of the aluminum overlying the plug into the poly, while the aluminum overlying the dielectric is not absorbed. The aluminum over the dielectric is oxidized which forms a self-aligned etch stop layer. Layers are formed over the aluminum oxide and are subsequently etched. The etch stops on the aluminum oxide and the poly plug.

Abstract: A conductive structure includes a conductively doped semiconductive material and an overlying WxSiyNz comprising material, where each of “x”, “y” and “z” is greater than zero. Insulative material is formed over the WxSiyNz comprising material of the conductive structure. A contact opening is etched through the insulative material and through the WxSiyNz material effective to expose the conductively doped semiconductive material. The contact opening etching includes at least one dry etch, followed by at least one wet etch, followed by at least one dry etch. At least one wet etch occurs before etching the WxSiyNz comprising material. After the contact opening etching, conductive material is formed within the contact opening in electrical connection with the conductively doped semiconductive material. Other aspects are disclosed.

Abstract: A process gas containing any one of N2 or N2O is plasmanized and then a surface of a copper wiring layer is exposed to the plasmanized process gas, whereby a surface layer portion of a copper wiring layer is reformed and made into a copper diffusion preventing layer. According to this method, a noble semiconductor device can be provided, in which, along with increasing the operation speed, the copper diffusion is suppressed.

Abstract: A method is presented for forming a liner upon spaced interconnect structures arranged upon a semiconductor topography. An oxide layer may be deposited to form the liner. The spaced interconnect structures may each include an interlevel dielectric portion arranged upon a metal interconnect portion, with gaps defined between adjacent interconnect structures. A low k dielectric material may be deposited over the interconnect structures such that the low k material substantially fills the gaps between adjacent interconnect structures. The low k dielectric material may then be planarized, preferably by chemical mechanical polishing.

Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.

Abstract: Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have begun using copper instead of aluminum to form integrated-circuit wiring, because copper offers lower electrical resistance and better reliability at smaller dimensions. However, use of copper typically requires forming a diffusion barrier to prevent contamination of other parts of an integrated circuit and forming a seed layer to facilitate copper plating steps. Unfortunately, typical diffusion barrier materials add appreciable resistance to the copper wiring, and thus negate some of the advantages of using copper. Moreover, conventional methods of forming the diffusion barriers and seed layers require use of separate wafer-processing chambers, giving rise to transport delays and the introduction of defect-causing particles.

Abstract: An interconnection system having a bottom metal layer that has a conduction layer with a sidewall and an overlying barrier layer. A lateral barrier layer is disposed adjacent the sidewall of the conduction layer, and an insulation layer is over the bottom metal layer. The insulation layer forms vias extending through the insulation layer to the bottom metal layer. A top metal layer extends through the vias to electrically contact the bottom metal layer. The overlying barrier layer and the lateral barrier layer are relatively resistant to interaction with the top metal layer as compared to the conduction layer.

Abstract: A method of isolating an exposed conductive surface. An aluminum layer (130) is selectively formed over the exposed conductive (106) surface (e.g., Cu) but not over the surrounding dielectric (110) surface using a thermal CVD process. The aluminum layer (130) is then oxidized to form a thin isolating aluminum-oxide (108) over only the conductive surface. The isolating aluminum-oxide provides a barrier for the Cu while taking up minimal space and reducing the effective dielectric constant.

Abstract: There is disclosed a method of manufacturing a semiconductor device utilizing a gate dielectric film. The present invention can obtain a (Al2O3)X—(TiO2)1−X gate dielectric film where its the dielectric constant is higher than that of Al2O3 and its leakage current characteristic is improved compared to TiO2, by depositing a Ti1−XAlXN film on a semiconductor substrate and then forming the (Al2O3)X—(TiO2)1−X gate dielectric film by oxidization process. Therefore, the present invention can implement a high-speed high-density logic device and an ultra high integration device of more than 1G DRAM class, which utilize a high dielectric material as the gate dielectric film.

Abstract: A method of forming a multiple layer damascene structure. A substrate comprising of a multi-layered stack that includes, from bottom to top, a metallic layer, a first etching stop layer, a first dielectric layer, a second etching stop layer and a second dielectric layer is provided. A photoresist layer having large area openings and vias pattern is formed over the substrate. Large area openings and vias that expose a portion of the first etching stop layer are formed in the substrate. A barrier layer that fills all the large area openings and vias is formed over the substrate. Chemical-mechanical polishing is conducted to remove a portion of the barrier layer and expose the second dielectric layer. A second photoresist having a trench pattern thereon is formed over the substrate. Using the second photoresist as a mask, etching is conducted so that the second etching stop layer around the vias is exposed. Lastly, the barrier layer is removed.

Abstract: Substrate bombardment during HDP deposition of carbon-doped silicon oxide film results in filling the gaps between metal lines with carbon-doped low k dielectric material. This leads to the placement of low k dielectric between the narrow metal lines while the films over the metal lines have higher dielectric constant due to removal of carbon from these films during ion bombardment. Films over the metal lines have properties similar to silicon dioxide and are ready for sequential integration processes.

Abstract: A method for providing a self-aligned etch stop layer comprises the steps of providing a dielectric layer having a polycrystalline silicon (poly) plug formed therein. An aluminum layer is formed to contact the dielectric layer and the plug, then the structure is heated. Heating the aluminum and the poly results in the absorption of the aluminum overlying the plug into the poly, while the aluminum overlying the dielectric is not absorbed. The aluminum over the dielectric is oxidized which forms a self-aligned etch stop layer. Layers are formed over the aluminum oxide and are subsequently etched. The etch stops on the aluminum oxide and the poly plug.

Abstract: A TiN film is selectively formed as a barrier layer on a Cu metal layer by selective removal of a Ti metal layer on the Si metal layer after the following steps of selectively forming a Si metal layer as an etching mask on an insulation film, forming a trench pattern by selective removal of the insulation film using the Si metal layer, forming a Cu metal layer in the trench pattern with the Si metal layer remained, forming the Ti metal layer on the Si metal layer and the Cu metal layer as a barrier material with a different kind of eutectic reaction with Cu from the reaction with the etching mask by heat-treatment in an atmosphere of nitrogen, and selectively nitriding the Ti metal layer on the Cu metal layer by heat-treatment of the Ti metal layer in an atmosphere of nitrogen.

Abstract: A method of making connection between an aluminum or aluminum based material and tungsten. The method includes providing an underlying region containing a layer of tungsten thereover. The underlying region is preferably a layer of titanium over which is a layer of titanium nitride. The layer of tungsten is etched back to the underlying region while exposed tungsten is retained over a portion of the underlying region. The underlying region also may contain a via therein which contains the exposed tungsten. An nitrogen-containing plasma, preferably elemental nitrogen, is then applied to the exposed tungsten and exposed underlying region and a layer of a barrier material is formed by reaction of the nitrogen in the plasma and the tungsten over the exposed tungsten. A further barrier layer, preferably titanium nitride, is optionally then applied followed by a layer of aluminum over the exposed surface, the barrier layer isolating the layer of aluminum from the tungsten.

Abstract: A plug is formed of polysilicon, or other oxidizable conductor. Chemical-mechanical polishing is performed, with a polish stop layer defining the top of the dielectric layer. The upper portion of the polysilicon is oxidized to a controlled depth, then the oxidized portion is removed by an etch, followed by removal of the polish stop layer. The plug thus formed protrudes a controllable distance above the surrounding dielectric, providing good contact to subsequent conductive layers.

Abstract: Disclosed is a method for manufacturing a metal oxide semiconductor FET (MOSFET), which utilizes a low-temperature liquid phase oxidation for III-V group. The method includes the steps of (a) providing a substrate, (b) forming an epitaxial layer on the substrate, (c) defining and forming a drain and a source on a portion of the epitaxial layer, (d) forming a recess in an another portion of the epitaxial layer, (e) forming an oxide layer on a surface of the recess by relatively low-temperature oxidation, and (f) forming a gate on a portion of the oxide layer between the drain and source. In addition, the method further includes two selective procedures, that is, a synchronic sulfurated passivation process which can be performed with the growth of the oxide film simultaneously, and a rapid thermal annealing (RTA) process.

Abstract: A method of film processing comprises forming an integrated titanium/titanium nitride (Ti/TiN) film structure having an intermediate layer. The intermediate layer comprises species containing Si, and preferably containing Si and Ti, such as titanium silicide (TiSix), or TiSixOy, among others. The intermediate layer protects the underlying Ti film against chemical attack during subsequent TiN deposition using a titanium tetrachloride (TiCl4)-based chemistry. The method allows reliable Ti/TiN film integration to be achieved with excellent TiN step coverage. For example, the film structure can be used as an effective barrier layer in integrated circuit fabrication.

Abstract: The invention provides a method for forming a metal nitride film by depositing a metal oxide film on the substrate and exposing the metal oxide film to a nitrating gas to densify the metal oxide and form a metal nitride film. The metal oxide film is deposited by the decomposition of a chemical vapor deposition precursor. The nitrating step comprises exposing the metal oxide film to a thermally or plasma enhanced nitrating gas preferably comprising nitrogen, oxygen, and anunonia. The invention also provides a process for forming a liner/barrier scheme for a metallization stack by forming a metal nitride layer over the substrate by the densification of a metal oxide layer by a nitrating gas depositing a metal liner layer. Optionally, a metal liner layer may be deposited over substrate prior to the metal nitride layer to form a metal/metal nitride liner/barrier scheme.

Abstract: There is presented a semiconductor device including multiple levels of copper interconnects; wherein the surface of a copper interconnect corresponding to at least one underlying layer of another copper interconnect layer is turned into copper oxide to a thickness of 30 nm or more by oxidation conducted at the oxidation rate of 20 nm/minor less, and thereby the reflection of the exposure light from the lower-level copper interconnect is prevented, in forming by means of photolithography a trench to form a copper interconnect through damascening.

Abstract: A hard Al oxide film having a high melting point, which grows on the surface of an Al—Cu film during a wafer is carried in atmospheric air, obstructs the burying of a viahole with the Al—Cu film by high pressure reflow, with a result that a void remains in the hole. The present invention is intended to remove such an Al oxide film grown on the Al—Cu film formed by sputtering, by Ar+ sputtering/etching directly before high pressure reflow. Moreover, when a Ti oxide film is present on the surface of a Ti based underlying film formed by CVD, an Al oxide film is possibly grown at the boundary between the Ti based underlying film and an Al—Cu film laminated thereon. In this case, the Ti oxide film is similarly removed directly before formation of the Al—Cu film, thereby preventing the growth of the Al oxide film.

Abstract: A pair of transistors sharing a common electrodes e.g. a bitline in a DRAM array, has a self-aligned contact to the bitline in which the transistor gate stack has only a poly layer with a nitride cover; the aperture for the bitline contact is time-etched to penetrate only between the gates and not reach the silicon substrate; exposed nitride shoulders of the gate are etched to expose the poly; the remainder of the interlayer dielectric is removed by a selective etch; the exposed poly is re-oxidized to protect the gates; and the aperture bottom is cleaned; so that the thick gate stack of a DRAM is dispensed with in order to improve uniformity of line width across the chip beyond what the DRAM technique can deliver.

Abstract: A method for providing a self-aligned etch stop layer comprises the steps of providing a dielectric layer having a polycrystalline silicon (poly) plug formed therein. An aluminum layer is formed to contact the dielectric layer and the plug, then the structure is heated. Heating the aluminum and the poly results in the absorption of the aluminum overlying the plug into the poly, while the aluminum overlying the dielectric is not absorbed. The aluminum over the dielectric is oxidized which forms a self-aligned etch stop layer. Layers are formed over the aluminum oxide and are subsequently etched. The etch stops on the aluminum oxide and the poly plug.

Abstract: A dielectric layer (27) is formed between a semiconductor surface (24) and an electrical contact (26) to promote adhesion of the contact (26). The dielectric layer (27) is formed by cleaning operation followed by a chemical oxidation.

Abstract: A method of film processing comprises forming an integrated titanium/titanium nitride (Ti/TiN) film structure having an intermediate layer. The intermediate layer comprises species containing Si, and preferably containing Si and Ti, such as titanium silicide (TiSix), or TiSixOy, among others. The intermediate layer protects the underlying Ti film against chemical attack during subsequent TiN deposition using a titanium tetrachloride (TiCl4)-based chemistry. The method allows reliable Ti/TiN film integration to be achieved with excellent TiN step coverage. For example, the film structure can be used as an effective barrier layer in integrated circuit fabrication.

Abstract: The adhesion of a diffusion barrier or capping layer to Cu and/or Cu alloy interconnect members is significantly enhanced by treating the exposed surface of the Cu and/or Cu alloy interconnect members with a silane or dichlorosilane plasma to form a layer of copper silicide thereon prior to depositing the capping layer. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, treating the exposed surface of the Cu or Cu alloy interconnect member in a silane or dichlorosilane plasma to form the copper silicide layer and depositing a capping layer of silicon nitride thereon.

Abstract: A planarization process for filling spaces between patterned metal features formed over a surface of a semiconductor substrate. The patterned metal features are preferably coated with a dielectric barrier. The dielectric barrier is coated with an material that expands during oxidation or nitridization to a thickness about half the depth of the space between metallized features. The layer is then plasma oxidized using an RF or ECR plasma at low temperature with an oxygen ambient. Alternatively, the layer is plasma nitridized at low temperature. The plasma oxidation or nitridization is continued until the expandable material is converted to a dielectric and has expanded to fill the space between patterned metal features. Optionally, the process can be followed by a mechanical or chemical mechanical planarization step.

Abstract: Exemplary embodiments of the present invention teach a process for forming a storage capacitor for a semiconductor assembly, by forming a first storage electrode having a top surface consisting of titanium nitride; forming a barrier layer directly on the titanium nitride, the barrier layer (a material containing any one of amorphous silicon, tantalum, titanium, or strontium) being of sufficient thickness to substantially limit the oxidation of the titanium nitride when said semiconductor assembly is subjected to an oxidizing agent (either an oxidizing agent or an nitridizing agent); converting a portion of the barrier layer to a dielectric compound; depositing a storage cell dielectric directly on the dielectric compound, the storage cell dielectric being of the same chemical makeup as the dielectric compound and thereby using the dielectric compound as a nucleation surface; and forming a second capacitor electrode on the storage cell dielectric.

Abstract: A method for forming intermetal dielectric of semiconductor device comprising the steps of: forming a first insulating layer on a semiconductor substrate having device such as transistors therein; forming metal wirings in which a Ti/TiN layer, an Al layer and a TiN layer are stacked successively on the first insulating layer; forming a spacer of TiN layer at side of the metal wirings; forming a second insulating layer on the metal wirings having the spacer and on the first insulating layer, wherein the second insulating layer is made of an insulating material whose deposition rate varies in accordance with the kinds of bottom layers; forming a third insulating layer on the second insulating layer; and polishing the third insulating layer by a chemical mechanical polishing process.

Abstract: In a method of manufacturing a semiconductor device, a titanium silicide layer is formed on a region of a diffusion layer formed in a semiconductor substrate. A silicon nitride film functioning as an etching stopper is formed on the semiconductor substrate. The silicon nitride film covers the layer. An interlayered insulating film is formed on the silicon nitride film. A barrier metal of Tin/Ti is formed in a contact hole, which is formed in the interlayered insulating film. The contact holes is opened toward the diffusion layer. A conductive film comprising a Ti—Si—N based alloy is formed between a metal wiring and the diffusion layer. The conductive film is formed by reacting the silicon nitride film with titanium contained in the titanium silicide layer or the barrier metal. With these manufacturing features, the manufacturing process is not increased and the manufacturing cost can be reduced.

Abstract: A process for making a MOS transistor. The transistor includes a source, a channel and drain formed on a portion of silicon film in a silicon-on-insulator type structure. A field insulation layer surrounds the film. A grid structure with insulated flanks is formed above the channel. Source and drain contacts are formed on the portion of the silicon film between the field insulation layer and the grid structure. The source and drain contacts are self-aligned on the grid structure and the field insulation layer is placed directly adjacent to the grid structure.

Abstract: A method of forming metal lines is disclosed. The method comprises the steps of: forming a composite metal layer over a wafer, the composite metal layer having a top layer of titanium/titanium nitride; oxidizing the top layer of titanium/titanium nitride to form a layer of titanium oxide; and patterning and etching the composite metal layer to form the metal lines.

Abstract: Methods of forming refractory metal silicide components are described. In accordance with one implementation, a refractory metal layer is formed over a substrate. A silicon-containing structure is formed over the refractory metal layer and a silicon diffusion restricting layer is formed over at least some of the silicon-containing structure. The substrate is subsequently annealed at a temperature which is sufficient to cause a reaction between at least some of the refractory metal layer and at least some of the silicon-containing structure to at least partially form a refractory metal silicide component. In accordance with one aspect of the invention, a silicon diffusion restricting layer is formed over or within the refractory metal layer in a step which is common with the forming of the silicon diffusion restricting layer over the silicon-containing structure.

Abstract: An improved contact structure and process for forming an improved contact structure for a semiconductor device. A metal (14) is formed on a first metal layer (12) positioned on a substrate (10) The metal (14) is a Group VIIB or Group VIII metal or metal oxide and increases the electrically conductive surface area (25) of the first metal layer (12). In one embodiment, a Group VIIB or Group VIII metal layer is deposited onto the first metal layer and the Group VIIB or Group VIII metal layer is anisotropically etched to form sidewall spacers (24). An insulating layer (16) is deposited overlying the first conductive layer (12) and the sidewall spacers (24). A via opening (18) is formed in the insulation layer (16) to expose a portion of the electrically conductive surface area (25). A second metal layer (22) fills the opening (18) and forms a metallurgical contact to the first metal layer (12).

Abstract: Conductive structures, conductive lines, conductive SRAM lines, integrated circuitry, SRAM cells, and methods of forming the same are described. In one embodiment, a substrate is provided and a layer comprising TiN is physical vapor deposited over the substrate having greater than or equal to about 90% by volume <200> grain orientation. In another embodiment, at least two components are electrically connected by forming a layer of TiN over a substrate having the desired by-volume concentration of <200> grain orientation, and etching the layer to form a conductive line. In a preferred embodiment, conductive lines formed in accordance with the invention electrically connect at least two SRAM components and preferably form cross-coupling electrical interconnections between first and second inverters of an SRAM cell.

Abstract: A procedure for forming the barrier layer includes a plasma procedure in the fabricating procedure. The procedure is that an opening is formed on a dielectric layer, which is formed over a semiconductor substrate, by a damascene technology or a patterning process. Then, the plasma procedure is applied by following a procedure in which a halide gas is flowed over the substrate. Then, the halide gas is dissolved by applying plasma to it to form halogen atoms with free bonds, which can enter the dielectric layer to form another halide with the dielectric material and stay close to the surface. Then, a metal layer is formed over the substrate. The metal layer fills the opening and results in a reaction with the halide in the surface of the dielectric layer. A nonvolatile metallic halide layer, therefore, is formed. The nonvolatile metallic halide layer is a nonvolatile insulating layer that acts as the barrier layer between the metal layer and the dielectric layer.

Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.

Abstract: A process for forming an electronic component carrier, the electronic carrier having routing layers parallel to an aluminum substrate and vias perpendicular to the aluminum substrate, the process comprising defining routing layers by forming a blocking mask on the aluminum substrate, the blocking mask leaving exposed areas corresponding to the routing layers, carrying out a barrier anodization process on the aluminum substrate to form a surface barrier oxide over the routing layers, removing the blocking mask, providing an upper aluminum layer over the aluminum substrate, defining vias by forming a blocking mask on the upper aluminum layer, the blocking mask covering areas corresponding to the vias, and subjecting both the aluminum substrate and the upper aluminum layer to porous anodization. The barrier oxide defining the routing layer provides reliable masking of the routing layer during porous anodization.

Abstract: The invention provides a method for producing wiring and contacts in an integrated circuit including the steps of forming insulated gate components on a semiconductor substrate; applying a photo-reducible dielectric layer to cover the substrate; etching holes and forming contacts; photo-reducing the dielectric to increase its conductivity; covering the resulting structure with an interconnect layer; etching the interconnect layer to define wiring in electrical contact with the contacts; and oxidizing the dielectric to reduce its conductivity.

Abstract: A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After all of the conductive lines have received a deposit of conformal insulating material and a flowable insulating material, the composite insulating materials are removed, preferably by etching, from those pairs of conductive lines with a gap of about 0.5 microns or less. Now, a nonconformal insulating material with a poor step function is deposited and creates a large void in the open gaps of 0.5 microns or less. After creating the void, the deposition continues and is planarized at the desired composite thickness of insulation.

Abstract: A field effect transistor available for 1 giga-bit dynamic random access memory device has a two-layer gate structure consisting of a lower layer of nitrogen-containing silicon and an upper layer of refractory metal, and the nitrogen-containing silicon effectively prevents the gate oxide layer from alkaline metals diffused from the refractory metal.

Abstract: A method of forming a conductive line structure is provided. An adhesion layer is formed on a substrate surface. A seed layer is formed on the adhesion layer. A conductor is formed on the seed layer to form a partially complete structure. The partially complete structure is exposed to an electrolyte and undergoes an anodization process. At least a portion of the seed layer and a portion of the conductor are transformed to seed layer metal oxide and conductor metal oxide, respectively. At least a portion of the adhesion layer is transformed to an adhesion layer metal oxide and a further portion of the conductor is transformed to the conductor metal oxide. An outer metal layer is formed over the seed layer metal oxide and the conductor metal oxide.

Abstract: An SRAM cell having improved stability includes pass transistors having gate electrodes which are shaped by oxidation so that the lower edges of the gate electrodes are raised away from the substrate surface. Because the gate electrodes of the load and pull-down transistors are masked during the oxidation process, the gate electrodes of the load and pull-down transistors have the conventional rectangular shape. The modified shape of the gate electrodes of the pass transistors decreases the current flowing through the pass transistors relative to that which flows through the pull-down transistors, reducing the likelihood that data can inadvertently be lost from the SRAM cell.

Abstract: A method of fabricating a semiconductor device includes the step of removing native oxide on the surface of a metal silicide layer formed on a shallow impurity diffusion layer and exposed at the bottom portion of a contact hole by sputter etching under an incident ion condition of a high density and a low energy. In this sputter etching, the side surface of the contact hole is prevented from being sputtered and re-deposited on the bottom portion of the contact hole, whereby the native oxide is effectively removed while the impurity diffusion layer is prevented from being damaged. In addition, a substrate may be heated during sputter etching for preventing ion species such as Ar.sup.+ from being entrapped in the metal silicide layer.