Including Use Of Antireflective Layer Patents (Class 438/636)
  • Patent number: 10269576
    Abstract: Embodiments described herein relate generally to methods for etching structures and the structures formed thereby. In some embodiments, an etch selectivity between a first portion of a material and a second portion of the material is increased. Increasing the etch selectivity includes performing an anisotropic treatment, such as an anisotropic ion implantation, on the material to treat the first portion of the material, and the second portion of the material remains untreated after the anisotropic treatment. After increasing the etch selectivity, the first portion of the material is etched. The etching may be a wet or dry etch, and may further be isotropic or anisotropic.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Wei Huang, Yu-Yu Chen, Chia-Nan Lin
  • Patent number: 10211097
    Abstract: A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: February 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Shao-Kuan Lee, Hai-Ching Chen
  • Patent number: 9659821
    Abstract: A method includes forming a dielectric layer over a conductive feature. A first mask having a first opening is formed over the dielectric layer. A second mask is formed over the first mask. A third mask having a second opening is formed over the second mask. A fourth mask having a third opening is formed over the third mask, a portion of the third opening overlapping with the second opening. The portion of the third opening is transferred to the second mask to form a fourth opening, a portion of the fourth opening overlapping with the first opening. The portion of the fourth opening is transferred to the dielectric layer to form a fifth opening. The fifth opening is extended into the dielectric layer to form an extended fifth opening, the extended fifth opening exposing the conductive feature. The extended fifth opening is filled with a conductive material.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Ta-Ching Yu
  • Patent number: 9627319
    Abstract: A method includes forming a multilayered film including a conductive layer mainly containing aluminum, and a barrier metal layer formed thereon, forming a hard mask layer on the barrier metal layer, patterning a resist on the hard mask layer, patterning the hard mask layer by dry-etching the hard mask layer with the patterned resist as a mask, cleaning a surface of the barrier metal layer with a cleaning solution after the patterning the hard mask layer, and dry-etching the multilayered film with the patterned hard mask layer as a mask after the cleaning the surface of the barrier metal layer. In the patterning the hard mask layer, dry etching is performed with a ratio of a flow rate of an oxidizing gas to a total flow rate of a process gas at less than 1% in a state in which the barrier metal layer is exposed to the process gas.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: April 18, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Koji Hara, Nobutaka Ukigaya, Takeshi Aoki, Yasuhiro Kawabata, Junya Tamaki, Norihiko Nakata, Satoshi Ogawa
  • Patent number: 9564286
    Abstract: Provided is a method of forming a thin film of a semiconductor device. The method includes forming a precursor layer on a surface of a substrate by supplying a precursor gas into a chamber, discharging the precursor gas remaining in the chamber to an outside of the chamber by supplying a purge gas into the chamber, supplying a reactant gas into the chamber, generating plasma based on the reactant gas, forming a thin film by a chemical reaction between plasma and the precursor layer and radiating extreme ultraviolet (EUV) light into the chamber, and discharging the reactant gas and the plasma remaining in the chamber by supplying a purge gas into the chamber.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: February 7, 2017
    Assignees: Samsung Electronics Co., Ltd., The Board of Trustees of the Leland Stanford Junior University
    Inventors: Sam Hyung Sam Kim, Andrei Teodor Iancu, Friedrich B. Prinz, Michael C. Langston, Peter Schindler, Ki-Hyun Kim, Stephen P. Walch, Takane Usui
  • Patent number: 9330965
    Abstract: A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: May 3, 2016
    Assignees: International Business Machines Corporation, Global Foundries Inc.
    Inventors: Hsueh-Chung Chen, Yongan Xu, Yunpeng Yin, Ailian Zhao
  • Patent number: 9196632
    Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: November 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masahiko Hayakawa, Mitsunori Sakama, Satoshi Toriumi
  • Patent number: 9175173
    Abstract: A system and method for anti-reflective layers is provided. In an embodiment the anti-reflective layer comprises a polymer resin which has repeating units within it. At least one of the repeating units comprises a locked unit which has a cyclic structure and a lock within the unit. After the anti-reflective layer has been applied and baked, irregularities such as voids and step heights differences that have occurred may be handled by unlocking the lock within the locked unit. This unlocking breaks the cyclic structure, allowing the polymer to take up more volume and causing the anti-reflective layer to self-expand, filling the voids and reducing the step-height. The unlocking may be performed by exposure or thermal treatments.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: November 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Yu Liu, Ching-Yu Chang
  • Publication number: 20150108652
    Abstract: A semiconductor device and its fabrication method are provided. A first dielectric layer is provided to cover a substrate. The first dielectric layer contains a plurality of first conductive layers. A portion of each first conductive layer is removed to form a plurality of first openings in the first dielectric layer. A second dielectric layer is formed in each first opening. A third dielectric layer having second-openings are formed on the first dielectric layer and on the second dielectric layers. Each second-opening exposes at least two adjacent second dielectric layers. Second dielectric layers exposed by a first second-opening are removed to form third openings to expose corresponding first conductive layers. Second conductive layers are formed in the third opening and the second-openings including the first second-opening. Stable electrical interconnections with high quality electrical isolations can be provided.
    Type: Application
    Filed: February 19, 2014
    Publication date: April 23, 2015
    Applicant: Semiconductor Manufactruing International (Shanghai) Corporation
    Inventor: ZHONGSHAN HONG
  • Patent number: 8999840
    Abstract: A method of forming a micro pattern of a semiconductor device may include forming an acid-extinguisher containing film on a substrate, forming a photoresist film containing a potential acid on the acid-extinguisher containing film, forming an exposed area containing acids by exposing a portion of the photoresist film to light, forming an insoluble polymer thin film between the acid-extinguisher containing film and the exposed area by extinguishing the acids of the exposed area at an interface between the acid-extinguisher containing film and the exposed area, developing the photoresist film to form a space exposing the insoluble polymer thin film in the exposed area and a photoresist pattern integrally connected to the insoluble polymer thin film, exposing the acid-extinguisher containing film through the space by removing the insoluble polymer thin film, and removing the acid-extinguisher containing film exposed through the space.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: April 7, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Cha-won Koh
  • Publication number: 20140363969
    Abstract: A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.
    Type: Application
    Filed: June 10, 2013
    Publication date: December 11, 2014
    Applicants: Globalfoundries Inc., International Business Machines Corporation
    Inventors: Hsueh-Chung Chen, Yongan Xu, Yunpeng Yin, Ailian Zhao
  • Patent number: 8900897
    Abstract: Devices are described including a component comprising an alloy of AlN and AlSb. The component has an index of refraction substantially the same as that of a semiconductor in the optoelectronic device, and has high transparency at wavelengths of light used in the optoelectronic device. The component is in contact with the semiconductor in the optoelectronic device. The alloy comprises between 0% and 100% AlN by weight and between 0% and 100% AlSb by weight. The semiconductor can be a III-V semiconductor such as GaAs or AlGaInP. The component can be used as a transparent insulator. The alloy can also be doped to form either a p-type conductor or an n-type conductor, and the component can be used as a transparent conductor. Methods of making and devices utilizing the alloy are also disclosed.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: December 2, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Philip Kraus, Thai Cheng Chua, Yoga Saripalli
  • Patent number: 8853101
    Abstract: Methods for creating chemical guide patterns by DSA lithography for fabricating an integrated circuit are provided. In one example, an integrated circuit includes forming a bifunctional brush layer of a polymeric material overlying an anti-reflective coating on a semiconductor substrate. The polymeric material has a neutral polymeric block portion and a pinning polymeric block portion that are coupled together. The bifunctional brush layer includes a neutral layer that is formed of the neutral polymeric block portion and a pinning layer that is formed of the pinning polymeric block portion. A portion of the neutral layer or the pinning layer is selectively removed to define a chemical guide pattern. A block copolymer layer is deposited overlying the chemical guide pattern. The block copolymer layer is phase separated to define a nanopattern that is registered to the chemical guide pattern.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 7, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Richard A. Farrell, Gerard M. Schmid, xU Ji
  • Patent number: 8835307
    Abstract: A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hakeem Akinmade-Yusuff, John A. Fitzsimmons, Ranee Wai-Ling Kwong
  • Patent number: 8835966
    Abstract: A semiconductor light-emitting element (1) is provided which includes a semiconductor layer (10), an n-type electrode (18) which is provided on an exposed surface (12a) of an n-type semiconductor layer, wherein an exposed surface is exposed by removing a part of the semiconductor layer (10), a transparent conductive film which is provided on the semiconductor layer (10) and a p-type electrode (17) which is provided on the transparent conductive film; a light-reflecting layer (39) is provided between the semiconductor layer (10) and the transparent conductive film, wherein at least part of the light-reflecting layer overlaps with the p-type electrode (17) in the planar view; the p-type electrode (17) comprises a pad portion (P) and a linear portion (L) which linearly extends from the pad portion (P) and has an annular structure in the planar view; the n-type electrode (18) exists in an inner area which is surrounded by the linear portion (L) and exists on a straight line (L1) which goes through a center (17a)
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: September 16, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Hironao Shinohara, Remi Ohba
  • Patent number: 8791013
    Abstract: A pattern forming method is disclosed. The method includes the steps of: forming a dielectric layer on a substrate; forming a first patterned mask on the dielectric layer, wherein the first patterned mask comprises an opening; forming a material layer on the dielectric layer and covering the first patterned mask; forming a second patterned mask on the material layer, wherein the second patterned mask comprises a first aperture; forming a second aperture in the second patterned mask after forming the first aperture, wherein the second aperture and the first aperture comprise a gap therebetween and overlap the opening; and utilizing the second patterned mask as an etching mask for partially removing the material layer and the dielectric layer through the first aperture and the second aperture.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: July 29, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Shin-Chi Chen, Yu-Tsung Lai, Jiunn-Hsiung Liao, Guang-Yaw Hwang
  • Patent number: 8791012
    Abstract: In accordance with the teachings of the present disclosure, methods and apparatus are provided for a semiconductor device having thin anti-reflective layer(s) operable to absorb radiation that may otherwise reflect off surfaces disposed inwardly from the anti-reflective layer(s). In a method embodiment, a method for manufacturing a semiconductor device includes forming a support structure outwardly from a substrate. The support structure has a first thickness and a first outer sidewall surface that is not parallel with the substrate. The first outer sidewall surface has a first minimum refractive index. The method further includes forming an anti-reflective layer outwardly from the first outer sidewall surface. The anti-reflective layer has: a second outer sidewall surface that is not parallel with the substrate, a second refractive index that is greater than the first minimum refractive index, and a second thickness that is less than the first thickness.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: July 29, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Stanford Joseph Gautier, Jr., Rabah Mezenner, Randy Long
  • Patent number: 8753974
    Abstract: Structures and methods for the dissipation of charge build-up during the formation of cavities in semiconductor substrates.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: June 17, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Brian Griffin, Russ Benson
  • Patent number: 8748310
    Abstract: A method for producing a metal contact structure of a photovoltaic solar cell, including: applying an electrically non-conductive insulating layer to a semiconductor substrate, applying a metal contact layer to the insulating layer, and generating a plurality of local electrically conductive connections between the semiconductor substrate and the contact layer right through the insulating layer. The metal contact layer is formed using two pastes containing metal particles: the first paste containing metal particles is applied to local regions, and the second paste containing metal particles is applied covering at least the regions covered with the first paste and partial regions located therebetween.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: June 10, 2014
    Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung E.V.
    Inventors: Daniel Biro, Benjamin Thaidigsmann, Florian Clement, Robert Woehl, Edgar-Allan Wotke
  • Patent number: 8748198
    Abstract: A focus through a projection lens is corrected to prevent the occurrence of a dimensional error in a pattern due to defocusing. At least one automatic focus correction mark is formed over each of chip patterns formed in a reticle used for exposure. Using one of the automatic focus correction marks located in the center portion of an actual device region, automatic correction of the focus of exposure light is performed. In this manner, a variation in the focus of the exposure light through the center portion of the projection lens, which is more likely to reach a high temperature than an end portion of the projection lens, is detected and corrected.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: June 10, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Naoyuki Teramoto, Megumu Fukazawa, Masayuki Kumashiro, Kiyoshi Kawagashira
  • Patent number: 8716122
    Abstract: To provide: a technique capable of suppressing a titanium nitride film that is exposed at the side surface of an opening from turning into a titanium oxide film even when water permeates the opening over a pad from outside a semiconductor device and thus improving the reliability of the semiconductor device; and a technique capable of suppressing a crack from occurring in a surface protective film of a pad and improving the reliability of a semiconductor device. An opening is formed so that the diameter of the opening is smaller than the diameter of another opening and the opening is included in the other opening. Due to this, it is possible to cover the side surface of an antireflection film that is exposed at the side surface of the other opening with a surface protective film in which the opening is formed. As a result of this, it is possible to form a pad without exposing the side surface of the antireflection film.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: May 6, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takuro Honma, Yoshifumi Takata
  • Patent number: 8658532
    Abstract: Various lithography methods are disclosed. An exemplary lithography method includes forming a first patterned silicon-containing organic polymer layer over a substrate by removing a first patterned resist layer, wherein the first patterned silicon-containing organic polymer layer includes a first opening having a first dimension and a second opening having the first dimension, the first opening and the second opening exposing the substrate; forming a second patterned silicon-containing organic polymer layer over the substrate by removing a second patterned resist layer, wherein a portion of the patterned second silicon-containing organic polymer layer combines with a portion of the first patterned silicon-containing organic polymer layer to reduce the first dimension of the second opening to a second dimension; and etching the substrate exposed by the first opening having the first dimension and the second opening having the second dimension.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: February 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ching-Yu Chang
  • Patent number: 8592302
    Abstract: A patterning method is provided for fabrication of a semiconductor device structure having conductive contact elements, an interlayer dielectric material overlying the contact elements, an organic planarization layer overlying the interlayer dielectric material, an antireflective coating material overlying the organic planarization layer, and a photoresist material overlying the antireflective coating material. The method creates a patterned photoresist layer from the photoresist material to define oversized openings corresponding to respective conductive contact elements. The antireflective coating is etched using the patterned photoresist as an etch mask. A liner material is deposited overlying the patterned antireflective coating layer. The liner material is etched to create sidewall features, which are used as a portion of an etch mask to form contact recesses for the conductive contact elements.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: November 26, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Erik P. Geiss, Peter Baars
  • Patent number: 8580678
    Abstract: A method for fabricating a semiconductor device includes forming first plugs over a substrate, forming contact holes that expose the first plugs, ion-implanting an anti-diffusion material into the first plugs, and forming second plugs filling the contact holes.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: November 12, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sun-Hwan Hwang
  • Patent number: 8536049
    Abstract: Methods of forming metal contacts with metal inks in the manufacture of photovoltaic devices are disclosed. The metal inks are selectively deposited on semiconductor coatings by inkjet and aerosol apparatus. The composite is heated to selective temperatures where the metal inks burn through the coating to form an electrical contact with the semiconductor. Metal layers are then deposited on the electrical contacts by light induced or light assisted plating.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: September 17, 2013
    Assignees: Rohm and Haas Electronic Materials LLC, Alliance for Sustainable Energy, LLC
    Inventors: Erik Reddington, Thomas C. Sutter, Lujia Bu, Alexandra Cannon, Susan E. Habas, Calvin J. Curtis, Alexander Miedaner, David S. Ginley, Marinus Franciscus Antonius Maria Van Hest
  • Patent number: 8530323
    Abstract: A method for fabricating a capacitor is provided. The method for fabricating a capacitor includes forming a dielectric layer over a lower electrode on a substrate, forming an upper electrode over the dielectric layer, forming a hard mask over the upper electrode, etching the hard mask to form a hard mask pattern, etching the upper electrode to make the dielectric layer remain on the lower electrode in a predetermined thickness, forming an isolation layer along an upper surface of the remaining dielectric layer and the hard mask pattern, leaving the isolation layer having a shape of a spacer on one sidewall of the hard mask pattern, the upper electrode, and the dielectric layer, and etching the lower electrode to be isolated.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: September 10, 2013
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Jin-Youn Cho, Young-Soo Kang, Jong-Il Kim, Sang-Geun Koo
  • Patent number: 8507346
    Abstract: A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: August 13, 2013
    Assignee: International Business Machines Corporation
    Inventors: Martin Burkhardt, Matthew E. Colburn, Allen H. Gabor, Oleg Gluschenkov, Scott D. Halle, Howard S. Landis, Helen Wang
  • Patent number: 8491984
    Abstract: A structure. The structure includes: a hole layer; a hole layer including a top hole layer surface, wherein the hole layer has a thickness in a first direction that is perpendicular to the hole layer surface; a bottom antireflective coating (BARC) layer on and in direct physical contact with the hole layer at the top hole layer surface; a photoresist layer on and in direct physical contact with the BARC layer, wherein a continuous hole in the first direction extends completely through the photoresist layer, the BARC layer, and the hole layer; and a polymerized hole shrinking region in direct physical contact with the photoresist layer at a lateral surface of the photoresist layer and with the hole layer at the top hole layer surface, wherein the hole shrinking region does not extend below the hole layer surface in a direction from the BARC layer to the hole layer.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Todd Christopher Bailey, Colin J. Brodsky, Allen H. Gabor
  • Patent number: 8470708
    Abstract: A method of lithography patterning includes forming a mask layer on a material layer and forming a capping layer on the mask layer. The capping layer is a boron-containing layer with a higher resistance to an etching reaction of patterning process of the material layer. By adapting the boron-containing layer as the capping layer, the thickness of the mask layer can be thus reduced. Hence, a better gap filling for forming an interconnect metallization in the material layer could be achieved as well.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: June 25, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Cheng Shih, Kuan-Chen Wang, Chung-Chi Ko, Keng-Chu Lin, Tai-Yen Peng, Wen-Kuo Hsieh, Chih-Hao Chen
  • Patent number: 8450854
    Abstract: The present invention provides an interconnect structure in which a patternable low-k material is employed as an interconnect dielectric material. Specifically, this invention relates to single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric. In general terms, the interconnect structure includes at least one patterned and cured low-k dielectric material located on a surface of a substrate. The at least one cured and patterned low-k material has conductively filled regions embedded therein and typically, but not always, includes Si atoms bonded to cyclic rings via oxygen atoms. The present invention also provides a method of forming such interconnect structures in which no separate photoresist is employed in patterning the patterned low-k material.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: May 28, 2013
    Assignee: International Business Machines Corporation
    Inventors: Qinghuang Lin, Shyng-Tsong Chen
  • Patent number: 8445382
    Abstract: A dual damascene process for forming conductive interconnects on an integrated circuit die. The process includes providing a layer (16) of porous, ultra low-k (ULK) dielectric material in which a via opening (30) is subsequently formed. A thermally degradable polymeric (“porogen”) material (42) is applied to the side wall sidewalls of the opening (30) such that the porogen material penetrates deeply into the porous ULK dielectric material (thereby sealing the pores and increasing the density thereof). Once a conductive material (36) has been provided with the opening (30) and polished back by means of chemical mechanical polishing (CMP), the complete structure is subjected to a curing step to cause the porogen material (44) with the ULK dielectric layer (16) to decompose and evaporate, thereby restoring the porosity (and low-k value) of the dielectric layer (16). Attached are a marked-up copy of the originally filed specification and a clean substitute specification in accordance with 37 C.F.R. §§1.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: May 21, 2013
    Assignee: NXP B.V.
    Inventor: Willem Frederik Adrianus Besling
  • Publication number: 20130113071
    Abstract: A semiconductor device includes a fuse configured to be programmed in response to a laser, a protective layer formed under the fuse and overlapping with a portion of the fuse, and a heat emission portion coupled with the protective layer.
    Type: Application
    Filed: September 14, 2012
    Publication date: May 9, 2013
    Inventor: Min-Yung LEE
  • Patent number: 8420947
    Abstract: A method of manufacturing an integrated circuit system includes: providing a etch stop layer; forming a layer stack over the etch stop layer with the layer stack having an anti-reflective coating layer over a low temperature oxide layer; forming a photoresist layer over the anti-reflective coating layer; forming a first resist line and a second resist line from the photoresist layer with the first resist line and the second resist line separated by a through line pitch on the anti-reflective coating layer; etching the anti-reflective coating layer using a low-pressure polymer burst with a non-oxidizing gas mixture to remove a portion of the anti-reflective coating layer; and forming a first polymer layer over the first resist line.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: April 16, 2013
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventor: Ravi Prakash Srivastava
  • Patent number: 8394714
    Abstract: Micro-fluid ejection heads have anti-reflective coatings. The coatings destructively interfere with light at wavelengths of interest during subsequent photo imaging processing, such as during nozzle plate imaging. Methods include determining wavelengths of photoresists. Layers are applied to the substrate and anodized. They form an oxidized layer of a predetermined thickness and reflectivity that essentially eliminates stray and scattered light during production of nozzle plates. Process conditions include voltages, biasing, lengths of time, and bathing solutions, to name a few. Tantalum and titanium oxides define further embodiments as do layer thicknesses and light wavelengths.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: March 12, 2013
    Assignee: Lexmark International, Inc.
    Inventor: Byron V. Bell
  • Patent number: 8383511
    Abstract: Openings are formed in first and second mask layers. Next, diameter of the opening in the second mask layer is enlarged so that the diameter of the opening in the second mask layer becomes larger by a length X than diameter of the opening in the first mask layer. Thereafter, mask material is formed into the opening in the second mask layer, to form a cavity with a diameter X within the opening in the second mask layer. There is formed a mask which includes the second mask layer and the mask material having therein opening including the cavity.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: February 26, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Mitsunari Sukekawa
  • Patent number: 8367540
    Abstract: A photoresist conversion that changes a patterned photoresist into a permanent patterned interconnect dielectric is described. The photoresist conversion process includes adding a dielectric enabling element into a patterned photoresist. The dielectric enabling element-containing photoresist is converted into a permanent patterned dielectric material by performing a curing step. In one embodiment, a method is described that includes providing at least one photoresist to an upper surface of a substrate. At least one interconnect pattern is formed into the at least one photoresist. A dielectric enabling element is added to the patterned photoresist and thereafter the patterned photoresist including the dielectric enabling element is cured into a cured permanent patterned dielectric material. The cured permanent patterned dielectric material includes the dielectric enabling therein.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: February 5, 2013
    Assignee: International Business Machines Corporation
    Inventor: Qinghuang Lin
  • Publication number: 20130029484
    Abstract: One or more openings in an organic mask layer deposited on a first insulating layer over a substrate are formed. One or more openings in the first insulating layer are formed through the openings in the organic mask using a first iodine containing gas. An antireflective layer can be deposited on the organic mask layer. One or more openings in the antireflective layer are formed down to the organic mask layer using a second iodine containing gas. The first insulating layer can be deposited on a second insulating layer over the substrate. One or more openings in the second insulating layer can be formed using a third iodine containing gas.
    Type: Application
    Filed: July 25, 2011
    Publication date: January 31, 2013
    Inventors: Daisuke Shimizu, Jong Mun Kim
  • Publication number: 20120302056
    Abstract: A pattern forming method is disclosed. The method includes the steps of: forming a dielectric layer on a substrate; forming a first patterned mask on the dielectric layer, wherein the first patterned mask comprises an opening; forming a material layer on the dielectric layer and covering the first patterned mask; forming a second patterned mask on the material layer, wherein the second patterned mask comprises a first aperture; forming a second aperture in the second patterned mask after forming the first aperture, wherein the second aperture and the first aperture comprise a gap therebetween and overlap the opening; and utilizing the second patterned mask as an etching mask for partially removing the material layer and the dielectric layer through the first aperture and the second aperture.
    Type: Application
    Filed: August 7, 2012
    Publication date: November 29, 2012
    Inventors: Shin-Chi Chen, Yu-Tsung Lai, Jiunn-Hsiung Liao, Guang-Yaw Hwang
  • Patent number: 8309457
    Abstract: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: November 13, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kouros Ghandehari, Anna M. Minvielle, Marina V. Plat, Hirokazu Tokuno
  • Patent number: 8298935
    Abstract: A dual damascene process is disclosed. The process includes the steps of: forming a dielectric layer on a substrate; forming a first patterned mask on the dielectric layer, wherein the first patterned mask comprises an opening; forming a material layer on the dielectric layer and covering the first patterned mask; forming a second patterned mask on the dielectric layer, wherein the second patterned mask comprises a first aperture; forming a second aperture in the second patterned mask, wherein the second aperture and the first aperture comprise a gap therebetween; and utilizing the second patterned mask as etching mask for partially removing the material layer and the dielectric layer through the first aperture and the second aperture.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: October 30, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Shin-Chi Chen, Yu-Tsung Lai, Jiunn-Hsiung Liao, Guang-Yaw Hwang
  • Patent number: 8288271
    Abstract: A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: October 16, 2012
    Assignee: International Business Machines Corporation
    Inventors: Hakeem Akinmade Yusuff, John A. Fitzsimmons, Ranee Wai-Ling Kwong
  • Patent number: 8263489
    Abstract: A method for the deposition of an anti-reflection film on a substrate is disclosed. A substrate including a plurality of solar cell structures is provided and placed in a vacuum chamber with a target including silicon. A flow of a nitrogen-containing reactive gas into the vacuum chamber is set to a first value while a voltage between the target and ground is switched off and then increased to a second value. A voltage is applied between the target and ground, whereby a film of silicon and nitrogen is deposited on the substrate in a flow of the nitrogen-containing reactive gas which is higher than the first value.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: September 11, 2012
    Assignee: OC Oerlikon Balzers AG
    Inventors: Oliver Rattunde, Stephan Voser
  • Patent number: 8258056
    Abstract: A method of lithography patterning includes forming a first material layer on a substrate; forming a first patterned resist layer including at least one opening therein on the first material layer; forming a second material layer on the first patterned resist layer and the first material layer; forming a second patterned resist layer including at least one opening therein on the second material layer; and etching the first and second material layers uncovered by the first and second patterned resist layers.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: September 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ching-Yu Chang
  • Patent number: 8258456
    Abstract: The present invention provides an image sensor. The image sensor comprises: a substrate, a plurality of optical elements, a first insulation layer, an anti-reflective coating (ARC) layer, a second insulation layer, and a color filter array. The optical elements are disposed in the substrate. The first insulation layer is disposed on the substrate and the optical elements. The ARC layer is disposed on the first insulation layer. The second insulation layer is disposed on the ARC layer. The color filter array is disposed on the second insulation layer, and the color filter array comprises a plurality of color filters corresponding to a plurality of different colors of light, respectively. The ARC layer comprises a plurality of sections directly below the color filters in a vertical direction, respectively, and the sections have different inherent reflection characteristics. The image sensor of the present invention can increase sensitivity and reduce crosstalk.
    Type: Grant
    Filed: November 27, 2009
    Date of Patent: September 4, 2012
    Assignee: Himax Imaging, Inc.
    Inventor: Desmond Cheung
  • Patent number: 8252659
    Abstract: The present disclosure is related to method for producing a semiconductor device comprising the steps of: providing a semiconductor substrate (1), comprising active components on the surface of said substrate, depositing a top layer (2) of dielectric material on the surface of said substrate or on other dielectric layers present on said surface, etching at least one first opening (7) at least through said top layer, filling said opening(s) at least with a first conductive material (8), and performing a first CMP step, to form said first conductive structures (3,26), etching at least one second opening (13) at least through said top layer, filling said opening(s) at least with a second conductive material (10), and performing a second CMP step, to form said second conductive structures (4,24), wherein the method comprises the step of depositing a common CMP stopping layer (5,25) on said dielectric top layer, before the steps of etching and filling said first opening(s), so that said same CMP stopping layer is
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: August 28, 2012
    Assignee: IMEC
    Inventors: Cedric Huyghebaert, Jan Vaes, Jan Van Olmen
  • Patent number: 8252694
    Abstract: A plasma etching method that can increase the selection ratio of a stop layer to an interlayer insulation film. The plasma etching method is carried out on a substrate that has the interlayer insulation film formed of CwFx (x and w are predetermined natural numbers) and a stop layer that stops etching and is exposed at the bottom of a hole or a trench formed in the interlayer insulation film. The interlayer insulation film and the stop layer are exposed at the same time to plasma generated from CyFz (y and z are predetermined natural numbers) gas and hydrogen-containing gas.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: August 28, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Naotsugu Hoshi, Noriyuki Kobayashi
  • Patent number: 8252614
    Abstract: At least one exemplary embodiment is directed to a solid state image sensor including at least one antireflective layer and/or non rectangular shaped wiring layer cross section to reduce dark currents and 1/f noise.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: August 28, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toru Koizumi, Akira Okita, Tetsuya Itano, Sakae Hashimoto, Ryuichi Mishima
  • Patent number: 8241992
    Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: August 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Maxime Darnon, Qinghuang Lin, Anthony D. Lisi, Satyanarayana V. Nitta
  • Publication number: 20120129337
    Abstract: A dual damascene process is disclosed. The process includes the steps of: forming a dielectric layer on a substrate; forming a first patterned mask on the dielectric layer, wherein the first patterned mask comprises an opening; forming a material layer on the dielectric layer and covering the first patterned mask; forming a second patterned mask on the dielectric layer, wherein the second patterned mask comprises a first aperture; forming a second aperture in the second patterned mask, wherein the second aperture and the first aperture comprise a gap therebetween; and utilizing the second patterned mask as etching mask for partially removing the material layer and the dielectric layer through the first aperture and the second aperture.
    Type: Application
    Filed: November 22, 2010
    Publication date: May 24, 2012
    Inventors: Shin-Chi Chen, Yu-Tsung Lai, Jiunn-Hsiung Liao, Guang-Yaw Hwang
  • Patent number: 8177990
    Abstract: Disclosed is a method of etching a substrate having a layered structure in which a photoresist mask with a pattern, a coating film made of silicon oxide, and an organic film are laminated in that order from the top. Before etching the coating film of silicon oxide, a deposit is deposited on the photoresist mask by using plasma generated from a hydrocarbon gas such as CH4 gas so as to narrow the size of openings in the pattern of the photoresist mask. The pattern of the photoresist mask is well transferred to the organic film through the coating film, and a pattern with openings having a high aspect ratio can be formed in the organic film and toppling of the pattern in the organic film can be prevented. The organic film with the transferred pattern is used as an etch mask for etching the underlying layer.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: May 15, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Ryou Mochizuki, Jun Yashiro