Abstract: A method of forming a metal line of a semiconductor memory device includes the steps of forming plugs of a damascene structure in a first interlayer insulating layer over a semiconductor substrate, forming a barrier metal layer, a metal layer and an anti-reflection layer on the resulting surface, etching the anti-reflection layer, the metal layer, and the barrier metal layer according a specific pattern, and forming an insulating layer on sidewalls of the metal layer.

Abstract: Provided is a method of fabricating a semiconductor device with a dual damascene pattern. According to the method, a diffusion barrier layer, dielectric, a capping layer, and an organic bottom anti-reflection coating (BARC) are sequentially formed on a substrate where a metal interconnection is formed. A photoresist pattern on the organic BARC is formed and the organic BARC, the capping layer, and the dielectric are selectively etched to form a trench using the photoresist pattern as a mask. The photoresist pattern and the organic BARC are removed, and a byproduct capping mask is formed by reacting the capping layer with a reaction gas to form a byproduct. A portion of the trench is filled with the byproduct. Then, a via hole is formed in the trench using the byproduct capping mask as a mask, and the byproduct capping mask, the diffusion barrier layer, and the capping layer are removed.

Abstract: A method of forming a dual damascene opening comprising the following steps. A structure having an overlying exposed conductive layer formed thereover is provided. A dielectric layer is formed over the exposed conductive layer. An anti-reflective coating layer is formed over the dielectric layer. The anti-reflective layer and the dielectric layer are etched using a via opening process to form an initial via exposing a portion of the conductive layer. A protective film portion is formed over at least the exposed portion of the conductive layer. The anti-reflective coating layer and the dielectric layer are patterned to reduce the initial via to a reduced via and to form a trench opening substantially centered over the reduced via. The trench opening and the reduced via comprising the dual damascene opening.

Abstract: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).

Abstract: A method for manufacturing a semiconductor device of the present invention includes: forming a first film, a second film and a third film in sequence on a silicon substrate; patterning a resist film formed on the third film by conducting an exposure and developing process for the resist film employing an exposure mask including a phase shifter; selectively dry-etching the third film through a mask of the resist film employing the second film as an etch stop to process the third film into a first pattern; further dry-etching the third film employing the second film as an etch stop to partially remove the third film, thereby processing the third film into a second pattern; patterning the second film employing the third film having the second pattern as a mask; and patterning the first film employing the patterned second film as a mask.

Abstract: A method of forming an insulative film includes a step of vacuum laminating an insulative organic material on a substrate that has a peripheral ring electrode formed in a peripheral region of the substrate and a device element(s) formed inside the peripheral region, and has a surface configuration including raised parts. A first dummy pattern is formed in a region between the peripheral ring electrode and the device element on the substrate.

Abstract: A process for forming an ARC layer in the fabrication of a semiconductor device comprises forming a modified ARC layer that increases the resistance to crown defects and bridging and also provides better adhesion for the ARC layer with the underlying metal layer. The modified ARC layer can comprise two titanium nitride ARC layers, a titanium nitride/titanium/titanium nitride sandwich structure, a modified titanium nitride layer, or an extended thickness titanium nitride layer.

Abstract: A lithographic structure consisting essentially of: an organic antireflective material disposed on a substrate; a vapor-deposited RCHX material, wherein R is one or more elements selected from the group consisting of Si, Ge, B, Sn, Fe and Ti, and wherein X is not present or is one or more elements selected from the group consisting of O, N, S and F; and a photoresist material disposed on the RCHX material. The invention is also directed to methods of making the lithographic structure, and using the structure to pattern a substrate.

Abstract: A method for fabricating a conducting layer pattern using a hard mask of which a upper surface is flattened by the use of ArF exposure light source.

Abstract: A method for manufacturing a semiconductor device is provided. First, a first metal conductive line is formed, and then a semiconductor device is formed on the first metal conductive line. A dielectric layer is formed on the semiconductor device. A contact window is formed at a position in the dielectric layer corresponding to the first metal conductive line. Then, a metal plug is formed in the contact window. The metal plug is used as a mask for etching the semiconductor device, such that the etched semiconductor device takes the form of a shape corresponding to the metal plug. Through the manufacturing method, the semiconductor device is formed according to the shape of the metal plug and is completely aligned with the metal plug.

Abstract: A process of physical vapor depositing mirror layer with improved reflectivity is disclosed. A wafer is loaded into a PVD tool comprising a degas chamber, a Ti/TiN sputter deposition chamber, a cooling chamber, and an aluminum sputter deposition chamber. A wafer degas process is first performed within the degas chamber. The wafer is then transferred to the Ti/TiN sputter deposition chamber and deposition sputtering a layer of titanium onto the wafer. The wafer is transferred to the cooling chamber and gas cooling the wafer temperature down to 40-50° C. The wafer is then transferred to the aluminum sputter deposition chamber and deposition sputtering a layer of aluminum onto the wafer at 40-50° C. with a backside gas turned off. The deposited layer of aluminum over the wafer has a reflectivity of about 0.925 at wavelength of around 380 nm.

Abstract: A method for depositing a Ru metal layer on a patterned substrate from a film precursor vapor delivered from a multi-tray film precursor evaporation system. The method comprises providing a patterned substrate in a process chamber of a deposition system, and forming a process gas containing Ru3(CO)12 precursor vapor and a carrier gas comprising CO gas. The process gas is formed by: providing a solid Ru3(CO)12 precursor in a plurality of spaced trays within a precursor evaporation system, wherein each tray is configured to support the solid precursor and wherein the plurality of spaced trays collectively provide a plurality of surfaces of solid precursor; heating the solid precursor in the plurality of spaced trays in the precursor evaporation system to a temperature greater than about 60° C.

Abstract: A treatment method for a surface of a photoresist layer is provided. After forming a patterned photoresist layer over a wafer, a surface treatment step is performed to the photoresist layer by using at least one reaction gas comprising hydrogen bromide or hydrogen iodide to form a hardened layer over the surface of the photoresist layer. Wherein, the surface treatment step and the etching step are in-situ performed.

Abstract: Interconnect structures possessing an organosilicate glass interlayer dielectric material with minimal stoichiometeric modification and optionally an intact organic adhesion promoter for use in semiconductor devices are provided herein. The interconnect structure is capable of delivering improved device performance, functionality and reliability owing to the reduced effective dielectric constant of the stack compared with that of those conventionally employed because of the use of a sacrificial polymeric material deposited onto the dielectric and optional organic adhesion promoter during the barrier open step done prior to ashing the patterning material. This sacrificial film protects the dielectric and optional organic adhesion promoter from modification/consumption during the subsequent ashing step during which the polymeric film is removed.

Abstract: An etching method is described, including a first etching step and a second etching step. The temperature of the second etching step is higher than that of the first etching step, such that the after-etching-inspection (AEI) critical dimension is smaller than the after-development-inspection (ADI) critical dimension.

Abstract: An etching method for semiconductor element is provided. The etching method includes the following procedure. First, a to-be-etched substrate is provided. Then, a silicon-rich silicon oxide (SRO) layer is formed on the to-be-etched substrate. Afterwards, an anti-reflective layer is formed on the SRO layer. Then, a patterned photo resist layer is formed on the anti-reflective layer. Afterwards, the anti-reflective layer, the SRO layer and the to-be-etched substrate is etched so as to form an opening.

Abstract: According to one aspect of the invention, a method of constructing a memory array is provided. An insulating layer is formed on a semiconductor wafer. A first metal stack is then formed on the insulating layer and etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. A puddle of smoothing solvent is then allowed to stand on the wafer. The smoothing solvent is then removed. After the smoothing solvent is removed, the polymeric layer has a reduced surface roughness. A second metal stack is then formed on the polymeric layer and etched to form second metal lines.

Abstract: The present invention relates to a spin-on antireflective coating composition for a photoresist comprising a polymer, a crosslinking compound and a thermal acid generator, where the polymer comprises at least one functional moiety capable of increasing the refractive index of the antireflective coating composition to a value equal or greater than 1.8 at exposure radiation used for imaging the photoresist and a functional moiety capable of absorbing exposure radiation used for imaging the photoresist. The invention further relates to a process for imaging the antireflective coating of the present invention.

Abstract: A method for fabricating a semiconductor device includes forming an interlayer insulating film over a semiconductor substrate. The interlayer insulating film is selectively etched to form a hole defining a storage node region. A lower electrode is formed in the hole. A support layer is formed over the lower electrode. The support layer fills an upper part of the hole and exposes the interlayer insulating film. A dip-out process is performed to remove the interlayer insulating film. The supporting layer is removed to expose the lower electrode. A dielectric film is formed over the semiconductor substrate including the lower electrode. A plate electrode is formed over the semiconductor substrate to fill the dielectric film and the lower electrode.

Abstract: A method of reworking a semiconductor substrate and a method of forming a pattern of semiconductor device using the same without damage to an organic anti-reflective coating (ARC) is provided. The method of reworking a semiconductor substrate includes forming a photoresist pattern on a substrate having the organic ARC formed thereon. An entire surface of the substrate having the photoresist pattern formed thereon may be exposed when a defect is present in the photoresist pattern. The entire-surface-exposed photoresist pattern may be removed by performing a developing process without damage to the organic ARC.

Abstract: An AlCu film is formed by simultaneously depositing AlCu within a via hole and on top of an interlayer dielectric film. The surface of the AlCu film is polished using a CMP process, and a TiN antireflection layer is formed thereon. The TiN antireflection layer having a flat surface prevents halation during pattering the interconnections including the AlCu film, thereby preventing ingress of etching solution during a subsequent wet etching process.

Abstract: Techniques are disclosed for fabricating a device using a photolithographic process. The method includes providing a first anti-reflective coating over a surface of a substrate. A layer which is transparent to a wavelength of light used during the photolithographic process is provided over the first anti-reflective coating, and a photosensitive material is provided above the transparent layer. The photosensitive material is exposed to a source of radiation including the wavelength of light. Preferably, the first anti-reflective coating extends beneath substantially the entire transparent layer. The complex refractive index of the first anti-reflective coating can be selected to maximize the absorption at the first anti-reflective coating to reduce nothing of the photosensitive material.

Abstract: A method and structure for a single or dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, patterning the laminated insulator stack, forming vias in the patterned laminated insulator stack, creating sidewall spacers in the bottom portion of the vias, depositing an anti-reflective coating on the sidewall spacers, etching the troughs, removing the anti-reflective coating, depositing a metal layer in the troughs, vias, and sidewall spacers, and applying conductive material in the troughs and the vias. The laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene.

Abstract: A method for forming a dual damascene structure is provided. In one embodiment, a semiconductor substrate with a patterned protective layer formed thereover is provided. A conformal dielectric layer is formed over the protective layer. A patterned mask layer is formed over the dielectric layer. A portion of the dielectric layer is etched substantially up to about the top surface of the protective layer according to the pattern of the mask layer to form a trench. The protective layer is then removed to form a via hole. A conductive layer is formed in the via hole and the trench, thereby forming a dual damascene structure.

Abstract: A bi-layer anti-reflective coating for use in photolithographic applications, and specifically, for use in ultraviolet photolithographic processes. The bi-layered anti-reflective coating is used to minimize pattern distortion due to reflections from neighboring features in the construction of microcircuits. The bi-layer anti-reflection coating features a first layer, an absorption layer, disposed on a second layer, a dielectric layer, which is then disposed between a substrate and a photoresist layer. The dielectric/absorption layer comprises one combination selected from Ta/Al2O3, Ta/SiO2, Ta/TiO2, Ta/Ta2O5, Ta/Cr2O3, Ta/Si3N4, Ti/Al2O3, Ti/SiO2, Ti/TiO2, Ti/Ta2O5, Ti/Cr2O3, Ti/Si3N4, Cr/Al2O3, Cr/SiO2, Cr/TiO2, Cr/Ta2O5, Cr/Cr2O3, Cr/Si3N4, Al/Al2O3, Al/TiO2, Al/Ta2O5, Al/Cr2O3, Al/Si3N4, Ni/Al2O3, Ni/SiO2, Ni/TiO2, Ni/Ta2O5, Ni/Cr2O3, Ni/Si3N4, Ir/Al2O3, Ir/SiO2, Ir/TiO2, Ir/Ta2O5, Ir/Cr2O3, and Ir/Si3N4. At least the absorption and dielectric layers can be formed using vacuum deposition.

Abstract: An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and top electrodes. The nanotips may have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. Typically, the nanotips are formed from iridium oxide (IrOx) nanotips. A MOCVD process forms the Ir bottom electrode. The IrOx nanotips are grown from the Ir. In one aspect, the Si phosphor layer is a SRSO layer. In response to an SRSO annealing step, nanocrystalline SRSO is formed with nanocrystals having a size in the range of 1 to 10 nm.

Abstract: Anti-reflective materials such as bottom anti-reflective coatings (BARC's) and sacrificial light absorbing materials (SLAM) may be made more effective at preventing coherent light or electron beam reflection from a substrate by including in the anti-reflective material an additive to alter the radiation beam path of the reflected light or electrons. The radiation beam path altering additive may be a reflective material or a refractive material. The inclusion of such a radiation beam bath altering additive may reduce line width roughness and increase critical dimension (CD) control of interconnect lines and vias.

Abstract: A method of reducing critical dimensions of a feature in a anti-reflective coating layer structure can utilize a polymerizing agent. The anti-reflective coating structure can be utilized to form various integrated circuit structures. The anti-reflective coating can be utilized to form gate stacks comprised of polysilicon and a dielectric layer, conductive lines, or other IC structure. The polymerizing agent can include carbon, hydrogen and fluorine.

Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

Abstract: Methods of fabricating a microelectronic device having improved performance characteristics are disclosed which are characterized by using super critical fluid to perform a material removal step. In one illustrative embodiment, the method includes preparing a substrate, forming an HSQ layer covering at least a portion of the substrate, and thereafter removing at least portions of the HSQ layer using super critical fluid CO2.

Abstract: Disclosed are methods of fabricating a memory cell structure. More specifically, a copper substrate, including but not limited to copper contacts and/or bit lines, can be formed within a metal-containing layer, for example. Optionally, one or more via openings can then be formed in an overlying dielectric layer to expose one or more of the copper contacts and/or bit lines. Copper sulfide material can be formed thereon. Alternatively, a portion of the exposed copper can be converted to copper sulfide (e.g., Cu2S2 or Cu2S). The copper sulfide material can then be exposed to a vapor phase monomer to facilitate selective growth of a conducting polymer.

Abstract: In the manufacture of a semiconductor, a DBARC layer is deposited upon a wafer to prevent reflection. A photo resist layer is deposited upon the DBARC layer and the wafer is selectively exposed to irradiation. The irradiation generates photo acid (H+ ions) in the exposed areas of the photo resist and DBARC. In order to provide better resolution in the DBARC for micro-features, an electric field is generated vertically through the coated wafer before or during post exposure baking (PEB) to create a uniform vertical distribution of H+ ions though the DBARC. The coated wafer is then developed to remove either the unexposed portions, or exposed portion of the DBARC. The cavities formed by the developer have side walls that are substantially vertical as a result of the uniform vertical distribution of the H+ ions.

Abstract: A method for manufacturing a semiconductor device which, on performing a via first Dual Damascene process, inhibits or prevents the formation of a void in a bottom anti-reflective coating filling a via hole. The method typically includes the steps of forming a bottom anti-reflective coating (BARC) in a via hole in an interlayer dielectric on a semiconductor substrate sufficiently to fill the via hole; disposing an acid diffusion material on the BARC; forming a cross-link layer between the BARC and the acid diffusion material; removing the remaining acid diffusion material; and etching the cross-link layer, the BARC and the interlayer dielectric to form a trench extending from an upper portion of the via hole.

Abstract: A method for fabricating an insulating layer having contact openings of varying depths for logic/DRAM circuits is achieved using a single mask and etch step. After forming stacked or trench capacitors, a planar insulating layer is formed. Contact openings are etched in the planar insulating layer to the substrate, and contact openings that extend over the edge of the stacked or trench capacitor top electrode, having an ARC, are etched using a novel mask design and a single etching step. This allows one to make contacts to the substrate without overetching while making low-resistance contacts to the sidewall of the capacitor top electrode. In the trench capacitor open areas are formed to facilitate making contact openings that extend over the top electrode. A series of contact openings that are skewed or elongated also improve the latitude in alignment tolerance.

Abstract: The present invention provides a nitrogen-free ARC layer, which is formed on the basis of silane and carbon dioxide by PECVD in a nitrogen-free deposition atmosphere. The optical characteristics may be tuned in a wide range, wherein, in particular, a back reflection into the resist is maintained at 3% or less. The ARC layer is well suited for 193 nm lithography.

Abstract: The present invention includes an embodiment that relates to method of forming an interconnect. The method includes the effect of reducing electromigration in a metallization. An article achieved by the inventive method includes a first interconnect disposed above a substrate; a first conductive diffusion barrier layer disposed above and on the first interconnect; an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect; and an upper conductive diffusion barrier layer disposed above and on the upper interconnect.

Abstract: A semiconductor component having a composite via structure with an enhanced aspect ratio and a method for manufacturing the semiconductor component. Vias having a first aspect ratio are formed in a contact layer disposed on a semiconductor substrate and filled with a metal. The metal is planarized and a dielectric layer is formed over the contact layer. Via extension structures having the same aspect ratio as those in the contact layer are formed in the dielectric layer and aligned with the vias in the contact layer. The vias in the dielectric layer are filled with metal and the metal is planarized. The contact vias in the contact layer and the dielectric layer cooperate to form a composite via structure having the enhanced aspect ratio. Additional dielectric layers having via structures can be included in the composite contact structure to further enhance the aspect ratio of the via structure.

Abstract: The present invention provides a nitrogen-free ARC/capping layer in a low-k layer stack, which, in particular embodiments, is comprised of carbon-containing silicon dioxide, wherein the optical characteristics are tuned to conform to the 193 nm lithography. Moreover, the ARC/capping layer is directly formed on the low-k material, thereby also preserving the integrity thereof during an etch and chemical mechanical polishing process.

Abstract: A polymer for forming an organic anti-reflective coating layer between an etching layer and a photoresist layer to absorb an exposure light in a photolithography process and a composition comprising the same are disclosed. The polymer for forming an organic anti-reflective coating layer has repeating units represented by wherein, R is a substituted or non-substituted alky group of C1 to C5.

Abstract: Methods of forming a multi-level metal line of a semiconductor device are disclosed. One example method includes subsequently stacking first and second metal layers, wherein a conductive etching stopper layer is interposed at an interface between the first and second metal layers; forming first and second metal layer pattern by patterning the first metal layer, the etching stopper layer, and the second metal layer, wherein the first metal layer pattern is formed as a lower metal line; forming a connection contact in form of a plug by selectively etching the second metal layer pattern until the etching stopper layer is exposed; forming an interlayer insulating layer to cover the connection contact and the first metal layer pattern; and exposing an upper surface of the connection contact by planarizing the interlayer insulating layer.

Abstract: Inwardly-tapered openings are created in an Anti-Reflection Coating layer (ARC layer) provided beneath a patterned photoresist layer. The smaller, bottom width dimensions of the inwardly-tapered openings are used for defining further openings in an interlayer dielectric region (ILD) provided beneath the ARC layer. In one embodiment, the ILD separates an active layers set of an integrated circuit from its first major interconnect layer. Further in one embodiment, a taper-inducing etch recipe is used to create the inwardly-tapered ARC openings, where the etch recipe uses a mixture of CF4 and CHF3 and where the CF4/CHF3 volumetric inflow ratio is substantially less than 5 to 1, and more preferably closer to 1 to 1.

Abstract: A method including introducing a dielectric layer over a substrate between an interconnection line and the substrate, the dielectric layer comprising a plurality of alternating material layers; and patterning an interconnection to the substrate. An apparatus comprising a substrate comprising a plurality of devices formed thereon; and an interlayer dielectric layer comprising a base layer and a cap layer, the cap layer comprising a plurality of alternating material layers overlying the substrate.

Abstract: The method prevents oxidation or contamination phenomena of conductive interconnection structures in semiconductor devices and includes providing a layer of semiconductor or oxide base, a conductive layer or stack on the base layer, and an antireflection coating (ARC) layer on the conductive layer or stack. The method provides a thin dielectric covering layer on the antireflection coating layer to fill or cover the microfissures existing in the antireflection coating layer.

Abstract: The invention pertains to films comprising silicon, oxygen and carbon and the use of the films in integrated circuit technology, such as capacitor constructions, DRAM constructions, semiconductive material assemblies, etching processes, and methods for forming capacitors, DRAMs and semiconductive material assemblies. One particular disclosed film is an anti-reflective coating, and a method of formation thereof.

Abstract: An anti-reflective coating layer for the manufacturing of semiconductor devices is disclosed. In one example, a partial semiconductor device includes a substrate; a bottom anti-reflective coating (BARC) layer over the substrate, and the BARC layer is transformed from being hydrophobic to being hydrophilic during a lithography process; and a photoresist layer over the BARC layer.

Abstract: To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

Abstract: In accordance with the objectives of the invention a new method is provided for the creation of an interconnect pattern. The invention provides for a layer of Photo-Active Dielectric (PAD) to be used for the insulation material in which the interconnect pattern is created, this without the use of an overlying exposure mask of photoresist.

Abstract: A method of fabricating an integrated circuit (IC), during which wafer warpage is controlled by appropriately controlling intrinsic stresses in one or more service layers of the layer stack of the IC's multilevel interconnect structure. In one embodiment, each interconnect level of the multilevel interconnect structure has a dielectric layer, a conducting layer formed over the dielectric layer, and a service anti-reflective coating (ARC) layer formed over the conducting layer. Each ARC layer is formed from silicon oxynitride such that at least two ARC layers corresponding to different interconnect levels have different intrinsic stresses. The amount of intrinsic stress in each ARC layer is controlled, e.g., through the control of temperature and/or gas composition during the layer deposition.

Abstract: A method for forming a dual damascene interconnection in a semiconductor device, which is capable of preventing a lower metal film from being corroded. The method includes the steps of forming an etch stop film and an intermetal insulating film sequentially on a lower metal film to be interconnected, forming a via hole for exposing a portion of a surface of the etch stop film through the intermetal insulating film, and forming a trench having a width wider than that of the via hole on the intermetal insulating film. The method also includes the steps of exposing the lower metal film by removing the etch stop film by performing an etching process using an etching equipment of a dual plasma source, performing a nitrogen passivation process for the exposed lower metal film, and forming a barrier metal film and an upper metal film sequentially within the trench and the via hole.

Abstract: A BARC or other sacrificial fill layer etch comprises a selective etch chemistry of Ar/O2/CO. The BARC etch may be used in a via-first dual damascene method. After via (116) pattern and etch, a BARC/sacrificial fill layer (120) is deposited to fill the via (116) and coat the IMD (110). The excess sacrificial fill layer (120) material over the IMD (110) is removed using the Ar/O2/CO etch. A trench resist pattern (125) is formed over the BARC layer (120). During the main trench etch, portions of sacrificial fill layer (120) remain in the via to protect the etch-stop (104) at the bottom of the via (116).