Abstract: A semiconductor device and fabrication method thereof that uses a far ultraviolet ray photolithography, which may be used to prevent the lift phenomenon of a photoresist pattern, is disclosed. The semiconductor device may be fabricated by the process of: forming a film which is an object of forming a pattern on a structure of a semiconductor substrate; forming a anti-reflection layer on the film to form a stacking structure including the film and the anti-reflection layer; performing a plasma treatment to form grooves on a upper surface of the stacking structure; forming a photoresist pattern on the stacking structure on which the grooves are formed; and etching the stacking structure using the photoresist pattern as a mask to form a stacking structure pattern.

Abstract: To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

Abstract: A method for determining an optical constant of an bottom antireflective layer formed between a resist film and an underlying substrate in an optical lithography process in a process for fabricating a semiconductor device, the resist film having an absorption coefficient ?? of 1.5 ?m?1 to 3.

Abstract: A method of fabricating a solid-state imaging device is provided, which enables the formation of an anti-reflection film by oxidizing a surface of a metallic light-shield film without adding additional steps, even though the metallic light-shield film is composed of not only refractory metal silicide but also metals, including tungsten and molybdenum. The method comprises the steps of forming a metallic light-shield film on a light receiving sensor and a transfer electrode formed on a surface layer of a wafer, forming an opening on the metallic light-shield film on the light receiving sensor by etching, forming an interlayer film, and shaping the interlayer film into a lens shape by heat treatment. An atmosphere of either one or both of oxygen gas and ozone gas is prepared in a chamber for forming the interlayer film, and a surface of the metallic light-shield-film is oxidized before the interlayer film is formed.

Abstract: An aspect of the present invention is directed to an avalanche photodiode (APD) device for use in oil well drilling applications in harsh, down-hole environments where shock levels are near 250 gravitational acceleration (G) and/or temperatures approach or exceed 150° C. Another aspect of the present invention is directed to an APD device fabricated using SiC materials. Another aspect of the present invention is directed to an APD device fabricated using GaN materials.

Abstract: A process is described for transferring a photoresist pattern into a substrate. In one embodiment a stack comprised of a top photoresist layer, a middle ARC layer, and a bottom hardmask is formed over a gate electrode layer. A line in the photoresist pattern is anisotropically transferred through the ARC and hardmask. Then an isotropic etch to trim the linewidth by 0 to 50 nm per edge is performed simultaneously on the photoresist, ARC and hardmask. This method minimizes the amount of line end shortening to less than three times the dimension trimmed from one line edge. Since a majority of the photoresist layer is retained, the starting photoresist thickness can be reduced by 1000 Angstroms or more to increase process window. The pattern is then etched through the underlying layer to form a gate electrode. The method can also be used to form STI features in a substrate.

Abstract: After a wiring material layer (14) which is made of WSi2 or the like is formed on an insulation film covering a semiconductor substrate (10), a first antireflection coating film (16) which is made of TiON or TiN and a second antireflection coating film (18) which is made of an organic material are sequentially formed on the wiring material layer (14). Resist patterns (20a to 20c) are formed on the second antireflection coating film (18) by photolithography. The dry etching of the second antireflection coating film (18) is performed using the resist patterns (20a to 20c) as masks, after which the dry etching of the first antireflection coating film (16) is conducted using the resist patterns (20a to 20c) and patterns (18a to 18c) of the second antireflection coating film (18) as masks.

Abstract: A via hole 18 is opened in an interlayer insulating film 17, which covers a lower layer interconnect 12, a protective film 19 is embedded on the base portion of the via hole 18, and a soluble resin 20, which dissolves in a resist developing fluid under unexposed conditions, is further embedded thereupon. On this basis, a photoresist 21 is applied, and this photoresist 21 is subjected to an exposure and a development process so as to form a resist pattern 21a, which has an aperture window in a region including the via hole. Upon formation of an interconnective trench in the interlayer insulating film 17 utilizing the resist pattern 21a, a dual damascene structure is formed by embedding a metallic material into the vial hole and interconnective trench.

Abstract: A method for fabricating a semiconductor device by simultaneously forming via holes in a multi-layered structure having depth differences without requiring additional process steps. Steps to achieve this effect include forming a first conductive layer; forming a first etching protection layer on the first conductive layer; forming a first insulating layer; forming a second conductive layer on the first insulating layer; forming a second etching protection layer on the second conductive layer, wherein etching protection efficiency of the second protection layer is higher than that of the first etching protection layer; forming a second insulating layer; and forming a first and a second via hole respectively exposing the first and the second conductive layer by selectively etching the first and second insulating layer.

Abstract: A method for determining the anti-reflective coating (or bottom anti-reflective coating) over-etch time adjust with real-time process feedback is presented. The critical dimension CDresist of the patterned photoresist is measured and a first wafer with median values chosen (101) from a lot. A first time t★ is found (102) and used to form the desired structure. Using the measured critical dimension of the formed structure on the first wafer a second time tlot is found (104). Finally, an over-etch time t(x) is found and used to etch the remaining wafers in the lot (106).

Abstract: In a distributed feedback type semiconductor layer diode including a semiconductor substrate, an optical guide layer formed on the semiconductor substrate, a diffraction grating having a phase shift region being formed between the semiconductor substrate and the optical guide layer, and an active layer formed on the optical guide layer, &kgr;L+A·&Dgr;&lgr;≧B where &kgr; is a coupling coefficient of the diffraction grating, L is a cavity length of the diode, &Dgr;&lgr; is a detuning amount denoted by &Dgr;&lgr;=&lgr;g−&lgr; where &lgr;g is a gain peak wavelength of the diode and &lgr; is an oscillation wavelength of the diode, A is a constant from 0.04 nm−1 to 0.06 nm−1, and B is a constant from 3.0 to 5.0.

Abstract: Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a plurality of light absorbing layers having a combined extinction coefficient >0.5. As reflected light passes through the light absorbing layers, a substantially amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photo-lithography. Following patterning of the photoresist, isolation trenches are formed in the semiconductor substrate by etching through the light absorbing layers and into the semiconductor substrate in accordance with the pattern formed on the photoresist.

Abstract: A method of manufacturing electronic devices containing one or more layers of materials that are sensitive to the strong chemicals used to remove cross-linked polymeric layers such as photoresists and antireflective coatings is provided. The cross-linked polymeric layers can be easily removed following etching through the use of certain removable layers disposed between the substrate and the cross-linked polymeric layers.

Abstract: An integrated device comprises a first conductive region and a first insulating region of dielectric material covering the first conductive region. A first through region of electrically conductive material extends inside the first insulating region, and is in direct electrical contact with the first conductive region. A second conductive region, arranged above the first insulating region, is in a position not aligned and not in contact with the first through region. A second insulating region of dielectric material covers the second conductive region. A second through region of electrically conductive material extends inside the second insulating region as far as the first through region and is aligned and in direct electrical contact with the first through region. A third conductive region, arranged above the second insulating region, is aligned and in direct electrical contact with the second through region.

Abstract: After an etching stop layer and an interlayer dielectric film are formed on a semiconductor substrate including a contact formation portion, a polysilicon film and a anti-reflective layer are successively formed on the interlayer dielectric film. A second mask pattern exposing the polysilicon film is formed after etching the anti-reflective layer exposed through a first mask pattern. A third mask pattern is formed by attaching polymer on a sidewall of the second mask pattern. A contact hole exposing the contact formation portion is formed by etching the polysilicon film and the interlayer dielectric film using the third mask pattern as an etching mask. A conductive material is filled in the contact hole to form the contact. By attaching the polymer to the second mask pattern, a contact hole with a minute size can be formed.

Abstract: A method of fabricating an integrated circuit in and on a semiconductor substrate with deep implantations by applying a scattered ion capturing layer in the resist mask opening to capture any implanted ions scattered in the resist and deflected out of the resist into the mask opening to prevent these ions from reaching the semiconductor substrate and affecting the concentration of ions at the edge of the mask and thus the performance of the integrated circuit.

Abstract: A CMP process for selectively polishing an overlying material layer with an underlying layer comprising at least one material in a semiconductor device fabrication process including providing a semiconductor wafer process surface including a first material layer overlying a second layer including one material; mixing at least two slurry mixtures including a first CMP slurry formulation optimized for removing the first material layer and a second CMP slurry formulation optimized for removing the at least a second layer to form a slurry formulation mixture; and, carrying out a CMP process using the slurry formulation mixture to remove the first material layer and at least a portion of the at least a second layer.

Abstract: An EB curing process is performed on a photoresist (7), with an energy beam absorbing film (5) formed on a low dielectric constant interlayer insulator film (4).

Abstract: A method of forming a metal-oxide-metal (MIM), capacitor structure wherein the fabrication procedures used for the MIM capacitor structure are integrated into a process sequence used to form damascene type copper interconnect structures for CMOS type devices, has been developed. The process sequence features a copper damascene connector located overlying exposed portions of a semiconductor substrate, and underlying the MIM capacitor structure. The MIM capacitor structure, comprised a capacitor dielectric layer sandwiched between conductive capacitor plates, is protected during several selective reactive ion etching patterning procedures by an overlying anti-reflective coating (ARC), insulator shape, and by insulator spacers located on the sides of the ARC shape and on the sides of a capacitor dielectric shape.

Abstract: A BARC etch comprises a selective etch chemistry in combination with a high-polymerizing gas for CD control. The BARC etch may be used in a via-first dual damascene method. After via (116) pattern and etch, a thick BARC layer (120) is deposited to fill the via (116) and coat the IMD (110). A trench resist pattern (125) is formed over the BARC layer (120). Then, the exposed portion of BARC (120) over the IMD (110) is etched using a high-polymerizing gas added to a selective etch chemistry. The more polymerizing gas passivates the trench resist (125) sidewall to preserve or improve the trench CD. During the main trench etch, portions of BARC (120) remain in the via to protect the etch-stop (104) at the bottom of the via (116).

Abstract: In one aspect, the invention includes a semiconductor processing method comprising exposing silicon, nitrogen and oxygen in gaseous form to a high density plasma during deposition of a silicon, nitrogen and oxygen containing solid layer over a substrate.

Abstract: A photodetector device includes a doped semiconductor substrate. A first intrinsic semiconductor material layer, a main reflector, a second intrinsic semiconductor material layer, an upper semiconductor material layer, which is doped the opposite as the substrate, are formed in succession on the semiconductor substrate. An upper electrode is formed on and electrically connected with the upper semiconductor layer, and a lower electrode is electrically connected to the semiconductor substrate. One of the intrinsic semiconductor layers is relatively thin to absorb incident light, while the other is relatively thick. The photodetector device, a p-i-n photodetector, has an I region including the intrinsic semiconductor layers with different thicknesses, and a main reflector therebetween. The thickness of the entire I region can be increased with a reduced transit distance for holes.

Abstract: A portion, positioned at an opening portion of a resist, of an anti-reflection film is etched using an etching gas containing a substituted hydrocarbon with a halogen. At the time of etching of the anti-reflection film, a carbon component of the substituted hydrocarbon with a halogen is formed as a carbonaceous deposit on side walls, less irradiated with ions, of the opening portion of the resist, and on side walls of an opening portion, formed by etching, of the anti-reflection film. The deposit acts as a side wall blocking film, to suppress lateral extension of the opening portion of the resist and the opening portion of the anti-reflection film by etching, thus allowing anisotropic etching of the anti-reflection film. With this etching method, it is possible to etch the anti-reflection film with a resist taken as a mask while suppressing a variation in pattern dimension.

Abstract: An anti-reflective coating material layer is provided that has a relatively high etch rate such that it can be removed simultaneously with the cleaning of a defined opening in a relatively short period of time without affecting the critical dimensions of the opening. A method of forming such a layer includes providing a substrate assembly surface and using a gas mixture of at least a silicon containing precursor, a nitrogen containing precursor, and an oxygen containing precursor. The layer is formed at a temperature in the range of about 50° C. to about 600° C. Generally, the anti-reflective coating material layer deposited is SixOyNz:H, where x is in the range of about 0.39 to about 0.65, y is in the range of about 0.02 to about 0.56, z is in the range of about 0.05 to about 0.33, and where the atomic percentage of hydrogen in the inorganic anti-reflective coating material layer is in the range of about 10 atomic percent to about 40 atomic percent.

Abstract: A plasma chamber for performing semiconductor wafer processing within a wafer track system. The processing chamber may be configured as a thermal stack module within a wafer track cell for exposing a semiconductor wafer surface to a processing plasma. A showerhead electrode and wafer chuck assembly may be positioned within the processing chamber for effecting plasma-enhanced processing of the semiconductor wafer. Various types of supply gas sources may be in fluid communication with the showerhead electrode to provide a gaseous mixture that forms the desired plasma. The flow of gases may be regulated by a controller and a series of gas control valves to form and introduce the preselected gaseous mixture into the processing chamber as plasma that is exposed to the semiconductor wafer surface. The preselected gaseous mixture may be formulated for different semiconductor wafer processing operations such as surface prime treatment and bottom anti-reflective coating (BARC) deposition.

Abstract: A multi-layer wiring structure is formed by using a dual damascene method. First and second interlayer insulating films formed on a lower conductor layer are etched by using a first photo resist film as a mask to form a via hole. An anti-reflective coating is formed on the second interlayer insulating film such that a portion of the via hole is also filled therewith. A second photo resist film is formed on the anti-reflective coating such that a remaining portion of the via hole is also filled therewith. A development rate of an exposed portion of the second photo resist film is selected to be 250-700 nm/second. A wiring trench pattern is formed in the second photo resist film, and the anti-reflective coating and the second interlayer insulating film is etched by using the second photo resist film as a mask to form a wiring trench. The via hole and the wiring trench are filled with a conductive material to form a via and a wiring conductor.

Abstract: A first dielectric layer (30) and a second dielectric layer (40) are formed over an etch stop layer (20). A hardmask layer (50) is formed over the second dielectric layer and a via (62) is formed in the first dielectric layer (30) and the second dielectric layer (40). A trench (85) is formed mostly in the second dielectric layer (40) by fully or partially removing BARC from the via (62) are partially etching the trench (85) and prior to completion of the trench etch process.

Abstract: Insulating films 34 through 38 (of which insulating films 34, 36, 38 are silicon nitride films and insulating films 35, 38 are silicon oxide films) are sequentially formed on the wires 33 of the fourth wiring layer and groove pattern 40 is transferred into the insulating film 38 by means of photolithography. An anti-reflection film 41 is formed to fill the grooves 40 of the insulating film 38 and then a resist film 42 carrying a hole pattern 43 is formed. The films are subjected to an etching operation in the presence of the resist film 42 to transfer the hole pattern into the insulating films 38, 37, 36 and part of the insulating film 35. Subsequently, the resist film 42 and the anti-reflection film 41 are removed and the groove pattern 40 and the hole pattern 43 are transferred respectively into the insulating film 37 and the insulating film 35 by using the insulating film 38 as mask.

Abstract: A semiconductor product has an anti-reflective coating layer covering a semiconductor substrate. The ARC layer is formed of a matrix substance and of nanocrystalline particles of another material than the matrix substance. The nanocrystalline particles absorb light via the quantum size effect, that is, the novel kind of ARC layer is an absorbing ARC layer.

Abstract: A temperature-controlled focus ring assembly for use in a plasma chamber that includes a focus ring surrounding a wafer pedestal for confining plasma ions to a top surface of a wafer positioned on the wafer pedestal; a heat transfer means in intimate contact with the focus ring for decreasing or increasing the temperature of the focus ring; and a controller for controlling the temperature of the focus ring to a predetermined value. The invention further discloses a method for operating a plasma chamber equipped with a temperature-controlled focus ring assembly.

Abstract: A method for preventing a diffused reflection from being generated in patterning a via hole for the metal interconnection is disclosed. The disclosed method includes: forming an insulation layer on a semiconductor substrate, wherein elements for operating a semiconductor device are formed on the semiconductor substrate; forming first photoresist patterns on the insulation layer; etching the insulation layer in order to form a first via hole using the first photoresist patterns and then forming a resulting structure; coating a first anti-reflecting coating layer on the resulting structure with a low viscosity; coating a second anti-reflecting coating layer on the resulting structure with a low viscosity; forming second photoresist patterns on the second anti-reflecting coating layer; and forming a second via hole using the second photoresist patterns.

Abstract: An anti-reflective coating material layer is provided that has a relatively high etch rate such that it can be removed simultaneously with the cleaning of a defined opening in a relatively short period of time without affecting the critical dimensions of the opening. A method of forming such a layer includes providing a substrate assembly surface and using a gas mixture of at least a silicon containing precursor, a nitrogen containing precursor, and an oxygen containing precursor. The layer is formed at a temperature in the range of about 50° C. to about 600° C. Generally, the anti-reflective coating material layer deposited is SixOyNz:H, where x is in the range of about 0.39 to about 0.65, y is in the range of about 0.02 to about 0.56, z is in the range of about 0.05 to about 0.33, and where the atomic percentage of hydrogen in the inorganic anti-reflective coating material layer is in the range of about 10 atomic percent to about 40 atomic percent.

Abstract: A method of producing a protective inhibitor layer of moisture-generated corrosion for aluminum (Al) alloy metallization layers, particularly in semiconductor electronic devices, includes chemically treating the metallization layer in at least two steps using a mixture of concentrated nitric acid and trace phosphoric acid to produce a thin protective phosphate layer. Alternatively, the method may include dipping the electronic device at least once in a mixture of a polar organic solvent and phosphoric acid (H3PO4) or phosphate derivatives thereof in a low percentage amount (e.g., with a phosphate reactant such as orthophosphoric acid or even R—HxPOy, where R is an alkaline type of ion group or an alkyl radical). The thin film may be formed on top of a thin layer of native aluminum oxide hydrate Al2O3.xH2O.

Abstract: After a plurality of grooves are formed in an insulating film and in an anti-reflection film on the insulating film, a barrier metal film and a conductive film are deposited on the anti-reflection film such that each of the wiring grooves is filled therewith. Subsequently, the portions of the conductive film outside the grooves are removed by polishing and then the portions of the barrier metal film outside the wiring are removed by polishing. Thereafter, a foreign matter adhered to a surface to be polished during polishing is removed and then a surface of the anti-reflection film is polished.

Abstract: A first dielectric layer (30) and a second dielectric layer (40) are formed over an etch stop layer (20). A hardmask layer (50) is formed over the second dielectric layer and a via (62) is formed in the first dielectric layer (30) and the second dielectric layer (40). A trench (85) is formed mostly in the second dielectric layer (40) by fully or partially removing BARC from the via (62) are partially etching the trench (85) and prior to completion of the trench etch process.

Abstract: An improved and new process, used for the elimination of copper line damage, copper defects, non-uniformity improvement, with low dishing and erosion, in damacene processing, is disclosed. This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the elimination of copper line damage for damascene processing, by depositing a multilayer interface material, consisting of a mechanically hard film and a soft film, over a low dielectric constant, interlevel metal dielectric (IMD), and subsequently chemical mechanical polishing (CMP) back the excess material to planarize the surface.

Abstract: Antireflective structures according to the present invention comprise a metal silicon nitride composition in a layer that is superposed upon a layer to be patterned that would other wise cause destructive reflectivity during photoresist patterning. The antireflective structure has the ability to absorb light used during photoresist patterning. The antireflective structure also has the ability to scatter unabsorbed light into patterns and intensities that are ineffective to photoresist material exposed to the patterns and intensities. Preferred antireflective structures of the present invention comprise a semiconductor substrate having thereon at least one layer of a silicon-containing metal or silicon-containing metal nitride. The semiconductor substrate will preferably have thereon a feature size with width dimension less than about 0.5 microns, and more preferably less than about 0.25 microns.

Abstract: The invention relates to a method of manufacturing a semiconductor device, comprising the provision of a substrate (1) with a layer of silicon (3) thereon, an inorganic anti-reflective layer (4) applied to the layer of silicon (3), and a resist mask (6) applied to the inorganic anti-reflective layer (4), which method comprises the steps of:

Abstract: A method and system for providing at least one contact in a semiconductor device is described. The semiconductor device includes a substrate, an etch stop layer, an interlayer dielectric on the etch stop layer, an anti-reflective coating (ARC) layer on the interlayer dielectric, and at least one feature below the etch stop layer. A resist mask having an aperture and residing on the ARC layer is provided. The aperture is above an exposed portion of the ARC layer. The method and system include etching the exposed ARC layer and the underlying interlayer dielectric without etching through the etch stop layer, thereby providing a portion of at least one contact hole. The method and system also include removing the resist mask in situ, removing a portion of the etch stop layer exposed in the portion of the contact hole, and filling the contact hole with a conductive material.

Abstract: A method for forming a gate silicide portion comprising the following steps. A substrate having a gate oxide layer formed is provided. A gate layer is formed over the gate oxide layer. An RPO layer is formed over the gate layer. A patterned photoresist layer is formed over the RPO layer exposing a portion of the RPO layer. The portion of the RPO layer having a patterned photoresist residue thereover. The structure is subjected to a dry plasma or gas treatment to clean the exposed portion of the RPO layer and removing the patterned photoresist residue. The RPO layer is etched using the patterned photoresist layer as a mask to expose a portion of the gate layer. The dry plasma or gas treatment preventing formation of defects or voids in the RPO layer and the poly gate layer during etching of the RPO layer. A metal layer is formed over at least the exposed portion of the gate layer.

Abstract: The invention includes a semiconductor processing method in which a semiconductor substrate is exposed to reactive ion etching conditions. The reactive ion etching conditions comprise subjecting exposed surfaces of the substrate to a gas having components therein which are reactive with the exposed surfaces. A total concentration of the reactive components within the gas is less than 4.5%, by volume. In particular aspects, the total concentration of the reactive components can be less than 2% by volume, or less than 1% by volume. Exemplary reactive components are fluorine-containing components, such as NF3.

Abstract: An improved method for making a semiconductor device is described. That method includes forming a first dielectric layer on a substrate, then forming on the first dielectric layer a second dielectric layer. The second dielectric layer is made from a material that is more sensitive to radiation of a specified wavelength and energy than is the material from which the first dielectric layer is made. After the first dielectric layer and the second dielectric layer are exposed to radiation of a specified wavelength and energy, a portion of the first dielectric layer is removed to form a via, and a portion of the second dielectric layer is removed to form a trench. The via and trench are then filled with a conductive material.

Abstract: A gap-filling process is provided. A substrate having a dielectric layer thereon is provided. The dielectric layer has an opening therein. A gap-filling material layer is formed over the dielectric layer and inside the opening. A portion of the gap-filling material is removed from the gap-filling material layer to expose the dielectric layer. A gap-filling material treatment of the surface of the gap-filling material layer and the dielectric layer is carried out to planarize the gap-filling material layer so that a subsequently formed bottom anti-reflection coating or material layer over the gap-filling material layer can have a high degree of planarity.

Abstract: A layer of antireflective coating (ARC) material for use in photolithographic processing. In one embodiment the ARC material has the formula SiwOxHy:Cz, where w, x, y and z represent the atomic percentage of silicon, oxygen, hydrogen and carbon, respectively, in the material and where w is between 35 and 55, x is between 35 and 55, y is between 4 and 15, z is between 0 and 3 and the atomic percentage of nitrogen in the material is less than or equal to 1 atomic percent.

Abstract: In one aspect, the invention includes a semiconductor processing method comprising exposing silicon, nitrogen and oxygen in gaseous form to a high density plasma during deposition of a silicon, nitrogen and oxygen containing solid layer over a substrate. In another aspect, the invention includes a gate stack forming method, comprising: a) forming a polysilicon layer over a substrate; b) forming a metal silicide layer over the polysilicon layer; c) depositing an antireflective material layer over the metal silicide utilizing a high density plasma; d) forming a layer of photoresist over the antireflective material layer; e) photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist; and f) transferring a pattern from the patterned masking layer to the antireflective material layer, metal silicide layer and polysilicon layer to pattern the antireflective material layer, metal silicide layer and polysilicon layer into a gate stack.

Abstract: A method is presented for forming a transistor gate structure. A gate oxide layer is formed. Gate material is deposited on the gate oxide layer. A layer of silicon oxynitride is deposited on the gate material. The layer of silicon oxynitride, the gate material and the gate oxide layer are etched to form a gate structure. A silicon oxynitride region remains on top of the gate structure. A wet chemical process is performed to remove the silicon oxynitride region from the top of the gate structure. After performing the wet chemical process, spacers are formed around the gate structure.

Abstract: The present invention relates to an anti-reflective coating composition characterized by comprising a resin made from triazine compounds having at least two nitrogen atoms substituted a hydroxymethyl group and/or an alkoxymethyl group, and a light absorbing compound and/or a light absorbing resin. The present invention offers an anti-reflective coating composition for the anti-reflective coating having high light absorption property of the light used for the lithography process in the preparation of semiconductor device, showing high reflective light preventing effect, being used at thinner film thickness more than before, and having greater dry etching rate in comparison to photoresist layer.

Abstract: A method for manufacturing a semiconductor device includes providing a dielectric layer over a substrate, providing a first photoresist layer over the dielectric layer, patterning and defining the first photoresist layer, etching the first photoresist layer and the dielectric layer to form a plurality of vertical openings, removing the first photoresist layer, depositing a second photoresist layer over the dielectric layer, wherein the second photoresist layer fills the plurality of vertical openings, removing only a portion of the second photoresist layer deposited over the dielectric layer, wherein the second photoresist layer has a first substantially uniform thickness over the dielectric layer, depositing an anti-reflection coating layer over the second photoresist layer, providing a third photoresist layer over the anti-reflection coating layer, patterning and defining the third photoresist layer, and etching the anti-reflection coating layer and the second photoresist layer to form a plurality of trench

Abstract: An improved method of patterning photoresist during formation of damascene structures is provided which involves a process that is resistant to poisoning from adjacent layers. An inert resin is used to fill vias in a damascene stack. Then a second stack comprised of an underlayer, a non-photosensitive Si-containing layer, an ARC, and a photoresist are formed on the first stack. A trench pattern formed in the photoresist is etch transferred into the first stack. The Si-containing layer that is preferably a spin-on material can be optimized for thermal and etch resistance without compromising lithographic properties since it is not photosensitive. The state of the art photoresist provides a large process window for printing small features with no scum. The inert resin, underlayer, and silicon containing layers are independent of exposure wavelength and can be readily implemented into existing or future manufacturing schemes.

Abstract: A nitrogen-free anti-reflective layer for use in semiconductor photolithography is fabricated in a chemical vapor deposition process, optionally plasma-enhanced, using a gaseous mixture of carbon, silicon, and oxygen sources. By varying the process parameters, acceptable values of the refractive index n and extinction coefficient k can be obtained. The nitrogen-free anti-reflective layer produced by this technique eliminates the mushrooming and footing problems found with conventional anti-reflective layers.