Having Viaholes Of Diverse Width Patents (Class 438/638)
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Patent number: 8294034Abstract: A circuit board including a circuit substrate, a first dielectric layer, an antagonistic activation layer, a first conductive layer, a second conductive layer and a second dielectric layer is provided. The circuit substrate has a first surface and a first circuit layer. The first dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The first dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit layer and an intaglio pattern. The antagonistic activation layer is disposed on the second surface of the dielectric layer. The first conductive layer is disposed in the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via and covers the first conductive layer. The second conductive layer is electrically connected with the first circuit layer via the first conductive layer.Type: GrantFiled: May 28, 2010Date of Patent: October 23, 2012Assignee: Unimicron Technology Corp.Inventors: Tzyy-Jang Tseng, Shu-Sheng Chiang, Tsung-Yuan Chen
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Publication number: 20120261831Abstract: According to one embodiment, an integrated circuit device includes a plurality of interconnects and a contact via. The plurality of interconnects are arranged parallel to each other. The contact via is connected to the each of the interconnects. A protrusion is formed at a portion of each of the interconnects connected to the contact via to protrude in a direction of the arrangement. A recess is formed at a portion of the each of the interconnects separated from the portion having the protrusion to recede in the direction. The protrusion formed on one interconnect of two mutually-adjacent interconnects among the plurality of interconnects is opposed to the recess formed in one other interconnect of the two mutually-adjacent interconnects. The portion having the recess is separated from portions on two sides thereof and is separated also from the portion having the protrusion.Type: ApplicationFiled: September 20, 2011Publication date: October 18, 2012Inventor: Gaku SUDO
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Patent number: 8288272Abstract: A semiconductor device includes a plurality of first interconnection layers which are provided in an insulating layer and formed in a pattern having a width and space smaller than a resolution limit of an exposure technique, and a second interconnection layer which is provided between the first interconnection layers in the insulating layer and has a width larger than that of a first interconnection layer. A space between the second interconnection layer and each of first interconnection layers adjacent to both sides of the second interconnection layer equals the space between the first interconnection layers.Type: GrantFiled: July 20, 2011Date of Patent: October 16, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masato Endo, Tatsuya Kato
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Patent number: 8283249Abstract: A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.Type: GrantFiled: December 16, 2010Date of Patent: October 9, 2012Assignee: Spansion LLCInventor: Simon S. Chan
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Patent number: 8278685Abstract: A semiconductor device, which reduces the earth inductance, and a fabrication method for the same is provided.Type: GrantFiled: December 3, 2007Date of Patent: October 2, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Kazutaka Takagi
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Patent number: 8273657Abstract: A method for manufacturing a semiconductor apparatus having a through-hole interconnection in a semiconductor substrate. An insulating layer is formed on the semiconductor substrate. A via hole is formed through the semiconductor substrate and the insulating layer. Another insulating layer is formed in the via hole, and a conductive layer of the through-hole interconnection is subsequently formed. The insulating layer formed in the via hole is formed such as to substantially planarize an inner surface of the via hole.Type: GrantFiled: February 15, 2011Date of Patent: September 25, 2012Assignees: Sony Corporation, Fujikura Ltd.Inventors: Yoshimichi Harada, Masami Suzuki, Yoshihiro Nabe, Yuji Takaoka, Tatsuo Suemasu, Hideyuki Wada, Masanobu Saruta
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Integrated circuit arrangement including vias having two sections, and method for producing the same
Patent number: 8273658Abstract: An integrated circuit arrangement containing a via is disclosed. The via has an upper section having greatly inclined sidewalls. A lower section of the via has approximately vertical sidewalls. In one embodiment, a liner layer is used as a hard mask in the production of the via and defines the position of the sections of the via.Type: GrantFiled: August 25, 2005Date of Patent: September 25, 2012Assignee: Infineon Technologies AGInventors: Klaus Goller, Jakob Kriz -
Patent number: 8269342Abstract: A semiconductor package may include at least one semiconductor chip mounted on a substrate, a molding layer adapted to mold the at least one semiconductor chip, a heat slug, on the molding layer, having a structure in which a dielectric is provided between conductors, and a through mold via electrically connecting the heat slug to the substrate.Type: GrantFiled: June 1, 2010Date of Patent: September 18, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Yonghoon Kim, Heeseok Lee, Eunseok Cho, Hyuna Kim, Soyoung Lim, PaLan Lee
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Patent number: 8264086Abstract: A via structure having improved reliability and performance and methods of forming the same are provided. The via structure includes a first-layer conductive line, a second-layer conductive line, and a via electrically coupled between the first-layer conductive line and the second-layer conductive line. The via has a substantially tapered profile and substantially extends into a recess in the first-layer conductive line.Type: GrantFiled: December 5, 2005Date of Patent: September 11, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shau-Lin Shue, Cheng-Lin Huang, Ching-Hua Hsieh
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Patent number: 8258010Abstract: A plurality of semiconductor die is mounted to a carrier separated by a peripheral region. An insulating material is deposited in the peripheral region. A first opening is formed in the insulating material of the peripheral region to a first depth. A second opening is formed in the insulating material of the peripheral region centered over the first opening to a second depth less than the first depth. The first and second openings constitute a composite through organic via (TOV) having a first width in a vertical region of the first opening and a second width in a vertical region of the second opening. The second width is different than the first width. A conductive material is deposited in the composite TOV to form a conductive TOV. An organic solderability preservative (OSP) coating is formed over a contact surface of the conductive TOV.Type: GrantFiled: March 17, 2009Date of Patent: September 4, 2012Assignee: STATS ChipPAC, Ltd.Inventors: Reza A. Pagaila, Byung Tai Do, Shuangwu Huang
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Patent number: 8252683Abstract: Provided are a three-dimensional (3D) interconnection structure and a method of manufacturing the same. The 3D interconnection structure includes a wafer that has one side of an inverted V-shape whose middle portion is convex and a lower surface having a U-shaped groove for mounting a circuit, and a first electrode formed to cover a part of the inverted V-shaped one side of the wafer and a part of the U-shaped groove.Type: GrantFiled: September 9, 2010Date of Patent: August 28, 2012Assignee: Electronics and Telecommunications Research InstituteInventor: Kwon-Seob Lim
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Patent number: 8241992Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.Type: GrantFiled: May 10, 2010Date of Patent: August 14, 2012Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Maxime Darnon, Qinghuang Lin, Anthony D. Lisi, Satyanarayana V. Nitta
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Patent number: 8236681Abstract: In a formation process of a semi-global interconnect in a Cu damascene multilayer wiring structure, it is the common practice, upon formation of the damascene wiring structure, to remove an etch stop insulating film from a via bottom by dry etching and then carry out nitrogen plasma treatment to reduce carbon deposits on the surface of the via bottom. Study by the present inventors has revealed that when a sequence of successive discharging for the removal of electrostatic charge by using nitrogen plasma and transportation of the wafer is performed, a Cu hollow is generated on the via bottom at the end of the via chain coupled to a pad lead interconnect having a length not less than a threshold value.Type: GrantFiled: March 3, 2010Date of Patent: August 7, 2012Assignee: Renesas Electronics CorporationInventor: Makoto Nagano
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Patent number: 8232115Abstract: A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel.Type: GrantFiled: September 25, 2009Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Hanyi Ding, Kai D. Feng, Ping-Chuan Wang, Zhijian Yang
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Patent number: 8232199Abstract: A method of fabricating a semiconductor device and a fabrication system of the semiconductor device are provided. The method includes sequentially forming a film to be etched and a dielectric film and measuring a thickness of the dielectric film, forming a photoresist film on the dielectric film, performing a lithography process using the measured thickness of the dielectric film to form a photoresist film pattern, and etching the dielectric film and the film to be etched using the photoresist film pattern.Type: GrantFiled: July 1, 2010Date of Patent: July 31, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Won Song, Byung-Goo Jeon
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Patent number: 8227339Abstract: Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.Type: GrantFiled: November 2, 2009Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: Shom Ponoth, David V. Horak, Takeshi Nogami, Chih-Chao Yang
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Patent number: 8227336Abstract: A structure is provided with a self-aligned resist layer on a surface of metal interconnects for use in forming air gaps in an insulator material and method of fabricating the same. The non-lithographic method includes applying a resist on a structure comprising at least one metal interconnect formed in an insulator material. The method further includes blanket-exposing the resist to energy and developing the resist to expose surfaces of the insulator material while protecting the metal interconnects. The method further includes forming air gaps in the insulator material by an etching process, while the metal interconnects remain protected by the resist.Type: GrantFiled: January 20, 2009Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Elbert E. Huang, Robert D. Miller
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Patent number: 8226836Abstract: Described herein are systems, devices, and methods relating to packaging electronic devices, for example, microelectromechanical systems (MEMS) devices, including optical modulators such as interferometric optical modulators. The interferometric modulator disclosed herein comprises a movable mirror. Some embodiments of the disclosed movable mirror exhibit a combination of improved properties compared to known mirrors, including reduced moving mass, improved mechanical properties, and reduced etch times.Type: GrantFiled: August 12, 2008Date of Patent: July 24, 2012Assignee: Qualcomm MEMS Technologies, Inc.Inventors: Clarence Chui, Jeffrey B. Sampsell
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Patent number: 8222135Abstract: By forming an aluminum nitride layer by a self-limiting process sequence, the interface characteristics of a copper-based metallization layer may be significantly enhanced while nevertheless maintaining the overall permittivity of the layer stack at a lower level.Type: GrantFiled: September 30, 2010Date of Patent: July 17, 2012Assignee: Globalfoundries Inc.Inventors: Christof Streck, Volker Kahlert
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Patent number: 8222146Abstract: A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained.Type: GrantFiled: March 21, 2011Date of Patent: July 17, 2012Assignee: Renesas Electronics CorporationInventors: Kazuyoshi Maekawa, Kenichi Mori
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Patent number: 8211793Abstract: A structure and formation method for electrically connecting aluminum and copper interconnections stabilize a semiconductor metallization process using an inner shape electrically connecting the aluminum and copper interconnections. To this end, a copper interconnection is disposed on a semiconductor substrate. An interconnection induction layer and an interconnection insertion layer are sequentially formed on the copper interconnection to have a contact hole exposing the copper interconnection. An upper diameter of the contact hole may be formed to be larger than a lower diameter thereof. A barrier layer and an aluminum interconnection are filled in the contact hole. The aluminum interconnection is formed not to directly contact the copper interconnection through the contact hole.Type: GrantFiled: March 1, 2010Date of Patent: July 3, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Myeong Lee, Sang-Woo Lee, Gil-Heyun Choi, Jong-Won Hong, Kyung-In Choi, Hyun-Bae Lee
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Patent number: 8207060Abstract: The present invention provides a method of forming a contact opening, such as a via hole, in which a sacrificial layer is deposited prior to exposing a conductor formed in a substrate at a bottom side of the opening to prevent damage and contamination to the materials constituting an integrated circuit device from happening. The exposing may or may not form a recess in the conductor. The present invention also provides a method of forming a contact opening having a recess in the conductor wherein a sacrificial layer is not deposited until the conductor is exposed, but deposited before a recess is formed in the conductor so that a major damage and contamination related to the recess formation can be prevented. By forming a trench feature over a contact opening formed by using the present invention, a dual damascene feature can be fabricated.Type: GrantFiled: December 18, 2008Date of Patent: June 26, 2012Inventor: Byung Chun Yang
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Patent number: 8202804Abstract: A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer layer over the dielectric layer. The polymer layer is applied uniformly and fills the apertures at different rates depending on the geometry of the apertures, or on the presence or absence of growth accelerating material. The polymer creates spacers for the etching of additional structure in between the spacers. The method is capable of achieving structures smaller than current lithography techniques.Type: GrantFiled: September 13, 2010Date of Patent: June 19, 2012Assignee: Micron Technology, Inc.Inventor: Gurtej Sandhu
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Patent number: 8198157Abstract: A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Related methods are also discussed.Type: GrantFiled: September 20, 2011Date of Patent: June 12, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Sun Sel, Jung-Dal Choi, Young-Woo Park, Jin-Taek Park
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Patent number: 8193642Abstract: This invention provides an interlayer insulating film for a semiconductor device, which has low permittivity, is free from the evolution of gas such as CFx and SiF4 and is stable, and a wiring structure comprising the same. In an interlayer insulating film comprising an insulating film provided on a substrate layer, the interlayer insulating film has an effective permittivity of not more than 3. The wiring structure comprises an interlayer insulating film, a contact hole provided in the interlayer insulating film, and a metal filled into the contact hole. The insulating film comprises a first fluorocarbon film provided on the substrate layer and a second fluorocarbon film provided on the first fluorocarbon film.Type: GrantFiled: June 20, 2006Date of Patent: June 5, 2012Assignees: Tohoku University, Foundation for Advancement of International ScienceInventor: Tadahiro Ohmi
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Patent number: 8183151Abstract: Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a temporary carrier may be secured to the layer of conductive material on a side thereof opposite the substrate prior to forming the vias. Structures, including workpieces formed using such methods, are also disclosed.Type: GrantFiled: May 4, 2007Date of Patent: May 22, 2012Assignee: Micron Technology, Inc.Inventor: Rickie C. Lake
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Patent number: 8173539Abstract: A method for fabricating a metal redistribution layer is described. A first opening and a second opening are formed in a dielectric layer over a first region and a second region thereof, respectively. A plurality of third openings are formed in the dielectric layer exposed by the first opening in the first region and a plurality of fourth openings are formed in the dielectric layer exposed by the second opening in the second region. A metal material is formed over the dielectric layer and in the first, second, third and fourth openings. A plurality of recesses is formed in the metal materials overlying the third and fourth openings. The metal material in the first region is patterned by using the recesses formed in portions of the metal material overlying the fourth openings in the second region as an alignment mark to form a metal redistribution layer.Type: GrantFiled: April 12, 2011Date of Patent: May 8, 2012Assignee: Nanya Technology CorporationInventors: Pei-Lin Huang, Chun-Yen Huang, Yuan-Yuan Lin, Yu Shan Chiu, Yi-Min Tseng
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Patent number: 8173541Abstract: A chip carrier substrate includes a capacitor aperture and a laterally separated via aperture, each located within a substrate. The capacitor aperture is formed with a narrower linewidth and shallower depth than the via aperture incident to a microloading effect within a plasma etch method that is used for simultaneously etching the capacitor aperture and the via aperture within the substrate. Subsequently a capacitor is formed and located within the capacitor aperture and a via is formed and located within the via apertures. Various combinations of a first capacitor plate layer, a capacitor dielectric layer and a second capacitor plate layer may be contiguous with respect to the capacitor aperture and the via aperture.Type: GrantFiled: August 17, 2009Date of Patent: May 8, 2012Assignee: International Business Machines CorporationInventors: Paul S. Andry, Chirag S. Patel
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Patent number: 8161637Abstract: A manufacturing method for a printed wiring board includes forming an electroless plated film on an interlayer resin insulation layer, forming on the electroless plated film a plating resist with an opening to expose a portion of the electroless plated film, forming an electrolytic plated film on the portion of the electroless plated film exposed through the opening, removing the plating resist using a resist-removing solution containing an amine, reducing a thickness of a portion of the electroless plated film existing between adjacent portions of the electrolytic plated film by using the resist-removing solution, and forming a conductive pattern by removing the portion of the electroless plated film existing between the adjacent portions of the electrolytic plated film by using an etchant.Type: GrantFiled: April 30, 2010Date of Patent: April 24, 2012Assignee: Ibiden Co., Ltd.Inventors: Hideo Mizutani, Toshiyuki Matsui, Atsushi Deguchi
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Patent number: 8158520Abstract: An integrated circuit device structure with a novel contact feature. The structure includes a substrate, a dielectric layer overlying the substrate, and a metal interconnect overlying the dielectric layer. A first interlayer dielectric layer is formed surrounding the metal interconnect. A second interlayer dielectric layer of a predetermined thickness is overlying the first interlayer dielectric layer. A trench opening of a first width is formed within an upper portion of the second interlayer dielectric layer. A first barrier layer is within and is overlying the trench opening of the first width. A contact opening of a second width is within a lower portion of the second interlayer dielectric layer. The second width is less than the first width. The lower portion of the second interlayer dielectric layer is coupled to the upper portion of the second interlayer dielectric layer within the predetermined thickness of the second interlayer dielectric.Type: GrantFiled: October 20, 2004Date of Patent: April 17, 2012Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventor: Xian J. Ning
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Patent number: 8158516Abstract: According to one embodiment, a method is described for manufacturing a semiconductor device. The method can form a conductive layer including tungsten on a foundation layer. The method can form a trench by selectively etching the conductive layer. The trench is shallower than a depth from a surface of the conductive layer to the foundation layer. The method can form a protective film on a side surface and a bottom surface of the conductive layer in the trench using a gas containing bromine. The protective film includes a compound of the tungsten and the bromine. The method can remove the protective film on the bottom surface of the conductive layer. The method can etch a portion of the conductive layer below the trench with the protective film on the side surface of the conductive layer.Type: GrantFiled: January 31, 2011Date of Patent: April 17, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Takuji Kuniya
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Patent number: 8153518Abstract: In a method for fabricating a metal interconnection of a semiconductor device, a lower interconnection and a lower insulation layer are formed over a semiconductor substrate. An etch stop layer is formed over the lower insulation layer. An upper insulation layer is formed over the etch stop layer. A first via hole is formed to expose the etch stop layer corresponding to the lower interconnection. A second via hole exposing the lower interconnection is formed by a primary etching process that selectively removes the etch stop layer exposed by the first via hole. A chemical cleaning process is performed on the second via hole, wherein polymer is formed over the surface of the lower interconnection during the chemical cleaning process. The polymer is removed from the second via hole by a secondary etching process using vaporized gas.Type: GrantFiled: December 15, 2009Date of Patent: April 10, 2012Assignee: Dongbu HiTek Co., Ltd.Inventor: Chung-Kyung Jung
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Patent number: 8153503Abstract: The invention relates to a method for protecting the interior of at least one cavity (4) having a portion of interest (5) and opening onto a face of a microstructured element (1), consisting of depositing, on said face, a nonconformal layer (6) of a protective material, in which said nonconformal layer closes off the cavity without covering the portion of interest. The invention also relates to a method for producing a device comprising such a microstructured element.Type: GrantFiled: April 3, 2007Date of Patent: April 10, 2012Assignee: Commissariat a l'Energie AtomiqueInventors: Barbara Charlet, Hélène Le Poche, Yveline Gobil
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Patent number: 8148259Abstract: The present invention offers a method for forming an opening portion by a simple process without using a photomask or a resist. Further, the present invention proposes a method for manufacturing a semiconductor device at low cost. A plurality of light absorbing layers is formed over a substrate, an interlayer insulating layer is formed over the plurality of light absorbing layers, the plurality of light absorbing layers is irradiated with a linear or rectangular laser beam from the interlayer insulating layer side, and at least the interlayer insulating layer which is over the plurality of light absorbing layers is removed and an opening portion is formed; and accordingly, a plurality of opening portions can be formed by removing the plurality of light absorbing layers and an insulating film formed over the plurality of light absorbing layers.Type: GrantFiled: August 23, 2007Date of Patent: April 3, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yasuyuki Arai, Koichiro Tanaka, Yukie Suzuki
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Patent number: 8143153Abstract: A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO2 film and including the multilayer interconnection structure; forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate; forming a film including Si and C as principal components and covering sidewall surfaces and a bottom surface of the groove; and forming a protection film on the film along the sidewall surfaces and the bottom surface of the groove.Type: GrantFiled: March 30, 2011Date of Patent: March 27, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Kenichi Watanabe, Nobuhiro Misawa, Satoshi Otsuka
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Patent number: 8124519Abstract: A system and method is disclosed for bonding a substrate to a semiconductor die that is prone to curling when subjected to an elevated temperature in a solder reflow oven, for example, thereby improving the electrical and mechanical bonding for large dies, wafers, chips, and photovoltaic cells. In one embodiment, the substrate is adapted to curl to the same degree as the die to form a uniform gap between the substrate and die across the boundary there between. In another embodiment, solder used to bond the die and substrate is applied such that the volume deposited varies based on the expected gap between the die and substrate when heated to the melting temperature of the solder.Type: GrantFiled: October 3, 2008Date of Patent: February 28, 2012Assignee: Energy Innovations, Inc.Inventor: Gregory Alan Bone
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Patent number: 8114734Abstract: A method of making a metal capacitor includes the following steps. A dielectric layer having a metal interconnection and a capacitor electrode is provided. Then, a treatment is performed to increase the dielectric constant of the dielectric layer surrounding the capacitor electrode. The treatment can be UV radiation, a plasma treatment or an ion implantation. Accordingly, the metal capacitor will have a higher capacitance and RC delay between the metal interconnection and the dielectric layer can be prevented.Type: GrantFiled: October 21, 2008Date of Patent: February 14, 2012Assignee: United Microelectronics Corp.Inventor: Chin-Sheng Yang
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Patent number: 8110497Abstract: An embodiment of the present invention provides a method for manufacturing a semiconductor device. This method comprises: forming a seed film at least on an inner face of a recessed portion of a substrate; forming a protection film on the seed film, the protection film being made of a material that is more easily oxidized than a material forming the seed film; heat-treating the protection film; exposing at least part of the seed film by removing at least part of the heat-treated protection film; forming a plating film on the seed film through electrolytic plating to be buried in the recessed portion, by supplying current to the seed film that is at least partially exposed; and removing the plating film except for a portion buried in the recessed portion.Type: GrantFiled: December 23, 2009Date of Patent: February 7, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Atsuko Sakata, Soichi Yamashita, Yasuyuki Sonoda, Hiroshi Toyoda, Masahiko Hasunuma
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Publication number: 20120025395Abstract: A semiconductor device includes: a first porous layer that is formed over a substrate and includes a SiO2 skeleton; a second porous layer that is formed immediately above the first porous layer and includes a SiO2 skeleton; a via wiring that is provided in the first porous layer; and a trench wiring that is buried in the second porous layer. The first porous layer has a pore density x1 of 40% or below and the second porous layer has a pore density x2 of (x1+5) % or above.Type: ApplicationFiled: July 28, 2011Publication date: February 2, 2012Applicants: ULVAC, INC., RENESAS ELECTRONICS CORPORATIONInventors: Shinichi CHIKAKI, Takahiro NAKAYAMA
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Patent number: 8105941Abstract: A through-wafer interconnect and a method for fabricating the same are disclosed. The method starts with a conductive wafer to form a patterned trench by removing material of the conductive wafer. The patterned trench extends in depth from the front side to the backside of the wafer, and has an annular opening generally dividing the conductive wafer into an inner portion and an outer portion whereby the inner portion of the conductive wafer is insulated from the outer portion and serves as a through-wafer conductor. A dielectric material is formed or added into the patterned trench mechanical to support and electrically insulate the through-wafer conductor. Multiple conductors can be formed in an array.Type: GrantFiled: May 18, 2006Date of Patent: January 31, 2012Assignee: Kolo Technologies, Inc.Inventor: Yongli Huang
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Patent number: 8101092Abstract: A method for controlling ADI-AEI CD difference ratios of openings having different sizes is provided. First, a first etching step using a patterned photoresist layer as a mask is performed to form a patterned Si-containing material layer and a polymer layer on sidewalls thereof. Next, a second etching step is performed with the patterned photoresist layer, the patterned Si-containing material layer and the polymer layer as masks to at least remove an exposed portion of a etching resistive layer to form a patterned etching resistive layer. A portion of a target material layer is removed by using the patterned etching resistive layer as an etching mask to form a first and a second openings in the target material layer. The method is characterized by controlling etching parameters of the first and second etching steps to obtain predetermined ADI-AEI CD difference ratios.Type: GrantFiled: October 24, 2007Date of Patent: January 24, 2012Assignee: United Microelectronics Corp.Inventors: Chih-Wen Feng, Pei-Yu Chou, Chun-Ting Yeh, Jyh-Cherng Yau, Jiunn-Hsiung Liao, Feng-Yi Chang, Ying-Chih Lin
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Patent number: 8101433Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: GrantFiled: March 30, 2009Date of Patent: January 24, 2012Assignee: Renesas Electronics CorporationInventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Patent number: 8097948Abstract: To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen.Type: GrantFiled: September 13, 2010Date of Patent: January 17, 2012Assignee: Renesas Electronics CorporationInventors: Takeshi Furusawa, Daisuke Kodama, Masahiro Matsumoto, Hiroshi Miyazaki
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Patent number: 8093150Abstract: Methods of manufacturing semiconductor devices are disclosed. A preferred embodiment comprises a method of manufacturing a semiconductor device, the method including providing a workpiece, disposing an etch stop layer over the workpiece, and disposing a material layer over the etch stop layer. The material layer includes a transition layer. The method includes patterning the material layer partially with a first pattern, and patterning the material layer partially with a second pattern. Patterning the material layer partially with the second pattern further comprises simultaneously completely patterning the material layer with the first pattern.Type: GrantFiled: September 19, 2006Date of Patent: January 10, 2012Assignee: Infineon Technologies AGInventors: Michael Beck, Erdem Kaltalioglu
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Patent number: 8084357Abstract: A method for manufacturing a multi cap layer includes providing a substrate, forming a multi cap layer comprising a first cap layer and a second cap layer formed thereon on the substrate, forming a patterned metal hard mask layer on the multi cap layer, and performing an etching process to etch the multi cap layer through the patterned hard mask layer and to form an opening in the second cap layer.Type: GrantFiled: April 11, 2007Date of Patent: December 27, 2011Assignee: United Microelectronics Corp.Inventors: Wei-Chih Chen, Su-Jen Sung, Feng-Yu Hsu, Chun-Chieh Huang, Mei-Ling Chen, Jiann-Jen Chiou
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Patent number: 8084358Abstract: In a manufacturing method of a semiconductor device, an insulating film is formed on a first conductive film. By using a mask film having an opening that exposes the insulating film, anisotropic etching is performed to form a recess is formed in an upper part of the insulating film exposed to the opening and to cause a reaction product to adhere to a lower part of a sidewall portion of the mask film. Isotropic etching is then performed to decrease the sidewall portion of the mask film in a horizontal direction, and anisotropic etching is performed to etch the insulating film exposed at a bottom of the recess in a vertical direction while removing the reaction product adhering to the lower part of the sidewall portion of the mask film. Anisotropic etching is then performed to etch the insulating film present around the recess in the vertical direction to form a stepped portion, and also to etch the insulating film exposed at the bottom of the recess to expose the first conductive film.Type: GrantFiled: February 4, 2009Date of Patent: December 27, 2011Assignee: Panasonic CorporationInventor: Hiroshi Yoshida
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Patent number: 8080473Abstract: A method of patterning a film stack is described. The method comprises preparing a film stack on a substrate, wherein the film stack comprises a SiCOH-containing layer formed on the substrate, a silicon oxide (SiOx) layer formed on the SiCOH-containing layer, and a mask layer formed on the silicon oxide layer. A pattern is created in the mask layer. Thereafter, the pattern in the mask layer is transferred to the silicon oxide layer using a first etching process, and then the mask layer is removed. The pattern in the silicon oxide layer is transferred to the SiCOH-containing layer using a second etching process formed from a process composition comprising NF3. Thereafter, the silicon oxide layer is removed using a third etching process.Type: GrantFiled: August 29, 2007Date of Patent: December 20, 2011Assignee: Tokyo Electron LimitedInventor: Yannick Feurprier
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Patent number: 8071474Abstract: (a1) A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. (a2) A first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. (a3) Conductive material essentially consisting of Cu is deposited on the first film to embed the conductive material in the concave portion. (a4) The semiconductor substrate is annealed. During the period until a barrier layer is formed having also a function of improving tight adhesion, it is possible to ensure sufficient tight adhesion of wiring members and prevent peel-off of the wiring members.Type: GrantFiled: August 10, 2010Date of Patent: December 6, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Noriyoshi Shimizu, Nobuyuki Ohtsuka, Hideki Kitada, Yoshiyuki Nakao
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Patent number: 8062976Abstract: A method is for forming a vertical interconnection through a dielectric layer between upper and lower electrically conductive layers of an integrated circuit. The method includes forming an opening through the dielectric layer and placing a solidifiable electrically conductive filler into the opening via a printing technique. The solidifiable electrically conductive filler is solidified to thereby form a solidified electrically conducting filler in the opening. A metallization layer is formed over the dielectric layer and the solidified electrically conducting filler to thereby form the vertical interconnection through the dielectric layer between the upper and lower electrically conductive layers of the integrated circuit.Type: GrantFiled: July 27, 2010Date of Patent: November 22, 2011Assignee: STMicroelectronics S.R.L.Inventors: Raffaele Vecchione, Luigi Giuseppe Occhipinti, Nunzia Malagnino, Rossana Scaldaferri, Maria Viviana Volpe
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Patent number: 8062972Abstract: A semiconductor manufacturing process is provided. First, a substrate is provided, wherein a patterned conductive layer, a dielectric layer and a patterned metal hard mask layer are sequentially formed thereon. Thereafter, a portion of the dielectric layer is removed to form a damascene opening exposing the patterned conductive layer. Afterwards, the dielectric layer is heated to above 200° C. Thereafter, a plasma treatment process is performed on the damascene opening, wherein the gases used to generate the plasma include hydrogen gas and inert gas. Afterwards, a conductive layer is formed in the damascene opening to fill therein.Type: GrantFiled: August 26, 2009Date of Patent: November 22, 2011Assignee: United Microelectronics Corp.Inventors: An-Chi Liu, Chih-Chien Huang, Tien-Cheng Lan