Having Viahole With Sidewall Component Patents (Class 438/639)
  • Patent number: 10319630
    Abstract: A plurality of metal tracks are formed in a plurality of intermetal dielectric layers stacked in an integrated circuit die. Thin protective dielectric layers are formed around the metal tracks. The protective dielectric layers act as a hard mask to define contact vias between metal tracks in the intermetal dielectric layers.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: June 11, 2019
    Assignees: STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu
  • Patent number: 10283523
    Abstract: A semiconductor memory device according to an embodiment comprises: conductive layers stacked in a vertical direction on a semiconductor substrate; and first and columnar bodies that extend in the vertical direction, the first and second columnar bodies each comprising: a first film; a second film disposed on the first film; and a semiconductor film, and the first film of the second columnar body having an upper end positioned higher than a first position lower than a first conductive layer and lower than a second position higher than the first conductive layer and a lower end positioned at or lower than the first position, and the second film of the second columnar body having an upper end positioned higher than the second position and a lower end positioned lower than the first position.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: May 7, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Kotaro Noda
  • Patent number: 10186452
    Abstract: An asymmetric stair structure includes multiple unit layers and has m regions (m?2). In each of the m regions, a different part of unit layers having an interval of m unit layers each have a portion not covered by an upper adjacent unit layer, so that a stair having a step difference of m unit layers is formed. In arbitrary two of the m regions, the two different parts of unit layers include no repeated unit layers.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: January 22, 2019
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Yao-Yuan Chang
  • Patent number: 9806172
    Abstract: A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the protrusion structure and extends to a bottom portion of the protrusion structure as a raised drain region. A drain contact is disposed over the drain region and overlap with the isolation feature.
    Type: Grant
    Filed: October 3, 2015
    Date of Patent: October 31, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay Chuang, Cheng-Cheng Kuo, Ming Zhu
  • Patent number: 9704878
    Abstract: A vertical NAND-type memory device includes a vertical stack of inter-gate insulating layers and gate electrodes arranged in an alternating sequence on an underlying substrate, which includes a cell array region and a contact region therein. At least one NAND-type channel structure is provided, which extends vertically through the vertical stack of inter-gate insulating layers and gate electrodes. An end sidewall of a first of the gate electrodes, which extends laterally over at least a portion of the contact region, has a vertical slope that is less steep than vertical slopes of end sidewalls of a first plurality of the gate electrodes extending between the first of the gate electrodes and the substrate.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: July 11, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woong-Seop Lee, Seokcheon Baek, Jinhyun Shin
  • Patent number: 9601577
    Abstract: A vertically integrated circuit device can include a substrate having a first region reserved for first functional circuits of the vertically integrated circuit device, where the first functional circuits has a substantially constant top surface level across the first region and having a second region reserved for second functional circuits of the vertically integrated circuit device and spaced apart from the first region. The second functional circuits can have a varied top surface level across the second region. A doped oxidation suppressing material can be included in the substrate and can extend from the first region to the second region at an interface of the substrate with the first functional circuits and the second functional circuits, respectively.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: March 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Sik Lee, Youngwoo Kim, Jinhyun Shin, Jung Hoon Lee
  • Patent number: 9508664
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a conductive structure over the substrate. The semiconductor device structure includes first metal oxide fibers over the conductive structure. The semiconductor device structure includes a dielectric layer over the substrate and covering the conductive structure and the first metal oxide fibers. The dielectric layer fills gaps between the first metal oxide fibers.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: November 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Szu-Wei Lu, Yen-Yao Chi
  • Patent number: 9502429
    Abstract: A trench can be formed through a stack of alternating plurality of first material layers and second material layers. A dielectric material liner and a trench fill material portion can be formed in the trench. The dielectric material liner and portions of first material layer can be simultaneously etched to form laterally-extending cavities having level-dependent lateral extents. A set of stepped surfaces can be formed by removing unmasked portions of the second material layers. Alternately, an alternating sequence of processing steps including vertical etch processes and lateral recess processes can be employed to laterally recess second material layers and to form laterally-extending cavities having level-dependent lateral extents. Lateral cavities can be simultaneously formed in multiple levels such that levels having laterally-extending cavities of a same lateral extent are offset across multiple integrated cavities.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: November 22, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Nobuo Hironaga
  • Patent number: 9412866
    Abstract: The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) selectivity stress films that apply a stress that improves the performance of semiconductor devices underlying the BEOL selectivity stress films, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices having a first device type. A stress transfer element is located within a back-end-of-the-line stack at a position over the one or more semiconductor devices. A selectivity stress film is located over the stress transfer element. The selectivity stress film induces a stress upon the stress transfer element, wherein the stress has a compressive or tensile state depending on the first device type of the one or more semiconductor devices. The stress acts upon the one or more semiconductor devices to improve their performance.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gwo-Chyuan Kuoh, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien, Yen-Ming Peng
  • Patent number: 9368645
    Abstract: This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode over a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate, a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, and etch stop layers including metal silicide and formed over the pipe connection gate electrode.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: June 14, 2016
    Assignee: SK Hynix Inc.
    Inventors: Min-Soo Kim, Young-Jin Lee, Jin-Hae Choi, Joo-Hee Han, Sung-Jin Whang, Byung-Ho Lee
  • Patent number: 9362304
    Abstract: This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a bottom buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled to the pipe channel layer and extended in a direction substantially perpendicular to the substrate, and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, wherein the pipe connection gate electrode includes a metal silicide layer formed within the groove. The electric resistance of the pipe connection gate electrode may be greatly reduced without an increase in a substantial height by forming the metal silicide layer buried in the substrate under the pipe connection gate electrode.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: June 7, 2016
    Assignee: SK Hynix Inc.
    Inventors: Min-Soo Kim, Young-Jin Lee, Jin-Hae Choi, Joo-Hee Han, Sung-Jin Whang, Byung-Ho Lee
  • Patent number: 9305886
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes fabricating a crack-stop structure that extends through a plurality of metallization layers above a semiconductor substrate. The plurality of metallization layers includes a first metallization layer and a second metallization layer that overlies the first metallization layer. Fabricating the crack-stop structure includes forming a first via-bar overlying and coupled to a first metal line of the first metallization layer that is disposed in a first ILD layer of dielectric material. The first via-bar is disposed in a second ILD layer of dielectric material and has a first width. A second metal line of the second metallization layer that is in the second ILD layer is formed overlying and coupled to the first via-bar. The second metal line has a second width that is from about 1 to about 5 times the first width.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: April 5, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wei Shao, Fan Zhang, Juan Boon Tan
  • Patent number: 9293431
    Abstract: The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via (“TSV”) extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Sung Chang, Chun-wen Cheng, Alexander Kalnitsky, Chia-Hua Chu
  • Patent number: 9202847
    Abstract: A solid-state image pickup device is provided which includes a plurality of pixels provided in a semiconductor substrate, the pixels including a plurality of photoelectric conversion portions and MOS transistors which selectively read out signals therefrom, at least one organic photoelectric conversion film on the photoelectric conversion portions, and an isolation region provided in the organic photoelectric conversion film at a position corresponding to between the pixels to perform optical and electrical isolation.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: December 1, 2015
    Assignee: Sony Corporation
    Inventor: Ritsuo Takizawa
  • Patent number: 9166086
    Abstract: The solar cell module having a preferable edge space that prevents characteristics of a solar cell such as conversion efficiency from being deteriorated without making processes complicated is provided. In a method for manufacturing a solar cell module including a substrate glass, a first layer formed on the substrate glass and a second layer formed on the first layer, the method includes a step of forming a first edge space having a first width by removing the first layer and the second layer by the first width from an end part of the glass substrate and a step of forming a second edge space by removing only the second layer by a second width from the end part of the glass substrate, and the width of the second edge space is larger than the width of the first edge space.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: October 20, 2015
    Assignee: SOLAR FRONTIER K.K.
    Inventors: Hirofumi Nishi, Hirohisa Suzuki
  • Patent number: 9142508
    Abstract: Methods of fabricating a multi-layer semiconductor device such as a multi-layer damascene or inverted multi-layer damascene structure using only a single or reduced number of exposure steps. The method may include etching a precursor structure formed of materials with differential removal rates for a given removal condition. The method may include removing material from a multi-layer structure under different removal conditions. Further disclosed are multi-layer damascene structures having multiple cavities of different sizes. The cavities may have smooth inner wall surfaces. The layers of the structure may be in direct contact. The cavities may be filled with a conducting metal or an insulator. Multi-layer semiconductor devices using the methods and structures are further disclosed.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: September 22, 2015
    Assignee: Tessera, Inc.
    Inventors: Cyprian Uzoh, Vage Oganesian, Ilyas Mohammed, Craig Mitchell, Belgacem Haba
  • Patent number: 9123706
    Abstract: Techniques are disclosed that enable interconnects, vias, metal gates, and other conductive features that can be formed through electroless material deposition techniques. In some embodiments, the techniques employ electroless fill in conjunction with high growth rate selectivity between an electroless nucleation material (ENM) and electroless suppression material (ESM) to generate bottom-up or otherwise desired fill pattern of such features. Suitable ENM may be present in the underlying or otherwise existing structure, or may be provided. The ESM is provisioned so as to prevent or otherwise inhibit nucleation at the ESM covered areas of the feature, which in turn prevents or otherwise slows down the rate of electroless growth on those areas. As such, the electroless growth rate on the ENM sites is higher than the electroless growth rate on the ESM sites.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: September 1, 2015
    Assignee: INTEL CORPORATION
    Inventors: Daniel J. Zierath, Shaestagir Chowdhury, Chi-Hwa Tsang
  • Patent number: 9111932
    Abstract: Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: August 18, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Nishant Sinha, John A. Smythe
  • Patent number: 9048125
    Abstract: A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: June 2, 2015
    Assignee: Amkor Technology, Inc.
    Inventors: Jong Sik Paek, Won Chul Do, Doo Hyun Park, Eun Ho Park, Sung Jae Oh
  • Patent number: 9048193
    Abstract: A method of forming a multi-floor step pattern structure includes forming a stacked structure having alternating insulating interlayers and sacrificial layers on a substrate. A first photoresist pattern is formed on the stacked structure. A first preliminary step pattern structure is formed by etching portions of the stacked structure using the first photoresist pattern as an etching mask. A passivation layer pattern is formed on upper surfaces of the first photoresist pattern and the first preliminary step pattern structure. A second photoresist pattern is formed by removing a side wall portion of the first photoresist pattern exposed by the passivation layer pattern. A second preliminary step pattern structure is formed by etching exposed insulating interlayers and underlying sacrificial layers using the second photoresist pattern as an etching mask. The above steps may be repeated on the second preliminary step pattern structure to form the multi-floor step pattern structure.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: June 2, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Ik Oh, Dae-Hyun Jang, Seong-Soo Lee, Han-Na Cho
  • Patent number: 9041216
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Su-Jen Sung, Yi-Nien Su
  • Patent number: 9040415
    Abstract: A method for forming a trench includes etching an oxide layer to form a trench therein, conformally forming a first reaction layer along a surface of the trench, the first reaction layer including a first region on an upper portion of the trench and a second region on a lower portion of the trench, forming a barrier layer by reacting a first amount of etching gas with the first region of the first reaction layer, and etching the oxide layer on a lower portion of the second region by reacting a second amount of etching gas with the second region of the first reaction layer, the second amount of etching gas being greater than the first amount of etching gas.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: May 26, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Bo-Un Yoon, Young-Sang Youn, Jeong-Nam Han, Kee-Sang Kwon, Doo-Sung Yun, Byung-Kwon Cho, Ji-Hoon Cha
  • Patent number: 9034755
    Abstract: Embodiments of the present invention provide a method of forming contact structure for transistor. The method includes providing a semiconductor substrate having a first and a second gate structure of a first and a second transistor formed on top thereof, the first and second gate structures being embedded in a first inter-layer-dielectric (ILD) layer; epitaxially forming a first semiconductor region between the first and second gate structures inside the first ILD layer; epitaxially forming a second semiconductor region on top of the first semiconductor region, the second semiconductor region being inside a second ILD layer on top of the first ILD layer and having a width wider than a width of the first semiconductor region; and forming a silicide in a top portion of the second semiconductor region.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Reinaldo A. Vega
  • Patent number: 9024449
    Abstract: A thin film transistor element includes: a gate electrode; a source electrode and a drain electrode; an insulating layer; partition walls; and an organic semiconductor layer. The partition walls define a first aperture. Within the first aperture, at least a part of the source electrode and at least a part of the drain electrode are in contact with the semiconductor layer. The partition walls have side face portions facing the first aperture, and some of the side face portions have gentler slopes than the rest of the side face portions.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: May 5, 2015
    Assignee: Panasonic Corporation
    Inventors: Yuko Okumoto, Akihito Miyamoto, Takaaki Ukeda
  • Patent number: 9018092
    Abstract: A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks in the metal layers above and below the intermediate metal layer.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: April 28, 2015
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu
  • Patent number: 9006102
    Abstract: Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method of forming a conductive via element disclosed herein includes forming a via opening in a substrate, the via opening extending through an interlayer dielectric layer formed above the substrate and a device layer formed below the interlayer dielectric layer, and extending into the substrate. The method also includes forming a first portion of the conductive via element comprising a first conductive contact material in a bottom portion of the via opening, and forming a second portion of the conductive via element comprising a second conductive contact material different from the first conductive contact material in an upper portion of the via opening and above the first portion.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: April 14, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte Ltd
    Inventors: Yu Hong, Liu Huang, Zhao Feng
  • Patent number: 8999837
    Abstract: A method of fabricating a semiconductor device may include forming isolation structures that include openings, over a substrate; forming sacrificial spacers on sidewalls of the openings; forming, on the sacrificial spacers, first conductive patterns that are recessed in the openings; removing the sacrificial spacers, and defining air gaps; forming a liner layer that caps the first conductive patterns and the air gaps; forming second conductive patterns through silicidation of the liner layer; and forming third conductive patterns over the second conductive patterns.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: April 7, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jong-Kook Park, Han-Sang Song, Jin-Yul Lee, Chang-Ki Lee
  • Patent number: 8994186
    Abstract: A thin film transistor element includes: a gate electrode; a source electrode and a drain electrode; an insulating layer; partition walls; and an organic semiconductor layer. The partition walls define a first aperture. Within the first aperture, at least a part of the source electrode and at least a part of the drain electrode are in contact with the semiconductor layer. In plan view of the bottom of the first aperture, the center of the total of the areas of the source electrode and the drain electrode is offset from the center of the area of the bottom in a given direction.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: March 31, 2015
    Assignee: Panasonic Corporation
    Inventors: Yuko Okumoto, Akihito Miyamoto, Takaaki Ukeda
  • Patent number: 8993436
    Abstract: A method for fabricating a semiconductor device includes sequentially forming an etch stop film and an insulating film on a substrate including a lower pattern forming a conductive mask pattern including a first opening on the insulating film, forming a via-hole in the insulating film using the conductive mask pattern as an etch mask, the via-hole exposing the etch stop film, removing the conductive mask pattern, and forming a passivation film along a side wall of the via-hole after removing the conductive mask pattern.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Whan Ko, Jong-Sam Kim, Hong-Jae Shin, Seung-Il Bok, Sae-Il Son, Woo-Jin Jang
  • Patent number: 8980740
    Abstract: A process of modulating the thickness of a barrier layer deposited on the sidewalls and floor of a recessed feature in a semiconductor substrate is disclosed. The process includes altering the surface of the conductive feature on which the barrier layer is deposited by annealing in a reducing atmosphere and optionally additionally, silylating the dielectric surface that forms the sidewalls of the recessed feature.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: March 17, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Errol Todd Ryan, Xunyuan Zhang
  • Patent number: 8981466
    Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alfred Grill, Seth L. Knupp, Son V. Nguyen, Vamsi K. Paruchuri, Deepika Priyadarshini, Hosadurga K. Shobha
  • Patent number: 8975749
    Abstract: A method of making a semiconductor device includes forming a dielectric layer over a semiconductor substrate. The method further includes forming a copper-containing layer in the dielectric layer, wherein the copper-containing layer has a first portion and a second portion. The method further includes forming a first barrier layer between the first portion of the copper-containing layer and the dielectric layer. The method further includes forming a second barrier layer at a boundary between the second portion of the copper-containing layer and the dielectric layer wherein the second barrier layer is adjacent to an exposed portion of the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer, and a boundary between a sidewall of the copper-containing layer and the first barrier layer is free of the second barrier layer.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Wei Liu, Zhen-Cheng Wu, Cheng-Lin Huang, Po-Hsiang Huang, Yung-Chih Wang, Shu-Hui Su, Dian-Hau Chen, Yuh-Jier Mii
  • Patent number: 8969194
    Abstract: Disclosed is a backside illuminated image sensor including a light receiving element formed in a first substrate, an interlayer insulation layer formed on the first substrate including the light receiving element, a via hole formed through the interlayer insulation layer and the first substrate while being spaced apart from the light receiving element, a spacer formed on an inner sidewall of the via hole, an alignment key to fill the via hole, interconnection layers formed on the interlayer insulation layer in a multilayer structure in which a backside of a lowermost layer of the interconnection layers is connected to the alignment key, a passivation layer covering the interconnection layers, a pad locally formed on a backside of the first substrate and connected to a backside of the alignment key, and a color filter and a microlens formed on the backside of the first substrate corresponding to the light receiving element.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: March 3, 2015
    Assignee: Intellectual Ventures II LLC
    Inventor: Sung-Gyu Pyo
  • Patent number: 8969214
    Abstract: A method of forming a pattern on a substrate includes forming spaced first features derived from a first lithographic patterning step. Sidewall spacers are formed on opposing sides of the first features. After forming the sidewall spacers, spaced second features derived from a second lithographic patterning step are formed. At least some of individual of the second features are laterally between and laterally spaced from immediately adjacent of the first features in at least one straight-line vertical cross-section that passes through the first and second features. After the second lithographic patterning step, all of only some of the sidewall spacers in said at least one cross-section is removed.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: March 3, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Scott L. Light, Kyle Armstrong, Michael D. Hyatt, Vishal Sipani
  • Patent number: 8970046
    Abstract: A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Lyong Kim, Taehoon Kim, Jongho Lee, Chul-Yong Jang
  • Patent number: 8969201
    Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Li Wang, Ding-Kang Shih, Chin-Hsiang Lin, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 8963319
    Abstract: According to one embodiment, a semiconductor chip includes a semiconductor substrate, a via and an insulating layer. The semiconductor substrate has a first major surface and a second major surface on opposite side from the first major surface. The semiconductor substrate is provided with a circuit section including an element and a wiring and a guard ring structure section surrounding the circuit section on the first major surface side. The via is provided in a via hole extending from the first major surface side to the second major surface side of the semiconductor substrate. The insulating layer is provided in a first trench extending from the first major surface side to the second major surface side of the semiconductor substrate.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: February 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumichi Tsumura, Kazuyuki Higashi
  • Patent number: 8957526
    Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: February 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-ho Chun, Byung-lyul Park, Hyun-soo Chung, Gil-heyun Choi, Son-kwan Hwang
  • Patent number: 8951910
    Abstract: A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor device structure includes an insulation layer with at least one damascene conductive structure formed therein, wherein the at least one damascene conductive structure includes an insulative, protective layer disposed thereon. The insulative material of the protective layer is able to resist removal by at least some suitable etchants for the insulative material of the insulation layer adjacent to the at least one damascene conductive structure. A self-aligned opening is formed by removing a portion of an insulation layer adjacent the at least one damascene conductive structure. The self-aligned opening is then filled with a conductive material to thereby provide another conductive structure adjacent to the at least one damascene conductive structure.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: February 10, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Patent number: 8951911
    Abstract: Embodiments described herein generally provide methods for reducing undesired low-k damages during a damascene process using a sacrificial dielectric material and optionally a barrier/capping layer. In one embodiment, a damascene structure is formed through a sacrificial dielectric material deposited over a dielectric base layer. The damascene structure is filled with a suitable metal such as copper. The sacrificial dielectric material filled in trench areas between the copper damascene is then removed, followed by a barrier/cap layer which conformally or selectively covers exposed surfaces of the copper damascene structure. Ultra low-k dielectric materials may then fill the trench areas that were previously filled with sacrificial dielectric material. The invention prevents the ultra low-k material between the metal lines from exposing to various damaging processes during a damascene process such as etching, stripping, wet cleaning, pre-metal cleaning or CMP process.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: February 10, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Mehul B. Naik, Zhenjiang Cui
  • Patent number: 8945996
    Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Roger W. Lindsay, Krishna K. Parat
  • Patent number: 8946077
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeon-Kyu Lee, Bo-Young Song, Seung-Hee Ko, Jin-A Kim, Hyun-Gi Kim, Cheol-Ju Yun, Chae-Ho Lim
  • Patent number: 8940634
    Abstract: A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: January 27, 2015
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES, Inc., STMicroelectronics, Inc.
    Inventors: Brett H. Engel, Lindsey Hall, David F. Hilscher, Randolph F. Knarr, Steven R. Soss, Jin Z. Wallner
  • Patent number: 8940638
    Abstract: In a substrate wiring method, copper is embedded all the way to the lowest parts of a wiring pattern formed on a substrate. The method is used to wire a substrate in a processing chamber kept in a vacuum state, the substrate having a wiring pattern formed thereon. The method includes a preprocessing step in which the wiring pattern on the substrate is cleaned using a desired cleaning gas and an embedding step in which, after the preprocessing step, metal nanoparticles are embedded in the wiring pattern using a clustered metal gas.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: January 27, 2015
    Assignees: Tokyo Electron Limited, Iwatani Corporation
    Inventors: Satohiko Hoshino, Hidefumi Matsui, Masaki Narushima
  • Patent number: 8931169
    Abstract: Methods of fabricating components for microelectronic devices are described herein. For example, one embodiment is directed toward a method of fabricating a memory cell on a workpiece having a substrate, a plurality of active areas in the substrate, and a dielectric layer over the active areas. Bit line contact openings can be formed in the dielectric layer over first portions of the active areas and cell plug openings over second portions of the active areas. A first conductive material is deposited into the bit line contact openings to form bit line contacts and into the cell plug openings to form cell plugs. A conductive line is formed in a trench in the substrate. Dielectric features can electrically insulate the conductive line.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: January 13, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Sanh Dang Tang
  • Publication number: 20150011083
    Abstract: An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring.
    Type: Application
    Filed: September 19, 2014
    Publication date: January 8, 2015
    Inventors: Chung-Hao Tsai, En-Hsiang Yeh, Chuei-Tang Wang
  • Patent number: 8927410
    Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: January 6, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Dave Pratt, Andy Perkins
  • Patent number: 8927413
    Abstract: A semiconductor structure and a fabricating process for the same are provided. The semiconductor fabricating process includes providing a first dielectric layer, a transitional layer formed on the first dielectric layer, and a conductive fill penetrated through the transitional layer and into the first dielectric layer; removing the transitional layer; and forming a second dielectric layer over the conductive fill and the first dielectric layer.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing, Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee
  • Patent number: 8927420
    Abstract: Among other things, one or more support structures and techniques for forming such support structures within semiconductor devices are provided. The support structure comprises an oxide infused silicon layer that is formed within a trench of a dielectric layer on a substrate of a semiconductor device. The oxide infused silicon layer results from a silicon layer that is exposed to oxide during an ultraviolet (UV) curing process. The oxide infused silicon layer is configured to support a barrier layer against a conductive structure formed on the barrier layer within the trench. In this way, the support structure provides pressure against the barrier layer so that the barrier layer substantially maintains contact with the conductive structure, to promote improved performance and reliability of the conductive structure.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Joung-Wei Liou, Keng-Chu Lin
  • Patent number: 8912627
    Abstract: A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to the metal layer. The dual damascene structure also includes a conductive feature within the line opening and the via opening. Dielectric spacers are also present within the line opening and the via opening. The dielectric spacers are present on vertical sidewalls of the patterned dielectric material and separate the conductive feature from the patterned dielectric material. The presence of the dielectric spacers within the line opening and the via opening reduces the area in which the conductive feature is formed. As such, a high programming efficiency electrical fuse is provided in which space is saved.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, David V. Horak, Charles W. Koburger, III, Shom Ponoth