Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming an interconnect layer on a semiconductor component, wherein the interconnect layer contains at least one metal pad electrically coupled to the semiconductor component; depositing an insulating layer on the interconnect layer; depositing a bonding dielectric on the insulating layer; and forming a re-routing layer penetrating through the bonding dielectric and the insulating layer and contacting the interconnect layer.

Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a fan-out redistribution layer (RDL) structure that has plural stacked polymer layers, plural metallization layers, plural conductive vias interconnecting adjacent metallization layers of the metallization layers, and plural rivets configured to resist delamination of one or more of the polymer layers. Each of the plural rivets includes a first head, a second head and a shank connected between the first head and the second head. The first head is part of one of the metallization layers. The shank includes at least one of the conductive vias and at least one part of another of the metallization layers.

Abstract: A method of forming a semiconductor structure includes forming one or more interconnect lines, the one or more interconnect lines including trenches of a first metal material surrounded by a first interlayer dielectric layer. The method also includes forming pillars of a second metal material different than the first metal material over the one or more interconnect lines utilizing a metal on metal growth process, and forming an etch stop dielectric layer, the pillars of the second metal material shaping the etch stop dielectric layer. The method further includes forming one or more vias to the one or more interconnect lines, the one or more vias being fully aligned to the one or more interconnect lines using the etch stop dielectric layer.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor component, a re-routing layer, a bonding dielectric and an insulating layer. The re-routing layer is disposed over the semiconductor component and electrically coupled to the semiconductor component. The bonding dielectric is disposed over the semiconductor component to surround a top portion of the re-routing layer. The insulating layer is disposed between the semiconductor component and the bonding dielectric to surround a bottom portion of the re-routing layer.

Abstract: A memory device includes a plurality of memory cells, a first nonconductive separator material separating the memory cells and having a word line end and bit line end, a metal via separated from the plurality of memory cells by a second nonconductive separator material, and metal bit line electrically connecting the metal via with the plurality of memory cells. The memory cells include a phase change material layer, a first electrode layer adjacent to the phase change material layer and having a phase change material layer side oriented toward the phase change material layer and a bit line side opposite the phase change material layer side, a metal silicon nitride layer on a surface of the bit line side of the first electrode layer. A bit line end surface of the first nonconductive separator material is at least partially free of contact with the metal silicon nitride layer.

Abstract: Techniques and mechanisms for mitigating the effect of signal noise on communication via an interconnect. In an embodiment, a substrate includes an interconnect and a conductor which has a hole formed therein. Portions of the interconnect variously extend over a side of the conductor, wherein another recess portion of the interconnect extends from a plane which includes the side, and further extends at least partially into the hole. The configuration of the recess portion extending within the hole may contribute to an impedance which dampens a transmitter slew rate of the communication. In an embodiment, a total distance along a path formed by the interconnect is equal to or less than 5.5 inches.

Abstract: A method for forming a self-aligned contact includes providing a substrate with a plurality of gate structures including spacers on opposite sides. The method also includes forming a sacrificial layer between the gate structures. The method also includes forming a mask layer on a part of the sacrificial layer. The method also includes forming a plurality of first openings by removing the sacrificial layer exposed from the mask layer. The method also includes forming a dielectric layer in the plurality of first openings. The method also includes removing the mask layer. The method also includes forming a plurality of second openings by removing the sacrificial layer that remains on the substrate. The method also includes forming a plurality of first contact plugs in the second openings.

Abstract: There is provided a method of manufacturing a semiconductor device by processing a substrate, which includes: embedding a polymer having a urea bond in a recess formed in the substrate by supplying a material for polymerization from above a sacrificial film to the substrate and forming a polymer film made of the polymer having the urea bond, wherein a surface of the substrate is covered with the sacrificial film, the recess including an opening of the sacrificial film that is formed by a patterning; removing the polymer film formed on the sacrificial film while leaving the polymer embedded in the recess; removing the sacrificial film in a state in which the polymer is embedded in the recess; and subsequently, removing the polymer embedded in the recess.

Abstract: Provided is a substrate processing method capable of preventing over-etching of a part of a stair-case structure due to an etching solution, when a barrier layer is selectively formed on a VNAND device having the stair-case structure. The substrate processing method includes: alternately stacking a first insulating layer and a second insulating layer; forming a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface to the lower surface by etching the first insulating layer and the second insulating layer that are stacked; densifying the stepped structure; forming a barrier layer on the densified second insulating layer; and performing isotropic etching on at least a part of a sacrificial word line structure including the second insulating layer and the barrier layer. During etching the barrier layer at the isotropic etching step, the second insulating layer is not etched or etched a little to an ignorable degree.

Abstract: A plurality of metal tracks are formed in a plurality of intermetal dielectric layers stacked in an integrated circuit die. Thin protective dielectric layers are formed around the metal tracks. The protective dielectric layers act as a hard mask to define contact vias between metal tracks in the intermetal dielectric layers.

Abstract: A semiconductor memory device according to an embodiment comprises: conductive layers stacked in a vertical direction on a semiconductor substrate; and first and columnar bodies that extend in the vertical direction, the first and second columnar bodies each comprising: a first film; a second film disposed on the first film; and a semiconductor film, and the first film of the second columnar body having an upper end positioned higher than a first position lower than a first conductive layer and lower than a second position higher than the first conductive layer and a lower end positioned at or lower than the first position, and the second film of the second columnar body having an upper end positioned higher than the second position and a lower end positioned lower than the first position.

Abstract: An asymmetric stair structure includes multiple unit layers and has m regions (m?2). In each of the m regions, a different part of unit layers having an interval of m unit layers each have a portion not covered by an upper adjacent unit layer, so that a stair having a step difference of m unit layers is formed. In arbitrary two of the m regions, the two different parts of unit layers include no repeated unit layers.

Abstract: A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the protrusion structure and extends to a bottom portion of the protrusion structure as a raised drain region. A drain contact is disposed over the drain region and overlap with the isolation feature.

Abstract: A vertical NAND-type memory device includes a vertical stack of inter-gate insulating layers and gate electrodes arranged in an alternating sequence on an underlying substrate, which includes a cell array region and a contact region therein. At least one NAND-type channel structure is provided, which extends vertically through the vertical stack of inter-gate insulating layers and gate electrodes. An end sidewall of a first of the gate electrodes, which extends laterally over at least a portion of the contact region, has a vertical slope that is less steep than vertical slopes of end sidewalls of a first plurality of the gate electrodes extending between the first of the gate electrodes and the substrate.

Abstract: A vertically integrated circuit device can include a substrate having a first region reserved for first functional circuits of the vertically integrated circuit device, where the first functional circuits has a substantially constant top surface level across the first region and having a second region reserved for second functional circuits of the vertically integrated circuit device and spaced apart from the first region. The second functional circuits can have a varied top surface level across the second region. A doped oxidation suppressing material can be included in the substrate and can extend from the first region to the second region at an interface of the substrate with the first functional circuits and the second functional circuits, respectively.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a conductive structure over the substrate. The semiconductor device structure includes first metal oxide fibers over the conductive structure. The semiconductor device structure includes a dielectric layer over the substrate and covering the conductive structure and the first metal oxide fibers. The dielectric layer fills gaps between the first metal oxide fibers.

Abstract: A trench can be formed through a stack of alternating plurality of first material layers and second material layers. A dielectric material liner and a trench fill material portion can be formed in the trench. The dielectric material liner and portions of first material layer can be simultaneously etched to form laterally-extending cavities having level-dependent lateral extents. A set of stepped surfaces can be formed by removing unmasked portions of the second material layers. Alternately, an alternating sequence of processing steps including vertical etch processes and lateral recess processes can be employed to laterally recess second material layers and to form laterally-extending cavities having level-dependent lateral extents. Lateral cavities can be simultaneously formed in multiple levels such that levels having laterally-extending cavities of a same lateral extent are offset across multiple integrated cavities.

Abstract: The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) selectivity stress films that apply a stress that improves the performance of semiconductor devices underlying the BEOL selectivity stress films, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices having a first device type. A stress transfer element is located within a back-end-of-the-line stack at a position over the one or more semiconductor devices. A selectivity stress film is located over the stress transfer element. The selectivity stress film induces a stress upon the stress transfer element, wherein the stress has a compressive or tensile state depending on the first device type of the one or more semiconductor devices. The stress acts upon the one or more semiconductor devices to improve their performance.

Abstract: This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode over a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate, a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, and etch stop layers including metal silicide and formed over the pipe connection gate electrode.

Abstract: This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a bottom buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled to the pipe channel layer and extended in a direction substantially perpendicular to the substrate, and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, wherein the pipe connection gate electrode includes a metal silicide layer formed within the groove. The electric resistance of the pipe connection gate electrode may be greatly reduced without an increase in a substantial height by forming the metal silicide layer buried in the substrate under the pipe connection gate electrode.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes fabricating a crack-stop structure that extends through a plurality of metallization layers above a semiconductor substrate. The plurality of metallization layers includes a first metallization layer and a second metallization layer that overlies the first metallization layer. Fabricating the crack-stop structure includes forming a first via-bar overlying and coupled to a first metal line of the first metallization layer that is disposed in a first ILD layer of dielectric material. The first via-bar is disposed in a second ILD layer of dielectric material and has a first width. A second metal line of the second metallization layer that is in the second ILD layer is formed overlying and coupled to the first via-bar. The second metal line has a second width that is from about 1 to about 5 times the first width.

Abstract: The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via (“TSV”) extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad.

Abstract: A solid-state image pickup device is provided which includes a plurality of pixels provided in a semiconductor substrate, the pixels including a plurality of photoelectric conversion portions and MOS transistors which selectively read out signals therefrom, at least one organic photoelectric conversion film on the photoelectric conversion portions, and an isolation region provided in the organic photoelectric conversion film at a position corresponding to between the pixels to perform optical and electrical isolation.

Abstract: The solar cell module having a preferable edge space that prevents characteristics of a solar cell such as conversion efficiency from being deteriorated without making processes complicated is provided. In a method for manufacturing a solar cell module including a substrate glass, a first layer formed on the substrate glass and a second layer formed on the first layer, the method includes a step of forming a first edge space having a first width by removing the first layer and the second layer by the first width from an end part of the glass substrate and a step of forming a second edge space by removing only the second layer by a second width from the end part of the glass substrate, and the width of the second edge space is larger than the width of the first edge space.

Abstract: Methods of fabricating a multi-layer semiconductor device such as a multi-layer damascene or inverted multi-layer damascene structure using only a single or reduced number of exposure steps. The method may include etching a precursor structure formed of materials with differential removal rates for a given removal condition. The method may include removing material from a multi-layer structure under different removal conditions. Further disclosed are multi-layer damascene structures having multiple cavities of different sizes. The cavities may have smooth inner wall surfaces. The layers of the structure may be in direct contact. The cavities may be filled with a conducting metal or an insulator. Multi-layer semiconductor devices using the methods and structures are further disclosed.

Abstract: Techniques are disclosed that enable interconnects, vias, metal gates, and other conductive features that can be formed through electroless material deposition techniques. In some embodiments, the techniques employ electroless fill in conjunction with high growth rate selectivity between an electroless nucleation material (ENM) and electroless suppression material (ESM) to generate bottom-up or otherwise desired fill pattern of such features. Suitable ENM may be present in the underlying or otherwise existing structure, or may be provided. The ESM is provisioned so as to prevent or otherwise inhibit nucleation at the ESM covered areas of the feature, which in turn prevents or otherwise slows down the rate of electroless growth on those areas. As such, the electroless growth rate on the ENM sites is higher than the electroless growth rate on the ESM sites.

Abstract: Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material.

Abstract: A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer.

Abstract: A method of forming a multi-floor step pattern structure includes forming a stacked structure having alternating insulating interlayers and sacrificial layers on a substrate. A first photoresist pattern is formed on the stacked structure. A first preliminary step pattern structure is formed by etching portions of the stacked structure using the first photoresist pattern as an etching mask. A passivation layer pattern is formed on upper surfaces of the first photoresist pattern and the first preliminary step pattern structure. A second photoresist pattern is formed by removing a side wall portion of the first photoresist pattern exposed by the passivation layer pattern. A second preliminary step pattern structure is formed by etching exposed insulating interlayers and underlying sacrificial layers using the second photoresist pattern as an etching mask. The above steps may be repeated on the second preliminary step pattern structure to form the multi-floor step pattern structure.

Abstract: A method for forming a trench includes etching an oxide layer to form a trench therein, conformally forming a first reaction layer along a surface of the trench, the first reaction layer including a first region on an upper portion of the trench and a second region on a lower portion of the trench, forming a barrier layer by reacting a first amount of etching gas with the first region of the first reaction layer, and etching the oxide layer on a lower portion of the second region by reacting a second amount of etching gas with the second region of the first reaction layer, the second amount of etching gas being greater than the first amount of etching gas.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound.

Abstract: Embodiments of the present invention provide a method of forming contact structure for transistor. The method includes providing a semiconductor substrate having a first and a second gate structure of a first and a second transistor formed on top thereof, the first and second gate structures being embedded in a first inter-layer-dielectric (ILD) layer; epitaxially forming a first semiconductor region between the first and second gate structures inside the first ILD layer; epitaxially forming a second semiconductor region on top of the first semiconductor region, the second semiconductor region being inside a second ILD layer on top of the first ILD layer and having a width wider than a width of the first semiconductor region; and forming a silicide in a top portion of the second semiconductor region.

Abstract: A thin film transistor element includes: a gate electrode; a source electrode and a drain electrode; an insulating layer; partition walls; and an organic semiconductor layer. The partition walls define a first aperture. Within the first aperture, at least a part of the source electrode and at least a part of the drain electrode are in contact with the semiconductor layer. The partition walls have side face portions facing the first aperture, and some of the side face portions have gentler slopes than the rest of the side face portions.

Abstract: A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks in the metal layers above and below the intermediate metal layer.

Abstract: Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method of forming a conductive via element disclosed herein includes forming a via opening in a substrate, the via opening extending through an interlayer dielectric layer formed above the substrate and a device layer formed below the interlayer dielectric layer, and extending into the substrate. The method also includes forming a first portion of the conductive via element comprising a first conductive contact material in a bottom portion of the via opening, and forming a second portion of the conductive via element comprising a second conductive contact material different from the first conductive contact material in an upper portion of the via opening and above the first portion.

Abstract: A method of fabricating a semiconductor device may include forming isolation structures that include openings, over a substrate; forming sacrificial spacers on sidewalls of the openings; forming, on the sacrificial spacers, first conductive patterns that are recessed in the openings; removing the sacrificial spacers, and defining air gaps; forming a liner layer that caps the first conductive patterns and the air gaps; forming second conductive patterns through silicidation of the liner layer; and forming third conductive patterns over the second conductive patterns.

Abstract: A method for fabricating a semiconductor device includes sequentially forming an etch stop film and an insulating film on a substrate including a lower pattern forming a conductive mask pattern including a first opening on the insulating film, forming a via-hole in the insulating film using the conductive mask pattern as an etch mask, the via-hole exposing the etch stop film, removing the conductive mask pattern, and forming a passivation film along a side wall of the via-hole after removing the conductive mask pattern.

Abstract: A thin film transistor element includes: a gate electrode; a source electrode and a drain electrode; an insulating layer; partition walls; and an organic semiconductor layer. The partition walls define a first aperture. Within the first aperture, at least a part of the source electrode and at least a part of the drain electrode are in contact with the semiconductor layer. In plan view of the bottom of the first aperture, the center of the total of the areas of the source electrode and the drain electrode is offset from the center of the area of the bottom in a given direction.

Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.

Abstract: A process of modulating the thickness of a barrier layer deposited on the sidewalls and floor of a recessed feature in a semiconductor substrate is disclosed. The process includes altering the surface of the conductive feature on which the barrier layer is deposited by annealing in a reducing atmosphere and optionally additionally, silylating the dielectric surface that forms the sidewalls of the recessed feature.

Abstract: A method of making a semiconductor device includes forming a dielectric layer over a semiconductor substrate. The method further includes forming a copper-containing layer in the dielectric layer, wherein the copper-containing layer has a first portion and a second portion. The method further includes forming a first barrier layer between the first portion of the copper-containing layer and the dielectric layer. The method further includes forming a second barrier layer at a boundary between the second portion of the copper-containing layer and the dielectric layer wherein the second barrier layer is adjacent to an exposed portion of the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer, and a boundary between a sidewall of the copper-containing layer and the first barrier layer is free of the second barrier layer.

Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer.

Abstract: A method of forming a pattern on a substrate includes forming spaced first features derived from a first lithographic patterning step. Sidewall spacers are formed on opposing sides of the first features. After forming the sidewall spacers, spaced second features derived from a second lithographic patterning step are formed. At least some of individual of the second features are laterally between and laterally spaced from immediately adjacent of the first features in at least one straight-line vertical cross-section that passes through the first and second features. After the second lithographic patterning step, all of only some of the sidewall spacers in said at least one cross-section is removed.

Abstract: A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.

Abstract: Disclosed is a backside illuminated image sensor including a light receiving element formed in a first substrate, an interlayer insulation layer formed on the first substrate including the light receiving element, a via hole formed through the interlayer insulation layer and the first substrate while being spaced apart from the light receiving element, a spacer formed on an inner sidewall of the via hole, an alignment key to fill the via hole, interconnection layers formed on the interlayer insulation layer in a multilayer structure in which a backside of a lowermost layer of the interconnection layers is connected to the alignment key, a passivation layer covering the interconnection layers, a pad locally formed on a backside of the first substrate and connected to a backside of the alignment key, and a color filter and a microlens formed on the backside of the first substrate corresponding to the light receiving element.

Abstract: According to one embodiment, a semiconductor chip includes a semiconductor substrate, a via and an insulating layer. The semiconductor substrate has a first major surface and a second major surface on opposite side from the first major surface. The semiconductor substrate is provided with a circuit section including an element and a wiring and a guard ring structure section surrounding the circuit section on the first major surface side. The via is provided in a via hole extending from the first major surface side to the second major surface side of the semiconductor substrate. The insulating layer is provided in a first trench extending from the first major surface side to the second major surface side of the semiconductor substrate.

Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.

Abstract: Embodiments described herein generally provide methods for reducing undesired low-k damages during a damascene process using a sacrificial dielectric material and optionally a barrier/capping layer. In one embodiment, a damascene structure is formed through a sacrificial dielectric material deposited over a dielectric base layer. The damascene structure is filled with a suitable metal such as copper. The sacrificial dielectric material filled in trench areas between the copper damascene is then removed, followed by a barrier/cap layer which conformally or selectively covers exposed surfaces of the copper damascene structure. Ultra low-k dielectric materials may then fill the trench areas that were previously filled with sacrificial dielectric material. The invention prevents the ultra low-k material between the metal lines from exposing to various damaging processes during a damascene process such as etching, stripping, wet cleaning, pre-metal cleaning or CMP process.

Abstract: A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor device structure includes an insulation layer with at least one damascene conductive structure formed therein, wherein the at least one damascene conductive structure includes an insulative, protective layer disposed thereon. The insulative material of the protective layer is able to resist removal by at least some suitable etchants for the insulative material of the insulation layer adjacent to the at least one damascene conductive structure. A self-aligned opening is formed by removing a portion of an insulation layer adjacent the at least one damascene conductive structure. The self-aligned opening is then filled with a conductive material to thereby provide another conductive structure adjacent to the at least one damascene conductive structure.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.