Abstract: A method for manufacturing a semiconductor device that improves the reliability of a metal cap layer and productivity. The method includes an insulation layer step of superimposing an insulation layer(11) on a semiconductor substrate (2) including an element region (2b), a recess step of forming a recess (12) in the insulation layer (11), a metal layer step of embedding a metal layer (13) in the recess (12), a planarization step of planarizing a surface of the insulation layer (11) and a surface of the metal layer (13) to be substantially flush with each other, and a metal cap layer step of forming a metal cap layer (16) containing at least zirconium element and nitrogen element on the surface of the insulation layer (11) and the surface of the metal layer (13) after the planarization step.

Abstract: Methods of forming semiconductor devices having customized contacts are provided including providing a first insulator layer and patterning the first insulator layer such that the first insulator layer defines at least one contact window. A second insulator layer is provided on the first insulator layer and in the at least one contact window such that the second insulator layer at least partially fills the at least one contact window. A first portion of the second insulator layer is etched such that a second portion of the second insulator layer remains in the at least one contact window to provide at least one modified contact window having dimensions that are different than dimensions of the at least one contact window. Related methods and devices are also provided.

Abstract: A semiconductor structure includes: at least one silicon surface wherein the surface can be a substrate, wafer or other device. The structure further includes at least one electronic circuit formed on each side of the at least one surface; and at least one conductive high aspect ratio through silicon via running through the at least one surface. Each through silicon via is fabricated from at least one etch step and includes: at least one thermal oxide dielectric for coating at least some of a sidewall of the through silicon via for a later etch stop in fabrication of the through silicon via.

Abstract: A method for manufacturing an image sensor includes forming circuitry including a metal line over a semiconductor substrate, forming a photodiode over the metal line, and forming a contact plug in the photodiode such that the contact plug is connected to the metal line. The forming of the contact plug includes performing a first etch process to etch a portion of the photodiode, and performing a second etch process to expose a portion of the metal line by using a byproduct generated in etching, to form a via hole for the contact plug in the photodiode.

Abstract: An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.

Abstract: A semiconductor wafer has an insulating layer formed over an active surface of the wafer. A conductive layer is formed over the insulating layer. A first via is formed from a back surface of the semiconductor wafer through the semiconductor wafer and insulating layer to the conductive layer. A conductive material is deposited in the first via to form a conductive TSV. An insulating material can be deposited in the first via to form an insulating core within the conductive via. After forming the conductive TSV, a second via is formed around the conductive TSV from the back surface of the semiconductor wafer through the semiconductor wafer and insulating layer to the conductive layer. An insulating material is deposited in the second via to form an insulating annular ring. The conductive via can be recessed within or extend above a surface of the semiconductor die.

Abstract: In sophisticated semiconductor devices, strain-inducing materials having a reduced dielectric strength or having certain conductivity, such as metal nitride and the like, may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors. For this purpose, a strain-inducing material may be efficiently encapsulated on the basis of a dielectric layer stack that may be patterned prior to forming the actual interlayer dielectric material in order to mask sidewall surface areas on the basis of spacer elements.

Abstract: A method for fabricating a semiconductor device includes: (a) forming an interlayer insulating film on a substrate; (b) forming an interconnect in the interlayer insulating film; (c) applying an organic solution to an upper surface of the interconnect and an upper surface of the interlayer insulating film; (d) after (c), applying a silylating solution to the upper surface of the interconnect and the upper surface of the interlayer insulating film; (e) after (d), heating the substrate; and (f) forming a first liner insulating film at least on the upper surface of the interconnect.

Abstract: A semiconductor device includes a semiconductor substrate and a through electrode provided in a through hole formed in the semiconductor substrate. The through electrode partially protrudes from a back surface of the semiconductor substrate, which is opposite to an active surface thereof. The through electrode includes a resin core and a conductive film covering at least a part of the resin core.

Abstract: A semiconductor device comprises insulating layer including damascene patterns and formed over a semiconductor substrate, conductive line formed higher than the insulating layer within the respective damascene patterns, and interference-prevention grooves formed within the damascene patterns between sidewalls of the conductive line and the insulating layer.

Abstract: Semiconductor dice comprise at least one bond pad on an active surface of the semiconductor die. At least one blind hole extends from a back surface of the semiconductor die opposing the active surface, through a thickness of the semiconductor die, to an underside of the at least one bond pad. At least one quantity of passivation material covers at least a sidewall surface of the at least one blind hole. At least one conductive material is disposed in the at least one blind hole adjacent and in electrical communication with the at least one bond pad and adjacent the at least one quantity of passivation material.

Abstract: An electronic device package and a fabrication method thereof are provided. The fabrication method includes providing a semiconductor substrate containing a plurality of chips having a first surface and an opposite second surface. A plurality of conductive electrodes is disposed on the first surface and the conductive electrodes of the two adjacent chips are arranged asymmetrically along side direction of the chip. A plurality of contact holes is formed in each chip, apart from the side of the chip, to expose the conductive electrodes.

Abstract: A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.

Abstract: A semiconductor device manufacturing method including: forming a first interlayer insulating film on a semiconductor substrate; forming a first hole in the first interlayer insulating film; forming a barrier film inside the first hole; filling a conductive material in the first hole to form a first plug; forming a second interlayer insulating film on the first interlayer insulating film; forming a second hole reaching the first plug in the second interlayer insulating film; selectively etching an upper end of the barrier film inside the second hole; and forming a second plug for connection to the first plug inside the second hole.

Abstract: A semiconductor device manufacturing method includes: stacking a plurality of electrode layers containing a semiconductor alternately with insulating layers; processing part of a multilayer body of the electrode layers and the insulating layers into a staircase shape and exposing a surface of the staircase-shaped electrode layers; forming a metal film in contact with the exposed electrode layers; reacting the semiconductor of the electrode layers with the metal film to form a metal compound in at least a portion of the electrode layers in contact with the metal film; removing an unreacted portion of the metal film; forming an interlayer insulating layer covering the staircase-shaped electrode layers after removing the unreacted portion of the metal film; forming a plurality of contact holes piercing the interlayer insulating layer, each of the contact holes reaching the metal compound of the electrode layer at a corresponding stage; and providing a plurality of contact electrodes inside the contact holes.

Abstract: A photovoltaic cell manufacturing method is disclosed. Methods include manufacturing a photovoltaic cell having a selective emitter and buried contact (electrode) structure utilizing nanoimprint technology. The methods include providing a semiconductor substrate having a first surface and a second surface opposite the first surface; forming a first doped region in the semiconductor substrate adjacent to the first surface; performing a nanoimprint process and an etching process to form a trench in the semiconductor substrate, the trench extending into the semiconductor substrate from the first surface; forming a second doped region in the semiconductor substrate within the trench, the second doped region having a greater doping concentration than the first doped region; and filling the trench with a conductive material. The nanoimprint process uses a mold to define a location of an electrode line layout.

Abstract: A method for controlling an ADI-AEI CD difference ratio of openings having different sizes is described. The openings are formed through a silicon-containing material layer, an etching resistive layer and a target material layer in turn. Before the opening etching steps, at least one of the opening patterns in the photoresist mask is altered in size through photoresist trimming or deposition of a substantially conformal polymer layer. A first etching step forming thicker polymer on the sidewall of the wider opening pattern is performed to form a patterned Si-containing material layer. A second etching step is performed to remove exposed portions of the etching resistive layer and the target material layer. At least one parameter among the parameters of the photoresist trimming or polymer layer deposition step and the etching parameters of the first etching step is controlled to obtain a predetermined ADI-AEI CD difference ratio.

Abstract: A hard mask material is removed from an SOI substrate without using a chemical mechanical polish (CMP) process. A blocking material is deposited on a hard mask material after a deep trench reactive ion etch (RIE) process. The blocking material on top of the hard mask material is removed. A selective wet etching process is used to remove the hard mask material. Trench recess depth is effectively controlled.

Abstract: A method of forming a thin film pattern includes: forming a thin film on a substrate; forming an amorphous carbon layer including first and second carbon layers on the thin film, wherein the first carbon layer is formed by one of a spin-on method and a plasma enhanced chemical vapor deposition (PECVD) method and the second carbon layer is formed by a physical vapor deposition (PVD) method; forming a hard mask layer on the amorphous carbon layer; forming a PR pattern on the hard mask layer; forming a hard mask pattern by etching the hard mask layer using the PR pattern as an etch mask; forming an amorphous carbon pattern including first and second carbon patterns by etching the amorphous carbon layer using the hard mask pattern as an etch mask; and forming a thin film pattern by etching the thin film using the amorphous carbon pattern.

Abstract: A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.

Abstract: A semiconductor device includes a through-silicon-via arranged to couple a plurality of stacked semiconductor chips, an interconnection line coupled to the through-silicon-via at one side and arranged to couple the through-silicon-via to the semiconductor chip, an internal interconnection line disposed at the other side of the interconnection line and intersected with the interconnection line, and at least one first contact disposed to couple the internal interconnection line to the interconnection line. A region of the interconnection line in which the internal interconnection line is disposed is equally divided, and an area between the divided regions is removed.

Abstract: A semiconductor device and a method for manufacturing the device include connecting a second wafer to a first wafer, forming a hard mask layer on and/or over a backside of the second wafer, forming a hard mask pattern over the second layer and then forming a via hole by etching the first and the second wafers to a predetermined depth using the hard mask pattern as an etching mask.

Abstract: A semiconductor device, which reduces the earth inductance, and a fabrication method for the same is provided.

Abstract: An integrated circuit arrangement containing a via is disclosed. The via has an upper section having greatly inclined sidewalls. A lower section of the via has approximately vertical sidewalls. In one embodiment, a liner layer is used as a hard mask in the production of the via and defines the position of the sections of the via.

Abstract: A semiconductor chip, an electrode structure and a method of manufacture, the chip including a semiconductor substrate having a multi-level interconnection and an electrode pad connected to the interconnection, a protective film on the substrate, an insulating film on the protective film, a bump of a metal on the electrode pad, and a barrier layer between the side of the bump and the insulation film.

Abstract: A via structure having improved reliability and performance and methods of forming the same are provided. The via structure includes a first-layer conductive line, a second-layer conductive line, and a via electrically coupled between the first-layer conductive line and the second-layer conductive line. The via has a substantially tapered profile and substantially extends into a recess in the first-layer conductive line.

Abstract: The present invention relates to a silicon chip having a through via and a method for making the same. The silicon chip includes a silicon substrate, a passivation layer, at least one electrical device and at least one through via. The passivation layer is disposed on a first surface of the silicon substrate. The electrical device is disposed in the silicon substrate, and exposed to a second surface of the silicon substrate. The through via includes a barrier layer and a conductor, and penetrates the silicon substrate and the passivation layer. A first end of the through via is exposed to the surface of the passivation layer, and a second end of the through via connects the electrical device. When a redistribution layer is formed on the surface of the passivation layer, the redistribution layer will not contact the silicon substrate, thus avoiding a short circuit. Therefore, a lower resolution process can be used, which results in low manufacturing cost and simple manufacturing process.

Abstract: A semiconductor device according to one embodiment includes: a substrate having an element region where a semiconductor element is formed; a via hole formed in a portion of the substrate adjacent to the element region; a conducting portion provided in the via hole via an insulating layer; and a buffer layer provided between the substrate and the insulating layer, wherein the buffer layer is made of a material in which a difference in thermal expansion coefficient between the substrate and the buffer layer is smaller than that between the substrate and the insulating layer.

Abstract: A silicide film is formed between a ferroelectric capacitor structure, which is formed by sandwiching a ferroelectric film between a lower electrode and an upper electrode, and a conductive plug (the conductive material constituting the plug is tungsten (W) for example). Here, an example is shown in which a base film of the conductive plug is the silicide film.

Abstract: A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer.

Abstract: This invention is directed to solving problems with a mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of a second insulation film on an inner wall of a mesa groove corresponding to a PN junction, and offers a mesa type semiconductor device of high withstand voltage and high reliability and its manufacturing method. After the mesa groove is formed by dry-etching, wet-etching with an etching solution including hydrofluoric acid and nitric acid is further applied to a sidewall of the mesa groove to form an overhang made of the first insulation film above an upper portion of the mesa groove. The overhang serves as a barrier to prevent the second insulation film formed in the mesa groove and on the first insulation film around the mesa groove beyond an area of the overhang from flowing toward a bottom of the mesa groove due to an increased fluidity resulting from a subsequent thermal treatment.

Abstract: A method of fabricating a three-dimensional semiconductor device includes forming a stacked structure, and the stacked structure includes a first layer, a second layer, a third layer, and a fourth layer sequentially stacked on a substrate. The method also includes forming a sacrificial spacer on a sidewall of the stacked structure such that the sacrificial spacer exposes a sidewall of the third layer, and recessing the exposed sidewall of the third layer thereby forming a recess region between the second and fourth layers.

Abstract: Some embodiments include methods of forming semiconductor constructions in which a semiconductor material sidewall is along an opening, a protective organic material is over at least one semiconductor material surface, and the semiconductor material sidewall and protective organic material are both exposed to an etch utilizing at least one fluorine-containing composition. The etch is selective for the semiconductor material relative to the organic material, and reduces sharpness of at least one projection along the semiconductor material sidewall. In some embodiments, the opening is a through wafer opening, and subsequent processing forms one or more materials within such through wafer opening to form a through wafer interconnect. In some embodiments, the opening extends to a sensor array, and the protective organic material is comprised by a microlens system over the sensor array. Subsequent processing may form a macrolens structure across the opening.

Abstract: The present invention provides a method of forming a contact opening, such as a via hole, in which a sacrificial layer is deposited prior to exposing a conductor formed in a substrate at a bottom side of the opening to prevent damage and contamination to the materials constituting an integrated circuit device from happening. The exposing may or may not form a recess in the conductor. The present invention also provides a method of forming a contact opening having a recess in the conductor wherein a sacrificial layer is not deposited until the conductor is exposed, but deposited before a recess is formed in the conductor so that a major damage and contamination related to the recess formation can be prevented. By forming a trench feature over a contact opening formed by using the present invention, a dual damascene feature can be fabricated.

Abstract: Provided is a semiconductor device which has excellent adhesiveness to a copper film and a base film thereof and has a small resistance between wirings. The semiconductor device includes a porous insulating layer (SIOC film 11) which absorbed water from the atmosphere, and a substrate (wafer W) having a trench 100 formed on such insulating film is placed in a processing chamber. The substrate is coated with a first base film (Ti film 13) made of a valve metal. The surface of the first film brought into contact with the insulating film is oxidized by the water discharged from the insulating layer, and a passivation film 13a is formed. The surface of the first base film is coated with a second base film made of nitride or carbide of the valve metal, and a copper film 15 is formed on the surface of the second base film by CVD by using a copper organic compound as a material.

Abstract: A through substrate via having a low stress is provided. The through substrate via is positioned in a substrate. The through substrate via includes: an outer tube penetrating the substrate; at least one inner tube disposed within the outer tube; a dielectric layer lining on a side wall of the outer tube, and a side wall of the inner tube; a strength-enhanced material filling the inner tube; and a conductive layer filling the outer tube.

Abstract: Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Abstract: Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a temporary carrier may be secured to the layer of conductive material on a side thereof opposite the substrate prior to forming the vias. Structures, including workpieces formed using such methods, are also disclosed.

Abstract: The present invention relates to a method for forming a recess array device structure in a semiconductor substrate. The method includes the steps of: providing a base material including a semiconductor substrate and a first material; forming a plurality of second recesses on the semiconductor substrate; forming a second material in the second recesses; forming a metal layer on the second material and the base material, wherein the metal layer includes a first portion and a second portion; removing the second portion to form a plurality of metal layer openings; to and etching the base material according to the metal layer openings so as to form a plurality of third recesses. Accordingly, the metal layer can overcome the non-selectivity issue during the etching process.

Abstract: A chip carrier substrate includes a capacitor aperture and a laterally separated via aperture, each located within a substrate. The capacitor aperture is formed with a narrower linewidth and shallower depth than the via aperture incident to a microloading effect within a plasma etch method that is used for simultaneously etching the capacitor aperture and the via aperture within the substrate. Subsequently a capacitor is formed and located within the capacitor aperture and a via is formed and located within the via apertures. Various combinations of a first capacitor plate layer, a capacitor dielectric layer and a second capacitor plate layer may be contiguous with respect to the capacitor aperture and the via aperture.

Abstract: An integrated circuit device structure with a novel contact feature. The structure includes a substrate, a dielectric layer overlying the substrate, and a metal interconnect overlying the dielectric layer. A first interlayer dielectric layer is formed surrounding the metal interconnect. A second interlayer dielectric layer of a predetermined thickness is overlying the first interlayer dielectric layer. A trench opening of a first width is formed within an upper portion of the second interlayer dielectric layer. A first barrier layer is within and is overlying the trench opening of the first width. A contact opening of a second width is within a lower portion of the second interlayer dielectric layer. The second width is less than the first width. The lower portion of the second interlayer dielectric layer is coupled to the upper portion of the second interlayer dielectric layer within the predetermined thickness of the second interlayer dielectric.

Abstract: One or more embodiments relate to a method of forming an electronic device, comprising: providing a workpiece; forming a first barrier layer over the workpiece; forming an intermediate conductive layer over the first barrier layer; forming a second barrier layer over the intermediate conductive layer; forming a seed layer over the second barrier layer; removing a portion of the seed layer to leave a remaining portion of the seed layer and to expose a portion of the second barrier layer; and electroplating a fill layer on the remaining portion of the seed layer.

Abstract: In a method of forming a contact plug of a semiconductor device, a nitride layer is prevented from being broken by forming a passivation layer over the nitride layer when contact holes are formed by etching an insulating layer between select lines formed over a semiconductor substrate. In an etch process of forming the contact plug, the passivation layer formed on sidewalls of the select lines is formed twice to protect the sidewalls of the select lines. Accordingly, the sidewalls of the select lines can be prevented from being damaged. Consequently, a process margin necessary to form a contact plug can be increased and, therefore, a smaller contact plug can be formed.

Abstract: A semiconductor device includes an interconnect having electrically conductive portions and a dielectric layer made of a first dielectric material. A trench is formed in the dielectric layer. The exposed portions of the dielectric layer which form the side walls of the trench are removed. A dielectric liner is then deposited on the side walls of the trench, the liner being made of a second dielectric material.

Abstract: A semiconductor device includes a plurality of stacked semiconductor chips; and a plurality of through-silicon vias (TSVs) including first TSVs and redundant TSVs and configured to commonly transfer a signal to the plurality of stacked semiconductor chips. At least one of the semiconductor chips includes a plurality of repair fuse units configured to store defect information as to at least one defect of the TSVs; and a plurality of latch units allocated to the respective TSVs and configured to store a plurality of signals indicating at least one TSV defect and outputted from the plurality of repair fuse units.

Abstract: A through-wafer interconnect and a method for fabricating the same are disclosed. The method starts with a conductive wafer to form a patterned trench by removing material of the conductive wafer. The patterned trench extends in depth from the front side to the backside of the wafer, and has an annular opening generally dividing the conductive wafer into an inner portion and an outer portion whereby the inner portion of the conductive wafer is insulated from the outer portion and serves as a through-wafer conductor. A dielectric material is formed or added into the patterned trench mechanical to support and electrically insulate the through-wafer conductor. Multiple conductors can be formed in an array.

Abstract: The disclosure provides a chip package structure and method for fabricating the same. The chip package structure includes at least one chip having at least one through via. At least one stress buffering structure is disposed in the through via. The stress buffering structure includes a first gasket and a second gasket. A supporting pillar has two terminals respectively connected to the first gasket and the second gasket. The cross-sectional area of the supporting pillar is smaller than areas of the first gasket and the second gasket. A buffering layer is sandwiched between the first gasket and the second gasket, surrounding a sidewall of the supporting pillar. An insulating layer is disposed on the through via, surrounding a sidewall of the stress buffering structure.

Abstract: A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer.

Abstract: Metallization systems on the basis of copper and low-k dielectric materials may be efficiently formed by providing an additional dielectric material of enhanced surface conditions after the patterning of the low-k dielectric material. Consequently, defects such as isolated copper voids and the like may be reduced without significantly affecting overall performance of the metallization system.

Abstract: Methods of forming nonvolatile memory devices include forming a stack of layers of different materials on a substrate. This stack includes a plurality of first layers of a first material and a plurality of second layers of a second material arranged in an alternating sequence of first and second layers. A selected first portion of the stack of layers is isotropically etched for a sufficient duration to define a first trench therein that exposes sidewalls of the alternating sequence of first and second layers. The sidewalls of each of the plurality of first layers are selectively etched relative to sidewalls of adjacent ones of the plurality of second layers. Another etching step is then performed to recess sidewalls of the plurality of second layers and thereby expose portions of upper surfaces of the plurality of first layers. These exposed portions of the upper surfaces of the plurality of first layers, which may act as word lines of a memory device, are displaced laterally relative to each other.