Abstract: The present invention describes a method for forming an interconnect to a region of an electronic device. The method comprises the steps of: forming a conductive material layer, wherein the conductive material layer fills an opening in a first dielectric layer and is disposed over the first dielectric layer; applying a patterning layer over the conductive material layer, wherein the patterning layer exposes a portion of the conductive material layer; etching the conductive material layer to remove the portion of the conductive material layer in order to provide an exposed conductive material structure that protrudes above the dielectric layer; forming a second dielectric layer; and planarizing the second dielectric layer to expose a portion of the exposed conductive material structure.

Abstract: A method for forming a copper interconnect on an integrated circuit (IC) begins by forming a dielectric layer (20) having an opening. A tantalum-based barrier layer (21), such as TaN or TaSiN, is formed within the opening in the layer (20). A copper layer (22) is formed over the barrier layer (21). A first CMP process is used to polish the copper (22) to expose portions of the barrier (21). A second CMP process which is different from the first CMP process is then used to polish exposed portions of the layer (21) faster than the dielectric layer (20) or the copper layer (22). After this two-step CMP process, a copper interconnect having a tantalum-based barrier is formed across the integrated circuit substrate (12).

Abstract: A method of fabricating a metal wiring line includes providing a semiconductor substrate having a region desired for connecting with the metal wiring line, wherein a first dielectric layer is formed to cover the semiconductor substrate and a plurality of substantially parallel oxide pillars are formed on the first dielectric layer. The metal wiring line is then formed to contact the desired connecting region, and a second metal layer is then formed to contact the metal wiring line.

Abstract: A method of burying a conductive metal into a contact hole formed in an insulation film formed over a silicon substrate. Within the contact hole a refractory metal silicide layer has been formed on the silicon substrate and a barrier metal layer has been formed on the refractory metal silicide layer and further a conductive metal film has been formed on the barrier metal layer.

Abstract: A process of polishing two dissimilar conductive materials deposited on semiconductor device substrate optimizes the polishing of each of the conductive material independently, while utilizing the same polishing equipment for manufacturing efficiency. A tungsten layer (258) and a titanium layer (256) of a semiconductor device substrate (250) are polished using one polisher (10) but two different slurry formulations. The two slurries can be dispensed sequentially onto the same polishing platen (132) from two different source containers (111 and 112), wherein the first slurry is dispensed until the tungsten is removed and then the slurry dispense is switched to the second slurry for removal of the titanium. In a preferred embodiment, the first slurry composition is a ferric nitrate slurry while the second slurry composition is an oxalic acid slurry.

Abstract: A method of chemical-mechanical polishing of a semiconductor device utilizes a combination of polishing steps, including a first step using a first slurry containing an abrasive component (i.e., mechanical component) and a chemical component (i.e., chemical reactants), and a second polishing step using a second slurry having a reduced amount of the abrasive component. The method is carried out with respect to metal (39), such as copper, deposited on a dielectric layer (34) and the first polishing step is stopped before the entirety of the metal overlying the dielectric layer is removed. In one embodiment, the second slurry has no abrasive component.

Abstract: In a semiconductor memory device, first insulating films are formed on a semiconductor substrate. Element isolating layers are formed on the semiconductor substrate for isolating element forming regions set at regular intervals in the semiconductor substrate, such that the upper surface of the element isolating layers are located at a higher level than the upper surface of the semiconductor substrate. First conductive layers are formed at regular intervals on the first insulating films. A second insulating film is formed on the element isolating layers and the first conductive layer. A second conductive layer, which has a lower surface with irregularities corresponding to the configurations of the element isolating layers and the first conductive layer, and a flat upper surface irrespective of the configurations of the element isolating films and the first conductive layer, is formed on the second insulating film.

Abstract: The method of metallization includes the steps as follows. At first, a semiconductor substrate is provided and a dielectric layer is formed over the semiconductor substrate. A portion of the dielectric layer is removed to form contact holes and a first conductive layer is formed within the contact holes and over the dielectric layer. A portion of the first conductive layer is removed to define a contact pattern. Using the first conductive layer as a mask, a portion of the dielectric layer is removed to form openings within the dielectric layer and over the first conductive layer. A second conductive layer is then formed within the openings and over the first conductive layer. To planarize the surface of the semiconductor substrate, a portion of the second conductive layer and the first conductive layer is removed to planarize to the dielectric layer.

Abstract: A method of manufacturing a semiconductor device has the steps of: forming a wiring pattern by dry etching a wiring layer on a semiconductor substrate, using a resist pattern as a mask; immersing the wiring pattern in amine containing liquid to remove deposition residues formed during the dry etching; then, processing the wiring pattern with fluid not containing amine and being capable of removing deposition residues; forming a conformal insulating layer on the processed wiring pattern; and forming an insulating layer having a planarizing function on the conformal insulating layer by CVD. This method is suitable for multi-layer wiring, and can form an interlayer insulating film having a satisfactory planarizing function.

Abstract: A MIS type field effect transistor has a source/drain region overlain by a titanium silicide layer contiguous to an upper silicon nitride layer of a buried isolating structure embedded into a silicon substrate, and a contact hole is formed in an inter-level insulating layer of silicon oxide exposing a part of the upper silicon nitride layer and a part of the titanium silicide layer into the contact hole; while the inter-level insulating layer is being selectively etched so as to form the contact hole, the upper silicon nitride layer serves as an etching stopper, and the contact hole never reaches the silicon substrate beneath the buried isolating structure.

Abstract: A method is described for overcoming the non-conformity and poor step coverage incurred when materials such as metals and barrier materials are deposited into contact or via openings by physical-vapor-deposition (PVD) techniques such as sputtering and evaporation. Conventional PVD deposition into a vertical walled opening results in the formations of cusps along the walls at the mouth of the opening. These cusps obstruct the material stream into the depth of the opening, resulting in inadequate coverage at the base of the opening particularly at the corners. This increases the chance of failure of the barrier material resulting in a reliability exposure. In addition, the cusps, if not removed, cause the formation of voids in subsequently deposited conductive plugs. The invention teaches the insulative layer, wherein the openings are formed, to be deposited to a greater thickness than required by the design. The openings are then formed and filled with a spin-on-glass.

Abstract: A dummy pattern is generated by enlarging a wiring pattern by a specified amount to generate an enlarged wiring pattern and deleting the overlapping portion of a first dummy original pattern composed of a group of squares with the enlarged wiring pattern. The dummy pattern is reduced by the specified amount to generate a reduced dummy pattern, which is enlarged by the specified amount to generate a planarizing pattern. The planarizing pattern is combined with the wiring pattern to generate a final pattern.

Abstract: Methods of forming electrical interconnects include the steps of forming a first electrically conductive layer on a semiconductor substrate and then forming a first electrically insulating layer on the first electrically conductive layer. A second electrically insulating layer is then formed on the first electrically insulating layer. The second electrically insulating layer is then etched to expose the first electrically insulating layer and then a third electrically insulating layer is formed on the first electrically insulating layer. The first and third electrically insulating layers are then etched to define a contact hole therein which exposes a portion of the first electrically conductive layer. A barrier metal layer is then formed. The barrier metal layer is preferably formed to extend on the third electrically insulating layer and on the exposed portion of the first electrically conductive layer.

Abstract: A method for fabricating a multi-level integrated circuit is disclosed which utilizes a grid pattern from which portions corresponding to the metal layer are selectively removed to form a mask which is subsequently used to deposit dummy features in the open areas between metal lines, thereby to allow the deposition of a substantially planar dielectric surface over the metal layers and dummy features.

Abstract: On a semiconductor substrate, an SiO.sub.2 layer as an insulating layer and an intermediate insulating layer are stacked successively. The intermediate insulating layer selectively has an opening portion and a copper wiring is formedwithin the opening portion. The copper wiring is covered with an anti-oxidation layer. The anti-oxidation layer is formed of copper sulfide so that it becomes unnecessary to form another anti-oxidation layer which does not contain copper, the treatment in the vacuum can be simplified or thermal treatment step at high temperatures can be omitted.

Abstract: A method of manufacturing a semiconductor component with a multi-level interconnect system includes providing a substrate (11), fabricating a device (12) in the substrate (11), forming an interconnect layer (15) over the substrate (11), depositing a dielectric layer (20) over the interconnect layer (15), depositing a separate interconnect layer (21) over the dielectric layer (20), etching a via (31) in the separate interconnect layer (21) and in the dielectric layer (20), and depositing a different interconnect layer (40) over the separate interconnect layer (21) and in the via (31) wherein the another interconnect layer (40) electrically couples the interconnect layer (15) and the separate interconnect layer (21).

Abstract: Disclosed is an aluminum filled via hole for use in a semiconductor interconnect structure. The aluminum filled via hole of the semiconductor interconnect structure includes a first patterned metallization layer lying over a first dielectric layer. A second dielectric layer overlying the first patterned metallization layer and the first dielectric layer. An aluminum filled via hole defined through the second dielectric layer and in contact with the first patterned metallization layer. The aluminum filled via hole has an electromigration barrier cap over a topmost portion of the aluminum filled via hole that is substantially level with the second dielectric layer. The electromigration barrier cap having a thickness of between about 500 angstroms and about 2,500 angstroms.

Abstract: A method of planarizing an inter-metal dielectric layer includes providing a semiconductor substrate having a component layer formed thereon; and forming a metallic layer over the component layer. Then, portions of the metallic layer are etched to form metal pads on the metallic layer surface. Next, the metallic layer is patterned and portions of the metallic layer are etched to form a plurality of metal lines and trenches between the metal lines. Subsequently, a first oxide layer is deposited over the metal lines and the trenches, and then a spin on glass layer is formed over the first oxide layer, filling up the trenches. Thereafter, portions of the spin on glass layer are etched back to expose the metal pad and form a residual spin on glass layer, and then a second oxide layer is formed over the metal pad, the residual spin on glass layer and the first oxide layer. Portions of the second oxide layer are etched to form an opening in the second oxide layer that corresponds to the metal pad location.

Abstract: A process for fabricating multilayer connection which provides a flattened surface of an interlayer insulating film and realizes a highly reliable semiconductor device, including: forming an interlayer dielectric film on a lower layer connection and forming an aperture portion in the interlayer dielectric film, the aperture portion being connected to the lower layer connection; forming a metallic film on the entire surface of the interlayer dielectric film inclusive of the aperture portion, thereby filling the aperture portion with a material constituting the metallic film; removing the metallic film from the interlayer dielectric film by etching, except for the metallic film material left over inside the aperture portion; flattening the surface by applying chemical mechanical polishing to the upper surface of the interlayer dielectric film; and forming an upper layer connection on the interlayer dielectric film, the upper layer connection being connected to the metallic film material left over inside the ape

Abstract: A method for forming within a Field Effect Transistor (FET) for use within an integrated circuit a polycide gate electrode. There is first provided a semiconductor substrate. Formed upon the semiconductor is a patterned polysilicon layer. Formed then upon the semiconductor substrate and the patterned polysilicon layer is a blanket insulator layer. The blanket insulator layer is then patterned through planarizing to form a patterned planarized insulator layer while simultaneously exposing the surface of the patterned polysilicon layer. Finally, there is formed upon the exposed surface of the patterned polysilicon layer a patterned metal silicide layer. The patterned metal silicide layer and the patterned polysilicon layer form a polycide gate electrode. The metal silicide layer within the polycide gate electrode is not susceptible to encroachment upon adjoining insulator spacers or source/drain regions within the Field Effect Transistor (FET) within which is formed the polycide gate electrode.

Abstract: A method of fabricating a semiconductor device includes the steps of forming an inter-layer insulating film, forming a contact hole in the inter-layer insulating film, forming a thin conductive film filling the contact hole and covering the inter-layer insulating film, and forming a contact plug filling the contact hole by etching the thin conductive film and thus exposing the surface of the inter-layer insulating film. The etching is conducted such that, from the time when a surface of the inter-layer insulating film is about to be exposed, the thin conductive film and the inter-layer insulating film are etched under substantially the same etching speed. Plug loss in the contact hole is suppressed so that wiring breakage in the contact hole can be prevented.

Abstract: A method of forming aluminum contacts of submicron dimensions wherein, after formation of both vias and line openings in a silicon oxide layer, a metal stop layer is deposited, followed by deposition of aluminum. Alternatively, the metal stop layer is deposited prior to forming the vias and line openings. The excess aluminum is removed by chemical-mechanical polishing, the stop layer providing high selectivity to the chemical mechanical polishing. The stop layer is then removed. The resultant silicon oxide-aluminum surface is planar and undamaged by the chemical-mechanical polishing step.

Abstract: A method for forming multilevel interconnects in a semiconductor IC device is provided. The method involves a simplified planarization process for planarization of inter-metal dielectrics that allows for easy and cost-effective fabrication of the device. By this method, an insulating layer is formed over a substrate, then a first conductive layer is formed over the insulating layer and which is selectively removed to form conductive interconnects. Subsequently, a dielectric layer is formed over the conductive interconnects. A photoresist layer is then formed and patterned over the dielectric layer by a spin-coating process. An etching process is then conducted on the photoresist layer and the dielectric layer with a 1:1 etching ratio until the photoresist layer is completely removed. At the same moment when the photoresist layer is completely removed, the via holes are formed. The following steps are the same for fabricating the next-level interconnects.

Abstract: An object of the present invention is to completely reduce a difference in level in a short time at a convex pattern spreading horizontally on a large scale and obtain a semiconductor device having a planarized surface. An insulating film is formed on a semiconductor substrate to cover a horizontally spreading convex pattern and to fill in a concave portion. A portion of insulating film located on a planarized portion of convex pattern is selectively etched away so as to leave a frame-shaped insulating film having a width of 1-500 .mu.m at least on the outer periphery portion of convex pattern. Insulating film left on semiconductor substrate is etched by chemical/mechanical polishing method, thereby planarizing a surface of the semiconductor substrate.

Abstract: A novel, high performance, high reliability interconnection structure for an integrated circuit. The interconnection structure of the present invention is formed on a first insulating layer which in turn is formed on a silicon substrate or well. A first multilayer interconnection comprising a first aluminum layer, a first refractory metal layer, and a second aluminum layer is formed on the first insulating layer. A second insulating layer is formed over the first multilayer interconnection. A conductive via is formed through the second insulating layer and recessed into the first multilayer interconnection wherein a portion of the via extends above the second insulating layer. A second interconnection is formed on the second insulating layer and on and around the portion of the via extending above the second insulating layer.

Abstract: A method of forming electromigration resistant integrated circuit runners is disclosed. A collimated beam of particles is directed toward a substrate to form a metal nucleating layer. Then a non-collimated beam is used to form the rest of the metal layer. Then the layers are patterned to form runners.

Abstract: A Chemical-Mechanical Polish (CMP) planarizing method and a Chemical-Mechanical Polish (CMP) slurry composition for Chemical-Mechanical Polish (CMP) planarizing of copper metal and copper metal alloy layers within integrated circuits. There is first provided a semiconductor substrate having formed upon its surface a patterned substrate layer. Formed within and upon the patterned substrate layer is a blanket copper metal layer or a blanket copper metal alloy layer. The blanket copper metal layer or blanket copper metal alloy layer is then planarized through a Chemical-Mechanical Polish (CMP) planarizing method employing a Chemical-Mechanical Polish (CMP) slurry composition. The Chemical-Mechanical Polish (CMP) slurry composition comprises a non-aqueous coordinating solvent and a halogen radical producing specie.

Abstract: A method for forming a metal plug is provided. The method includes: a) forming a metal contact window in a substrate having an oxide layer; b) forming a barrier layer over a top surface of the oxide layer and a wall defining the metal contact window; c) forming a metal layer covering the barrier layer and filling up the metal contact window; d) removing a portion of the metal layer located above the barrier layer covering the top surface of the oxide layer by a chemical mechanical polishing method; and e) removing the barrier layer covering the top surface of the oxide layer by an etching method.

Abstract: The uniformity in buried condition of conductors in contact holes is enhanced over the entire wafer surface. A first resist is coated on a conductor provided selectively in a contact hole formed in an insulating film provided on a semiconductor substrate, as well as on the insulating film, and a resultant structure is flattened. The first resist and the conductor are removed with their portions being left. A second resist is coated on the conductor and insulating film and a resultant structure is flattened. The second resist and the conductor are removed until the insulating film is exposed.

Abstract: A method for forming a Damascene structured multi-layered metal wiring for a semiconductor element, which includes the steps for forming a first insulating layer on the surface of a semiconductor substrate, forming a lower metal wiring pattern on the first insulating layer, forming a second insulating layer on the first insulating layer and the lower metal wiring pattern, forming contacts by subjecting the second insulating layer to etching, successively depositing first and second upper metals over the second insulating layer and the contact, subjecting the second upper metal to etching until the first upper metal is exposed, and forming an upper metal wiring pattern having a double metal structure by subjecting the first upper metal to etching until the second insulating layer is exposed. The upper wiring layer is preferably formed of aluminum deposited by a sputtering method and tungsten deposited by a chemical vapor deposition method.

Abstract: A method of forming metal lines such as titanium and aluminum on a semiconductor wafer by sputtering at a high temperature, preferably in the range of approximately 500.degree. C. to 800.degree. C. This method decreases the contact resistance between the layers while reducing the number of processing steps.

Abstract: In a semiconductor device and a method for manufacturing the same according to the present invention, for example, an insulating film is deposited on a silicon substrate, and a concave groove is formed in the insulating film in accordance with a predetermined wiring pattern. Titanium and palladium are deposited in sequence on the insulating film to form a titanium film and a palladium film, respectively. A silver film is formed on the palladium film by electroplating, and a groove-shaped silver wiring layer is formed by polishing. The resultant structure is annealed at a temperature of about 700.degree. C., and an intermetallic compound is formed by alloying the titanium film and palladium film with each other. Consequently, a burying type wiring layer whose resistance is lower than that of aluminum, is constituted by the silver wiring layer and intermetallic compound.

Abstract: A method for the fabrication of an ohmic, low resistance contact to silicon is described using a CVD deposited tungsten plug provided with Ti/TiN barrier metallurgy. The method provides for a glass insulator layer deposited on the silicon. After the glass is flowed to planarize its surface, contact holes are patterned in the glass exposing the silicon substrate. The Ti/TiN barrier metallurgy is deposited by sputtering which, because of inferior edge coverage, results in a sidewall with a negative taper. Subsequent deposition of the tungsten results in a tungsten plug with an exposed void. The method taught by this invention deposits first a thin layer of tungsten whose thickness is governed by the amount of overhang caused by the tapered sidewall. An anisotropic dry etch step is then performed to achieve a vertical sidewall of tungsten. The remaining tungsten is then deposited to fill the contact opening without the occurrence of voids.

Abstract: A method of forming a wiring layer for a semiconductor device forms a first layer on a dielectric film on a substrate to protect integrated circuit devices from overpolishing when a wiring layer is formed on a second layer above the polish stop layer. The wiring layer is deposited using selective chemical vapor deposition to prevent contamination of the wafer.

Abstract: A method for forming a conductive line uses a fluorine doped oxide layer as an insulating layer between conductive lines. The method comprises the steps of: (a) forming a fluorine doped oxide layer on a semiconductor substrate on which a lower structure is formed; (b) etching the oxide layer of the region where a conductive line is to be formed, thereby forming a trench; (c) forming an insulating layer on the overall surface of the resultant substrate; depositing conductive material on the resultant substrate; and (e) etching back the conductive material so that the conductive material is left on the trench only, thereby forming a conductive line. In this method, the conductive line is formed of aluminum-containing material and the insulating layer is formed of silicon dioxide. In the present invention, the insulating layer is interposed between the fluorine doped oxide layer and the aluminum-containing conductive line and thus the conductive line is free from corrosion.

Abstract: A method of planarizing an electrical contact region in a silicon substrate uses spin-on-glass or polysilicon as plug material (42) to fill a contact hole (34). A device or doped region (31) is formed at the surface of the substrate (30) and an insulating layer (33) is formed over the substrate so that the entire doped region is covered by the insulating layer. The contact hole is then formed through the insulating layer to expose a portion of the doped region. To increase the conductivity of the doped region through the contact hole, a filler layer of either spin-on-glass or polysilicon, thick enough to substantially fill the contact hole, is formed over the insulating layer. The filler layer is then etched away from the portions around the contact hole by a conventional dry or wet oxide etching process.

Abstract: A surface mountable integrated circuit and a method of manufacture are disclosed. A wafer 110 has a die with an integrated circuit 119 in one surface of the wafer. A via 130 extends to the opposite surface. The via has a sidewall oxide 131 and is filled with a conductive material such as metal or doped polysilicon. The metal may comprise a barrier layer and an adhesion layer. The second end of the via can be fashioned as a prong 233 or a receptacle 430. Dies with vias can be stacked on top of each other or surface mounted to printed circuit boards or other substrate.