Having Refractory Group Metal (i.e., Titanium (ti), Zirconium (zr), Hafnium (hf), Vanadium (v), Niobium (nb), Tantalum (ta), Chromium (cr), Molybdenum (mo), Tungsten (w), Or Alloy Thereof) Patents (Class 438/648)
  • Patent number: 9812328
    Abstract: Embodiments described herein generally relate to methods for forming silicide materials. Silicide materials formed according to the embodiments described herein may be utilized as contact and/or interconnect structures and may provide advantages over conventional silicide formation methods. In one embodiment, a one or more transition metal and aluminum layers may be deposited on a silicon containing substrate and a transition metal layer may be deposited on the one or more transition metal and aluminum layers. An annealing process may be performed to form a metal silicide material.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: November 7, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Kaushal K. Singh, Er-Xuan Ping, Xianmin Tang, Sundar Ramamurthy, Randhir Thakur
  • Patent number: 9698011
    Abstract: The process for growing at least one semiconductor nanowire (3), said growth process comprising a step of forming, on a substrate (1), a nucleation layer (2) for the growth of the nanowire (3) and a step of growth of the nanowire (3). The step of formation of the nucleation layer (2) comprises the following steps: deposition onto the substrate (1) of a layer of a transition metal (4) chosen from Ti, V, Cr, Zr, Nb, Mo, Hf, Ta; nitridation of at least a part (2) of the transition metal layer so as to form a transition metal nitride layer having a surface intended for growing the nanowire (3).
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: July 4, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Berangere Hyot, Benoit Amstatt, Marie-Francoise Armand
  • Patent number: 9385152
    Abstract: The present invention relates to a solid-state image pickup device. The device includes a first substrate including a photoelectric conversion element and a transfer gate electrode configured to transfer charge from the photoelectric conversion element, a second substrate having a peripheral circuit portion including a circuit configured to read a signal based charge generated in the photoelectric conversion element, the first and second substrates being laminated. The device further includes a multilayer interconnect structure, disposed on the first substrate, including an aluminum interconnect and a multilayer interconnect structure, disposed on the second substrate, including a copper interconnect.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: July 5, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Nobuyuki Endo, Tetsuya Itano, Kazuo Yamazaki, Kyouhei Watanabe, Takeshi Ichikawa
  • Patent number: 9269615
    Abstract: A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: February 23, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vivian W. Ryan, Xunyuan Zhang, Paul R. Besser
  • Patent number: 9190320
    Abstract: Described are apparatus and methods for forming films comprise indium and arsenic. In particular, these films may be formed in a configuration of two or more chambers under “load lock” conditions. These films may include additional components as dopants, such as aluminum and/or gallium. Such films can be used in metal/silicon contacts having low contact resistances. Also disclosed are devices including the films comprising indium arsenide.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: November 17, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Khaled Z. Ahmed, Prabu Gopalraja, Atif Noori, Mei Chang
  • Patent number: 9112003
    Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on copper instead of insulating or dielectric materials. In some embodiments, a first precursor forms a layer on the first surface and is subsequently reacted or converted to form a metallic layer. The deposition temperature may be selected such that a selectivity of above about 50% or even about 90% is achieved.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: August 18, 2015
    Assignee: ASM International N.V.
    Inventors: Suvi P. Haukka, Antti Niskanen, Marko Tuominen
  • Patent number: 9082834
    Abstract: A nitride semiconductor device is provide that can reduce contact resistance of an ohmic electrode and a nitride semiconductor layer. In a GaN HFET, recesses (106, 109) are formed in a nitride semiconductor multilayer body (20) composed of an undoped GaN layer (1) and an undoped AlGaN layer (2) formed on an Si substrate (10), and a source electrode (11) and a drain electrode (12) are formed in the recesses (106, 109). In a region deeper than an interface (S1, S2) between the GaN layer (1) and the source electrode (11) and drain electrode (12), which are formed from a TiAl material, a first chlorine concentration peak (P11) is formed in vicinity of the interface, and a second chlorine concentration peak (P22) having a chlorine concentration of 1.3×1017 cm?3 or lower is formed at a position deeper than the first chlorine concentration peak (P11).
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: July 14, 2015
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tadashi Yasui, Satoshi Morishita, Koichiro Fujita, Daisuke Kurita
  • Patent number: 9076843
    Abstract: A tungsten nucleation film is formed on a surface of a semiconductor substrate by alternatively providing to that surface, reducing gases and tungsten-containing gases. Each cycle of the method provides for one or more monolayers of the tungsten film. The film is conformal and has improved step coverage, even for a high aspect ratio contact hole.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: July 7, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Sang-Hyeob Lee, Joshua Collins
  • Patent number: 9064942
    Abstract: A method of fabricating an electronic device includes the following steps. At least one first set and at least one second set of nanowires and pads are etched in an SOI layer of an SOI wafer. A first gate stack is formed that surrounds at least a portion of each of the first set of nanowires that serves as a channel region of a capacitor device. A second gate stack is formed that surrounds at least a portion of each of the second set of nanowires that serves as a channel region of a FET device. Source and drain regions of the FET device are selectively doped. A first silicide is formed on the source and drain regions of the capacitor device that extends at least to an edge of the first gate stack. A second silicide is formed on the source and drain regions of the FET device.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: June 23, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Amlan Majumdar, Jeffrey W. Sleight
  • Patent number: 9040413
    Abstract: A nonvolatile memory device contains a resistive switching memory element with improved device switching performance and lifetime by custom tailoring the average concentration of defects in the resistive switching film and methods of forming the same. The nonvolatile memory element includes a first electrode layer, a second electrode layer, and a resistive switching layer disposed between the first electrode layer and the second electrode layer. The resistive switching layer comprises a first sub-layer and a second sub-layer, wherein the first sub-layer has more defects than the first sub-layer. A method includes forming a first sub-layer on the first electrode layer by a first ALD process and forming a second sub-layer on the first sub-layer by a second ALD process, where the first sub-layer has a different amount of defects than the second sub-layer.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: May 26, 2015
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Randall J. Higuchi, Chien-Lan Hsueh, Yun Wang
  • Patent number: 9034760
    Abstract: Methods, apparatus, and systems for depositing tensile or compressive tungsten films are described. In one aspect, a method includes providing a substrate to a chamber. The substrate has a field region and a feature recessed from the field region. Then, the substrate is exposed to an organometallic tungsten precursor. The organometallic tungsten precursor not adsorbed onto the substrate is removed from the chamber. The substrate is treated with a first treatment including a heat treatment or a plasma treatment to form a tungsten layer on the substrate. After treating the substrate, residual gasses are removed from the chamber. The tungsten layer on the substrate is treated with a second treatment including a heat treatment or a plasma treatment.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: May 19, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Feng Chen, Tsung-Han Yang, Juwen Gao, Roey Shaviv, Raashina Humayun, Deqi Wang
  • Patent number: 8987134
    Abstract: Semiconductor devices and methods of making thereof are disclosed. The semiconductor device includes a substrate prepared with a first dielectric layer formed thereon. The dielectric layer includes at least first, second and third contact regions. A second dielectric layer is disposed over the first dielectric layer. The device also includes at least first, second and third via contacts disposed in the second dielectric layer. The via contacts are coupled to the respective underlying contact regions and the via contacts do not extend beyond the underlying contact regions.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: March 24, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Zhehui Wang, Kwee Liang Yeo, Hai Cong, Huang Liu, Wen Zhan Zhou
  • Patent number: 8981332
    Abstract: A nonvolatile resistive memory element includes an oxygen-gettering layer. The oxygen-gettering layer is formed as part of an electrode stack, and is more thermodynamically favorable in gettering oxygen than other layers of the electrode stack. The Gibbs free energy of formation (?fG°) of an oxide of the oxygen-gettering layer is less (i.e., more negative) than the Gibbs free energy of formation of an oxide of the adjacent layers of the electrode stack. The oxygen-gettering layer reacts with oxygen present in the adjacent layers of the electrode stack, thereby preventing this oxygen from diffusing into nearby silicon layers to undesirably increase an SiO2 interfacial layer thickness in the memory element and may alternately be selected to decrease such thickness during subsequent processing.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 17, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Tony P. Chiang, Dipankar Pramanik, Milind Weling
  • Patent number: 8980743
    Abstract: A wafer level semiconductor device and manufacturing method including providing a semiconductor device wafer substrate having a backside, applying to the backside a conductive metallization layer, and applying to the backside over the conductive metallization layer a protective metal layer of titanium, titanium alloys, nickel, nickel alloys, chromium, chromium alloys, cobalt. cobalt alloys, palladium, and palladium alloys.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: March 17, 2015
    Assignee: FlipChip International LLC
    Inventors: Guy F. Burgess, Shannon D. Buzard, Anthony P. Curtis, Douglas M. Scott
  • Patent number: 8969196
    Abstract: A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Ho Park, Gil-Heyun Choi, Byung-Lyul Park, Jong-Myeong Lee, Zung-Sun Choi, Hye-Kyung Jung
  • Patent number: 8969195
    Abstract: Processes for improving adhesion of films to semiconductor wafers and a semiconductor structure are provided. By implementing the processes of the invention, it is possible to significantly suppress defect creation, e.g., decrease particle generation, during wafer fabrication processes. More specifically, the processes described significantly reduce flaking of a TaN film from edges or extreme edges (bevel) of the wafer by effectively increasing the adhesion properties of the TaN film on the wafer. The method increasing a mol percent of nitride with respect to a total tantalum plus nitride to 25% or greater during a barrier layer fabrication process.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Felix P. Anderson, Steven P. Barkyoumb, Edward C. Cooney, III, Thomas L. McDevitt, William J. Murphy, David C. Strippe
  • Patent number: 8952541
    Abstract: A contact may be fabricated by a method including depositing a dielectric layer on a substrate having a transistor, etching a first opening in the dielectric layer that extends to a source region, forming an insulator on the source region, forming a contact metal on the insulator, the insulator separating the contact metal from the source region, and filling substantially all of the first opening, wherein the contact metal remains separated from the source region after the first opening is filled.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: February 10, 2015
    Assignee: Intel Corporation
    Inventors: Niloy Mukherjee, Gilbert Dewey, Matthew V. Metz, Jack Kavalieros, Robert S. Chau
  • Publication number: 20150037973
    Abstract: A method of forming a capping layer over copper containing contacts in a dielectric layer with a liner comprising a noble metal liner around the copper containing contacts is provided. An electroless deposition is provided to deposit a deposition comprising copper on the noble metal liner and the copper containing contacts. A capping layer is formed over the deposition comprising copper.
    Type: Application
    Filed: July 30, 2013
    Publication date: February 5, 2015
    Inventors: Dries DICTUS, Artur KOLICS
  • Patent number: 8937009
    Abstract: Disclosed are a method for metallization during semiconductor wafer processing and the resulting structures. In this method, a passivation layer is patterned with first openings aligned above and extending vertically to metal structures below. A mask layer is formed and patterned with second openings aligned above the first openings, thereby forming two-tier openings extending vertically through the mask layer and passivation layer to the metal structures below. An electrodeposition process forms, in the two-tier openings, both under-bump pad(s) and additional metal feature(s), which are different from the under-bump pad(s) (e.g., a wirebond pad; a final vertical section of a crackstop structure; and/or a probe pad). Each under-bump pad and additional metal feature initially comprises copper with metal cap layers thereon.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Karen P. McLaughlin, Ekta Misra, Christopher D. Muzzy, Eric D. Perfecto, Wolfgang Sauter
  • Patent number: 8916880
    Abstract: A semiconductor device that can suppress deterioration in crystal quality caused by a lattice mismatch between a substrate and an epitaxial layer and that also can ensure a voltage sustaining performance, and a wafer for forming the semiconductor device. An epitaxial wafer of silicon carbide (SiC), which is used for manufacturing a semiconductor device, includes a low resistance substrate and an epitaxial layer provided thereon. The epitaxial layer is doped with the same dopant as a dopant doped into the substrate, and has a laminated structure including a low concentration layer and an ultrathin high concentration layer. A doping concentration in the low concentration layer is lower than that in the silicon carbide substrate. A doping concentration in the ultrathin high concentration layer is equal to that in the silicon carbide substrate.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: December 23, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichi Ohtsuka, Nobuyuki Tomita, Tomoaki Furusho
  • Patent number: 8901740
    Abstract: A contact may be fabricated by a method including depositing a dielectric layer on a substrate having a transistor, etching a first opening in the dielectric layer that extends to a source region, forming an insulator on the source region, forming a contact metal on the insulator, the insulator separating the contact metal from the source region, and filling substantially all of the first opening, wherein the contact metal remains separated from the source region after the first opening is filled.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: December 2, 2014
    Assignee: Intel Corporation
    Inventors: Niloy Mukherjee, Gilbert Dewey, Matthew V. Metz, Jack Kavalieros, Robert S. Chau
  • Patent number: 8900899
    Abstract: Novel processing methods for production of high-refractive index contrast and low loss optical waveguides are disclosed. In one embodiment, a “channel” waveguide is produced by first depositing a lower cladding material layer with a low refractive index on a base substrate, a refractory metal layer, and a top diffusion barrier layer. Then, a trench is formed with an open surface to the refractory metal layer. The open surface is subsequently oxidized to form an oxidized refractory metal region, and the top diffusion barrier layer and the non-oxidized refractory metal region are removed. Then, a low-refractive-index top cladding layer is deposited on this waveguide structure to encapsulate the oxidized refractory metal region. In another embodiment, a “ridge” waveguide is produced by using similar process steps with an added step of depositing a high-refractive-index material layer and an optional optically-transparent layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: December 2, 2014
    Inventor: Payam Rabiei
  • Patent number: 8896136
    Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: November 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Fang Wen Tsai, Weng-Jin Wu, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 8888916
    Abstract: Embodiments of the present invention provide apparatus and method for improving gas distribution during thermal processing. One embodiment of the present invention provides an apparatus for processing a substrate comprising a chamber body defining a processing volume, a substrate support disposed in the processing volume, wherein the substrate support is configured to support and rotate the substrate, a gas inlet assembly coupled to an inlet of the chamber body and configured to provide a first gas flow to the processing volume, and an exhaust assembly coupled to an outlet of the chamber body, wherein the gas inlet assembly and the exhaust assembly are disposed on opposite sides of the chamber body, and the exhaust assembly defines an exhaust volume configured to extend the processing volume.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: November 18, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Ming-Kuei (Michael) Tseng, Norman L. Tam, Yoshitaka Yokota, Agus S. Tjandra, Robert Navasca, Mehran Behdjat, Sundar Ramamurthy, Kedarnath Sangam, Alexander N. Lerner
  • Patent number: 8883637
    Abstract: A method for filling a recessed feature of a substrate includes a) at least partially filling a recessed feature of a substrate with tungsten-containing film using at least one of chemical vapor deposition (CVD) and atomic layer deposition (ALD); b) at a predetermined temperature, using an etchant including activated fluorine species to selectively etch the tungsten-containing film more than an underlying material of the recessed feature without removing all of the tungsten-containing film at a bottom of the recessed feature; and c) filling the recessed feature using at least one of CVD and ALD.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: November 11, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Esther Jeng, Anand Chandrashekar, Raashina Humayun, Michal Danek, Ronald Powell
  • Patent number: 8884400
    Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tung-Liang Shao, Ying-Ju Chen, Tsung-Yuan Yu, Jie Chen
  • Patent number: 8865594
    Abstract: The invention provides a method of forming a film stack on a substrate, comprising performing a silicon containing gas soak process to form a silicon containing layer over the substrate, reacting with the silicon containing layer to form a tungsten silicide layer on the substrate, depositing a tungsten nitride layer on the substrate, subjecting the substrate to a nitridation treatment using active nitrogen species from a remote plasma, and depositing a conductive bulk layer directly on the tungsten nitride layer.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: October 21, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Sang-Hyeob Lee, Sang Ho Yu, Kai Wu
  • Patent number: 8865013
    Abstract: A method for chemical mechanical polishing of a substrate comprising tungsten using a nonselective chemical mechanical polishing composition.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: October 21, 2014
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Yi Guo, Jerry Lee, Raymond L. Lavoie, Jr., Guangyun Zhang
  • Patent number: 8853075
    Abstract: Methods of forming titanium-containing layers on substrates are disclosed. In the disclosed methods, the vapor of a precursor compound having the formula Ti(Me5Cp)(OR)3, wherein R is selected from methyl, ethyl, or isopropyl is provided. The vapor is reacted with the substrate according to an atomic layer deposition process to form a titanium-containing complex on the surface of the substrate.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: October 7, 2014
    Assignee: L'Air Liquide Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude
    Inventors: Satoko Gatineau, Christian Dussarrat, Christophe Lachaud, Nicolas Blasco, Audrey Pinchart, Ziyun Wang, Jean-Marc Girard, Andreas Zauner
  • Patent number: 8841212
    Abstract: A method patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber. Next, sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening. A second Tantalum Nitride layer is formed on the conductor, the Tantalum layer, and the first Tantalum Nitride layer, again in the first chamber. After the second Tantalum Nitride layer is formed, the methods herein form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer in a second, different chamber.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Takeshi Nogami, Thomas M. Shaw, Andrew H. Simon, Jean E. Wynne, Chih-Chao Yang
  • Patent number: 8835309
    Abstract: A method of performing a silicide contact process comprises a forming a nickel-platinum alloy (NiPt) layer over a semiconductor device structure; performing a first rapid thermal anneal (RTA) so as to react portions of the NiPt layer in contact with semiconductor regions of the semiconductor device structure, thereby forming metal rich silicide regions; performing a first wet etch to remove at least a nickel constituent of unreacted portions of the NiPt layer; performing a second wet etch using a dilute Aqua Regia treatment comprising nitric acid (HNO3), hydrochloric acid (HCl) and water (H2O) to remove any residual platinum material from the unreacted portions of the NiPt layer; and following the dilute Aqua Regia treatment, performing a second RTA to form final silicide contact regions from the metal rich silicide regions.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: David F. Hilscher, Christian Lavoie, Ahmet S. Ozcan
  • Patent number: 8835311
    Abstract: Embodiments of the invention provide an improved process for depositing tungsten-containing materials. In one embodiment, the method for forming a tungsten-containing material on a substrate includes forming an adhesion layer containing titanium nitride on a dielectric layer disposed on a substrate, forming a tungsten nitride intermediate layer on the adhesion layer, wherein the tungsten nitride intermediate layer contains tungsten nitride and carbon. The method further includes forming a tungsten barrier layer (e.g., tungsten or tungsten-carbon material) from the tungsten nitride intermediate layer by thermal decomposition during a thermal annealing process (e.g., temperature from about 700° C. to less than 1,000° C.).
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: September 16, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Joshua Collins, Murali K. Narasimhan, Jingjing Liu, Sang-Hyeob Lee, Kai Wu, Avgerinos V. Gelatos
  • Patent number: 8835310
    Abstract: Electrodes, which contain molybdenum dioxide (MoO2) can be used in electronic components, such as memory or logic devices. The molybdenum-dioxide containing electrodes can also have little or no molybdenum element, together with a portion of molybdenum oxide, e.g., MoOx with x between 2 and 3. The molybdenum oxide can be present as molybdenum trioxide MoO3, or in Magneli phases, such as Mo4O11, MO8O23, or Mo9O26. The molybdenum-dioxide containing electrodes can be formed by annealing a multilayer including a layer of molybdenum and a layer of molybdenum oxide. The oxygen content of the multilayer can be configured to completely, or substantially completely, react with molybdenum to form molybdenum dioxide, together with leaving a small excess amount of molybdenum oxide MoOx with x>2.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: September 16, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Sergey Barabash, Dipankar Pramanik, Xuena Zhang
  • Patent number: 8822350
    Abstract: An oxide film is formed, having a specific film thickness on a substrate by alternately repeating: forming a specific element-containing layer on the substrate by supplying a source gas containing a specific element, to the substrate housed in a processing chamber and heated to a first temperature; and changing the specific element-containing layer formed on the substrate, to an oxide layer by supplying a reactive species containing oxygen to the substrate heated to the first temperature in the processing chamber under a pressure of less than atmospheric pressure, the reactive species being generated by causing a reaction between an oxygen-containing gas and a hydrogen-containing gas in a pre-reaction chamber under a pressure of less than atmospheric pressure and heated to a second temperature higher than the first temperature.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: September 2, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Kazuhiro Yuasa, Ryuji Yamamoto
  • Patent number: 8796142
    Abstract: A tantalum nitride film rich in tantalum atoms is formed by simultaneously introducing a raw gas consisting of a coordination compound of elemental tantalum (Ta) having a coordinated ligand of formula: N?(R, R?) (wherein, R and R? each represents an alkyl group having 1 to 6 carbon atoms) and NH3 gas into a film-forming chamber; reacting the raw gas with the NH3 gas; forming a reduced compound having Ta—NH3 on a substrate; and introducing a hydrogen atom-containing gas into the chamber to form a tantalum nitride film rich in tantalum atoms. The resulting tantalum nitride film has a low resistance, low contents of C and N atoms, and a high compositional ratio: Ta/N, show sufficiently high adherence to Cu film and can thus be useful as a barrier film. Moreover, tantalum particles are implanted in the resulting film according to the sputtering technique to further enrich the film with tantalum.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: August 5, 2014
    Assignee: Ulvac, Inc.
    Inventors: Narishi Gonohe, Satoru Toyoda, Harunori Ushikawa, Tomoyasu Kondo, Kyuzo Nakamura
  • Patent number: 8791011
    Abstract: In a process, an opening is formed to extend from a front surface of a semiconductor substrate through a part of the semiconductor substrate. A metal seed layer is formed on a sidewall of the opening. A block layer is formed on only a portion of the metal seed layer. A metal layer is formed on the block layer and the metal seed layer to fill the opening.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: July 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Weng-Jin Wu, Shau-Lin Shue
  • Patent number: 8741712
    Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high-k phase of a subsequently deposited dielectric layer. The high-k dielectric layer includes a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: June 3, 2014
    Assignees: Intermolecular, Inc., Elpidia Memory, Inc.
    Inventors: Tony P. Chiang, Wim Y. Deweerd, Sandra G Malhotra
  • Patent number: 8736054
    Abstract: A wiring structure for a semiconductor device includes a multilayer metallization having a total thickness of at least 5 ?m and an interlayer disposed in the multilayer metallization with a first side of the interlayer adjoining one layer of the multilayer metallization and a second opposing side of the interlayer adjoining a different layer of the multilayer metallization. The interlayer includes at least one of W, WTi, Ta, TaN, TiW, and TiN or other suitable compound metal or a metal silicide such as WSi, MoSi, TiSi, and TaSi.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: May 27, 2014
    Assignee: Infineon Technologies AG
    Inventors: Manfred Schneegans, Jürgen Förster
  • Patent number: 8697565
    Abstract: A method, and an apparatus formed thereby, to construct shallow recessed wells on top of exposed conductive vias on the surface of a semiconductor. The shallow recessed wells are subsequently filled with a conductive cap layer, such as a tantalum nitride (TaN) layer, to prevent or reduce oxidation which may otherwise occur naturally when exposed to air, or possibly occur during an under-bump metallization process.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: April 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lin-Ya Huang, Chi-Sheng Juan, Chien-Lin Tseng
  • Patent number: 8697571
    Abstract: A structure includes a semiconductor device formed in a substrate; an insulator adjacent to the semiconductor device; an electrical contact electrically coupled to the semiconductor device, wherein the electrical contact includes tungsten; and an electrical connector coupled to the electrical contact, wherein the electrical connector includes aluminum. A surface of the insulator and a surface of the electrical contact form a substantially even surface.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: April 15, 2014
    Assignee: Vishay-Siliconix
    Inventors: Ronald Wong, Jason Qi, Kyle Terrill, Kuo-In Chen
  • Patent number: 8696921
    Abstract: In a method of manufacturing a semiconductor device, a substrate is loaded to a process chamber having, unit process sections in which unit processes are performed, respectively. The unit processes are performed on the substrate independently from one another at the unit process sections under a respective process pressure. The substrate sequentially undergoes the unit processes at the respective unit process section of the process chamber. Cleaning processes are individually performed to the unit process sections, respectively, when the substrate is transferred from each of the unit process sections and no substrate is positioned at the unit process sections. Accordingly, the process defects of the process units may be sufficiently prevented and the operation period of the manufacturing apparatus is sufficiently elongated.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Ho Park, Gil-Heyun Choi, Byung-Lyul Park, Jong-Myeong Lee, Zung-Sun Choi, Hye-Kyung Jung
  • Patent number: 8698313
    Abstract: A nonvolatile semiconductor memory apparatus according to an embodiment includes: a semiconductor layer; a first insulating film formed on the semiconductor layer, the first insulating film being a single-layer film containing silicon oxide or silicon oxynitride; a charge trapping film formed on the first insulating film; a second insulating film formed on the charge trapping film; and a control gate electrode formed on the second insulating film. A metal oxide exists in an interface between the first insulating film and the charge trapping film, the metal oxide comprises material which is selected from the group of Al2O3, HfO2, ZrO2, TiO2, and MgO, the material is stoichiometric composition, and the charge trapping film includes material different from the material of the metal oxide.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: April 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Izumi Hirano, Shosuke Fujii, Yuichiro Mitani, Naoki Yasuda
  • Patent number: 8691691
    Abstract: The present invention includes embodiments of a processing method, and resulting structure, for building a chip having a TSV pillar which can be used as an interconnecting structure. The process includes the deposition of a dual diffusion barrier between the TSV and the substrate the TSV is embedded within. The TSV is then exposed from the back side of the substrate so that at least a portion of the TSV protrudes from the substrate and can be used as a contact for connecting the chip to another surface. The resulting TSV is rigid, highly conductive, can be placed in a tightly pitched grid of contacts, and reduces effects of CTE mismatch.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: April 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Troy L. Graves-Abe, William F. Landers, Kevin S. Petrarca, Richard P. Volant
  • Patent number: 8685851
    Abstract: A manufacturing method of a MOS device with memory function is provided, which includes: providing a semiconductor substrate, a surface of the semiconductor substrate being covered by a first dielectric layer, a metal interconnect structure being formed in the first dielectric layer; forming a second dielectric layer overlying a surface of the first dielectric layer and the metal interconnect structure; forming an opening in the second dielectric layer, a bottom of the opening revealing the metal interconnect structure; forming an alloy layer at the bottom of the opening, material of the alloy layer containing copper and other metal; and performing a thermal treatment to the alloy layer and the metal interconnect structure to form, on the surface of the metal interconnect structure, a compound layer containing oxygen element. The compound layer containing oxygen element and the MOS device formed in the semiconductor substrate constitute a MOS device with memory function.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: April 1, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Chao Zhao, Wenwu Wang
  • Patent number: 8652904
    Abstract: A method of manufacturing a semiconductor device is presented. The device has: a gate terminal formed from polysilicon and covered by an insulation layer; and a plug extending through an insulation layer to provide an electrical connection to the gate trench. A metal layer is deposited to cover at least a portion of the insulation layer. The metal layer is then etched to remove the metal layer from above the plug.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: February 18, 2014
    Assignee: NXP, B.V.
    Inventors: Philip Rutter, Christopher Martin Rogers
  • Patent number: 8642468
    Abstract: Embodiments of the invention generally provide methods for depositing metal-containing materials and compositions thereof. The methods include deposition processes that form metal, metal carbide, metal silicide, metal nitride, and metal carbide derivatives by a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: February 4, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Seshadri Ganguli, Srinivas Gandikota, Yu Lei, Xinliang Lu, Sang Ho Yu, Hoon Kim, Paul F. Ma, Mei Chang, Maitreyee Mahajani, Patricia M. Liu
  • Patent number: 8633101
    Abstract: A manufacturing method of a semiconductor device including an electrode having low contact resistivity to a nitride semiconductor is provided. The manufacturing method includes a carbon containing layer forming step of forming a carbon containing layer containing carbon on a nitride semiconductor layer, and a titanium containing layer forming step of forming a titanium containing layer containing titanium on the carbon containing layer. A complete solid solution Ti (C, N) layer of TiN and TiC is formed between the titanium containing layer and the nitride semiconductor layer. As a result, the titanium containing layer comes to be in ohmic contact with the nitride semiconductor layer throughout the border therebetween.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: January 21, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Masahiro Sugimoto, Akinori Seki, Akira Kawahashi, Yasuo Takahashi, Masakatsu Maeda
  • Patent number: 8623759
    Abstract: In a method for manufacturing a semiconductor device, a first Ti film, a titanium nitride (TiN) film, a second Ti film, a first aluminum (Al) film and a second Al film are formed sequentially in a contact hole formed in a second interlayer insulating film and on a Cu wire. The first titanium (Ti) film is formed so that a ratio of a thickness of a first portion of the first Ti film on a bottom face of the contact hole to a thickness of a second portion of the first Ti film on the second interlayer insulating film becomes equal to or smaller than 5/100. Moreover, the second Al film is formed using an aluminum reflow method, in which the second Ti film and the first Al film are alloyed with each other to form an Al—Ti alloy film.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: January 7, 2014
    Inventor: Takashi Kansaku
  • Patent number: 8624397
    Abstract: This wiring layer structure includes: an underlying substrate of a semiconductor substrate or a glass substrate; an oxygen-containing Cu layer or an oxygen-containing Cu alloy layer which is formed on the underlying substrate; an oxide layer containing at least one of Al, Zr, and Ti which is formed on the oxygen-containing Cu layer or the oxygen-containing Cu alloy layer; and a Cu alloy layer containing at least one of Al, Zr, and Ti which is formed on the oxide layer.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: January 7, 2014
    Assignees: Mitsubishi Materials Corporation, Ulvac, Inc.
    Inventors: Kazunari Maki, Kenichi Yaguchi, Yosuke Nakasato
  • Publication number: 20140004679
    Abstract: A method for fabricating a semiconductor device includes forming a metal layer over a substrate, forming a capping layer over the metal layer, and densifying the metal layer through a heat treatment.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 2, 2014
    Inventors: Beom-Yong KIM, Yun-Hyuck Ji, Seung-Mi Lee