Having Refractory Group Metal (i.e., Titanium (ti), Zirconium (zr), Hafnium (hf), Vanadium (v), Niobium (nb), Tantalum (ta), Chromium (cr), Molybdenum (mo), Tungsten (w), Or Alloy Thereof) Patents (Class 438/648)
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Patent number: 7745329Abstract: In one embodiment, a method for forming a tungsten barrier material on a substrate is provided which includes depositing a tungsten layer on a substrate during a vapor deposition process and exposing the substrate sequentially to a tungsten precursor and a nitrogen precursor to form a tungsten nitride layer on the tungsten layer. Some examples provide that the tungsten layer may be deposited by sequentially exposing the substrate to the tungsten precursor and a reducing gas (e.g., diborane or silane) during an atomic layer deposition process. The tungsten layer may have a thickness of about 50 ? or less and tungsten nitride layer may have an electrical resistivity of about 380 ??-cm or less. Other examples provide that a tungsten bulk layer may be deposited on the tungsten nitride layer by a chemical vapor deposition process.Type: GrantFiled: August 20, 2008Date of Patent: June 29, 2010Assignee: Applied Materials, Inc.Inventors: Shulin Wang, Ulrich Kroemer, Lee Luo, Aihua Chen, Ming Li
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Patent number: 7736984Abstract: In one embodiment, silicide layers are formed on two oppositely doped adjacent semiconductor regions. A conductor material is formed electrically contacting both of the two silicides.Type: GrantFiled: September 23, 2005Date of Patent: June 15, 2010Assignee: Semiconductor Components Industries, LLCInventors: Gordon M. Grivna, Prasad Venkatraman
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Patent number: 7732924Abstract: Semiconductor wiring structures including a dielectric layer having a metal wiring line therein, a via extending downwardly from the metal wiring line, a metal cap layer over the metal wiring line, and a local dielectric cap positioned within a portion of the metal cap layer and in contact with the metal wiring line and a related method are disclosed. The local dielectric cap represents an intentionally created weak point in the metal wiring line of a dual-damascene interconnect, which induces electromigration (EM) voiding in the line, rather than at the bottom of a via extending downwardly from the metal wiring line. Since the critical void size in line fails, especially with metal cap layer (liner) redundancy, is much larger than that in via fails, the EM lifetime can be significantly increased.Type: GrantFiled: June 12, 2007Date of Patent: June 8, 2010Assignee: International Business Machines CorporationInventors: Kaushik Chanda, Ronald G. Filippi, Ping-Chuan Wang, Chih-Chao Yang
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Patent number: 7709377Abstract: A thin film including multi components and a method of forming the thin film are provided, wherein a method according to an embodiment of the present invention, a substrate is loaded into a reaction chamber. A unit material layer is formed on the substrate. The unit material layer may be formed of a mosaic atomic layer composed of two kinds of precursors containing components constituting the thin film. The inside of the reaction chamber is purged, and the MAL is chemically changed. The method of forming the thin film of the present invention requires fewer steps than a conventional method while retaining the advantages of the conventional method, thereby allowing a superior thin film yield in the present invention than previously obtainable.Type: GrantFiled: July 8, 2005Date of Patent: May 4, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-hyun Lee, Dae-sig Kim, Yo-sep Min, Young-jin Cho
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Patent number: 7709376Abstract: A method for fabricating a semiconductor device includes forming a dielectric film on a semiconductor substrate; forming an opening in the dielectric film; forming a refractory metal film in the opening; performing a nitriding process to the refractory metal film; removing a nitride of the refractory metal film formed on a side wall of the opening; and depositing tungsten (W) in the opening from which the nitride is removed.Type: GrantFiled: July 17, 2008Date of Patent: May 4, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hideto Matsuyama, Fumio Hoshi
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Patent number: 7709368Abstract: A method for easily manufacturing a semiconductor device in which variation in thickness or disconnection of a source electrode or a drain electrode is prevented is proposed A semiconductor device includes a semiconductor layer formed over an insulating substrate; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; an opening which reaches the semiconductor layer and is formed at least in the first insulating layer and the second insulating layer; and a step portion formed at a side surface of the second insulating layer in the opening.Type: GrantFiled: March 12, 2008Date of Patent: May 4, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shinya Sasagawa
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Publication number: 20100105169Abstract: A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another.Type: ApplicationFiled: August 18, 2009Publication date: April 29, 2010Inventors: Ho-jin Lee, Hyun-soo Chung, Chang-seong Jeon, Sang-sick Park, Jae-hyun Phee
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Patent number: 7704885Abstract: A method for fabricating a semiconductor device is provided. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a first insulating layer, a first conductive layer and a chemical mechanical polishing (CMP) stop layer over the semiconductor substrate in sequence; forming openings in the chemical mechanical polishing (CMP) stop layer and the underlying first conductive layer to expose the first insulating layer, thereby leaving a patterned chemical mechanical polishing (CMP) stop layer and a patterned first conductive layer; forming a second insulating layer on the patterned chemical mechanical polishing (CMP) stop layer, filling in the openings; performing a planarization process to remove a portion of the second insulating layer until the patterned chemical mechanical polishing (CMP) stop layer is exposed, thereby leaving a remaining second insulating layer in the openings; removing the patterned chemical mechanical polishing (CMP) stop layer.Type: GrantFiled: May 24, 2007Date of Patent: April 27, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kern-Huat Ang, Po-Jen Wang
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Patent number: 7704869Abstract: A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.Type: GrantFiled: September 11, 2007Date of Patent: April 27, 2010Assignee: International Business Machines CorporationInventors: Douglas C. La Tulipe, Jr., Mark Todhunter Robson
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Publication number: 20100096756Abstract: A semiconductor device has a multilayer interconnection including a copper interconnection film formed in a predetermined area within an insulating film, a liner film, and a high-melting-point metal film. The copper interconnection film is polycrystalline, and crystal grains occupying 40% or more of an area of a unit interconnection surface among crystal grains forming the polycrystal are oriented to (111) in a substrate thickness direction. The copper interconnection film has crystal conformity with the noble metal liner film. In a case where the high-melting-point metal film is formed of Ti and the noble metal liner film is a Ru film, the high-melting-point metal of Ti dissolves into Ru in a solid state to form the noble metal liner. Thus, a copper interconnection is formed with both of Cu diffusion barrier characteristics and Cu crystal conformity.Type: ApplicationFiled: January 8, 2008Publication date: April 22, 2010Inventors: Masayoshi Tagami, Yoshihiro Hayashi, Munehiro Tada, Takahiro Onodera, Naoya Furutake, Makoto Ueki, Mari Amano
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Patent number: 7700480Abstract: Some embodiments include methods of titanium deposition in which a silicon-containing surface and an electrically insulative surface are both exposed to titanium-containing material, and in which such exposure forms titanium silicide from the silicon-containing surface while not depositing titanium onto the electrically insulative surface. The embodiments may include atomic layer deposition processes, and may include a hydrogen pre-treatment of the silicon-containing surfaces to activate the surfaces for reaction with the titanium-containing material. Some embodiments include methods of titanium deposition in which a semiconductor material surface and an electrically insulative surface are both exposed to titanium-containing material, and in which a titanium-containing film is uniformly deposited across both surfaces.Type: GrantFiled: April 27, 2007Date of Patent: April 20, 2010Assignee: Micron Technology, Inc.Inventors: Joel A. Drewes, Cem Basceri, Demetrius Sarigiannis
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Publication number: 20100087060Abstract: The present invention relates to methods of forming semiconductor structures. The methods may include disposing electrically conductive material within an opening in a first dielectric material, passivating an upper surface of the electrically conductive material and introducing materials to form an interlayer dielectric upon the passivated upper surface. The present invention also includes methods of passivating surfaces of a semiconductor structure with a nitrogen-containing species.Type: ApplicationFiled: December 7, 2009Publication date: April 8, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Zhiping Yin, Mark E. Jost
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Publication number: 20100084766Abstract: Semiconductor interconnect structures including a surface-repair material, e.g., a noble metal or noble metal alloy, that fills hollow-metal related defects located within a conductive material are provided. The filling of the hollow-metal related defects with the surface repair material improves the electromigration (EM) reliability of the structure as well as decreasing in-line defect related yield loss.Type: ApplicationFiled: October 8, 2008Publication date: April 8, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chih-Chao Yang, Conal E. Murray
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Patent number: 7674710Abstract: A method for integrating a metal-containing film in a semiconductor device, for example a gate stack. In one embodiment, the method includes providing a substrate in a process chamber, depositing the tungsten-containing film on the substrate at a first substrate temperature by exposing the substrate to a deposition gas containing a tungsten carbonyl precursor, heat treating the tungsten-containing film at a second substrate temperature greater than the first substrate temperature to remove carbon monoxide gas from the tungsten-containing film, and forming a barrier layer on the heat treated tungsten-containing film. Examples of tungsten-containing films include W, WN, WSi, and WC. Additional embodiments include depositing metal-containing films containing Ni, Mo, Co, Rh, Re, Cr, or Ru from the corresponding metal carbonyl precursors.Type: GrantFiled: November 20, 2006Date of Patent: March 9, 2010Assignee: Tokyo Electron LimitedInventors: Shigeo Ashigaki, Hideaki Yamasaki, Tomoyuki Sakoda, Mikio Suzuki, Genji Nakamura, Gert Leusink
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Publication number: 20100052176Abstract: A semiconductor device includes a first wiring extending in a first direction and a second wiring extending in a second direction which crosses the first direction and being disposed with a space interposed between the first wiring and the second wiring, and including a tantalum layer, a tantalum nitride layer formed over the tantalum layer, and a metal layer formed over the tantalum nitride layer.Type: ApplicationFiled: August 13, 2009Publication date: March 4, 2010Applicant: FUJITSU LIMITEDInventors: Yoichi Kamada, Naoya Okamoto
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Patent number: 7670944Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Trenches and contact vias are formed in insulating layers. The trenches and vias are exposed to alternating chemistries to form monolayers of a desired lining material. Exemplary process flows include alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with nitrogen. Near perfect step coverage allows minimal thickness for a diffusion barrier function, thereby maximizing the volume of a subsequent filling metal for any given trench and via dimensions.Type: GrantFiled: August 28, 2006Date of Patent: March 2, 2010Assignee: ASM International N.V.Inventors: Ivo Raaijmakers, Suvi P. Haukka, Ville A. Saanila, Pekka J. Soininen, Kai-Erik Elers, Ernst H.A. Granneman
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Patent number: 7666785Abstract: A method for fabricating a semiconductor memory device includes forming a first layer, injecting a tungsten source gas and a silicon source gas simultaneously to form a tungsten silicide layer over the first layer, forming a tungsten nitride layer over the tungsten silicide layer without a post purge process of additionally supplying the silicon source gas, and forming a second layer over the tungsten nitride layer.Type: GrantFiled: June 30, 2008Date of Patent: February 23, 2010Assignee: Hynix Semiconductor Inc.Inventors: Min-Gyu Sung, Yong-Soo Kim, Kwan-Yong Lim
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Publication number: 20100035427Abstract: Improved methods for depositing low resistivity tungsten films are provided. The methods involve depositing a tungsten nucleation layer on a substrate and then depositing a tungsten bulk layer over the tungsten nucleation layer to form the tungsten film. The methods provide precise control of the nucleation layer thickness and improved step coverage. According to various embodiments, the methods involve controlling thickness and/or improving step coverage by exposing the substrate to pulse nucleation layer (PNL) cycles at low temperature. Also in some embodiments, the methods may improve resistivity by using a high temperature PNL cycle of a boron-containing species and a tungsten-containing precursor to finish forming the tungsten nucleation layer.Type: ApplicationFiled: August 10, 2009Publication date: February 11, 2010Applicant: Novellus Systems, Inc.Inventors: Lana Hiului Chan, Panya Wongsenakhum, Joshua Collins
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Patent number: 7655567Abstract: The methods described herein relate to deposition of low resistivity, highly conformal tungsten nucleation layers. These layers serve as a seed layers for the deposition of a tungsten bulk layer. The methods are particularly useful for tungsten plug fill in which tungsten is deposited in high aspect ratio features. The methods involve depositing a nucleation layer by a combined PNL and CVD process. The substrate is first exposed to one or more cycles of sequential pulses of a reducing agent and a tungsten precursor in a PNL process. The nucleation layer is then completed by simultaneous exposure of the substrate to a reducing agent and tungsten precursor in a chemical vapor deposition process. In certain embodiments, the process is performed without the use of a borane as a reducing agent.Type: GrantFiled: July 24, 2007Date of Patent: February 2, 2010Assignee: Novellus Systems, Inc.Inventors: Juwen Gao, Lana Hiului Chan, Panya Wongsenakhum
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Patent number: 7655562Abstract: A method of manufacturing a semiconductor device is disclosed. In the method of manufacturing the semiconductor device, a first insulating layer is formed on a semiconductor substrate. A metal line layer and an etch-stop layer are formed over the first insulating layer. The etch-stop layer and the metal line layer are patterned to form a metal line. A second insulating layer is formed on the first insulating layer and the etch-stop layer. A first etch process for etching part of the second insulating layer is performed by using a first etch gas so that the etch-stop layer is exposed. A second etch process for removing the etch-stop layer is performed by using a second etch gas so that the metal line is exposed.Type: GrantFiled: May 4, 2007Date of Patent: February 2, 2010Assignee: Hynix Semiconductor Inc.Inventor: Min Chul Gil
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Patent number: 7642187Abstract: A method of forming a wiring for a semiconductor memory device includes obtaining a semiconductor substrate, depositing at least one conductive layer on the semiconductor substrate under controlled conditions, such as substrate temperature and atmosphere temperature, to provide a conductive layer exhibiting a reduced surface roughness as compared to a comparable conductive layer deposited under uncontrolled conditions, and patterning the conductive layer to form a wiring.Type: GrantFiled: September 28, 2007Date of Patent: January 5, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Hyun Lee, Min-Soo Kim, Tae-Hoon Kim
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Patent number: 7618855Abstract: A technology capable of improving the yield in a manufacturing process of a MISFET with a gate electrode formed of a metal silicide film. A gate insulating film is formed on a semiconductor substrate and silicon gate electrodes formed of a polysilicon film are formed on the gate insulating film. Then, after a silicon oxide film is formed so as to cover the silicon gate electrodes, a surface of the silicon oxide film is polished by CMP, thereby exposing the surface of the silicon gate electrodes. Subsequently, a patterned insulating film is formed on the silicon oxide film. Thereafter, an adhesion film is formed on the silicon oxide film and the insulating film. Then, a nickel film is formed on the adhesion film. Thereafter, a silicide reaction is caused to occur between the silicon gate electrode and the nickel film via the adhesion film.Type: GrantFiled: October 2, 2006Date of Patent: November 17, 2009Assignee: Renesas Technology Corp.Inventors: Masaru Kadoshima, Toshihide Nabatame
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Publication number: 20090278260Abstract: An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, a design structure of the IC interconnect and a method of manufacture of the IC interconnect is provided. The structure has electro-migration immunity and redundancy of design, which includes a plurality of wires laid out in parallel and each of which are coated with a liner material. Two adjacent of the wires are physically contacted to each other.Type: ApplicationFiled: May 6, 2008Publication date: November 12, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Louis L. Hsu, Conal E. Murray, Ping-Chuan Wang, Chih-Chao Yang
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Patent number: 7601637Abstract: Apparatus and methods of fabricating an atomic layer deposited tantalum containing adhesion layer within at least one dielectric material in the formation of a metal, wherein the atomic layer deposition tantalum containing adhesion layer is sufficiently thin to minimize contact resistance and maximize the total cross-sectional area of metal, including but not limited to tungsten, within the contact.Type: GrantFiled: December 24, 2008Date of Patent: October 13, 2009Assignee: Intel CorporationInventors: Steven W. Johnston, Kerry Spurgin, Brennan L. Peterson
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Patent number: 7598170Abstract: Methods of controllably producing conductive tantalum nitride films are provided. The methods comprise contacting a substrate in a reaction space with alternating and sequential pulses of a tantalum source material, plasma-excited species of hydrogen and nitrogen source material. The plasma-excited species of hydrogen reduce the oxidation state of tantalum, thereby forming a substantially conductive tantalum nitride film over the substrate. In some embodiments, the plasma-excited species of hydrogen react with and removes halide residues in a deposited metallic film.Type: GrantFiled: January 26, 2007Date of Patent: October 6, 2009Assignee: ASM America, Inc.Inventor: Kai-Erik Elers
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Patent number: 7589017Abstract: Improved methods for depositing low resistivity tungsten films are provided. The methods involve depositing a tungsten nucleation layer on a substrate and then depositing a tungsten bulk layer over the tungsten nucleation layer to form the tungsten film. The methods provide precise control of the nucleation layer thickness and improved step coverage. According to various embodiments, the methods involve controlling thickness and/or improving step coverage by exposing the substrate to pulse nucleation layer (PNL) cycles at low temperature. Also in some embodiments, the methods may improve resistivity by using a high temperature PNL cycle of a boron-containing species and a tungsten-containing precursor to finish forming the tungsten nucleation layer.Type: GrantFiled: November 1, 2005Date of Patent: September 15, 2009Assignee: Novellus Systems, Inc.Inventors: Lana Hiului Chan, Panya Wongsenakhum, Joshua Collins
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Patent number: 7585762Abstract: Embodiments of the invention generally provide methods for depositing and compositions of tantalum carbide nitride materials. The methods include deposition processes that form predetermined compositions of the tantalum carbide nitride material by controlling the deposition temperature and the flow rate of a nitrogen-containing gas during a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. In one embodiment, a method for forming a tantalum-containing material on a substrate is provided which includes heating the substrate to a temperature within a process chamber, and exposing the substrate to a nitrogen-containing gas and a process gas containing a tantalum precursor gas while depositing a tantalum carbide nitride material on the substrate.Type: GrantFiled: September 25, 2007Date of Patent: September 8, 2009Assignee: Applied Materials, Inc.Inventors: Kavita Shah, Haichun Yang, Schubert S. Chu
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Patent number: 7581314Abstract: A semiconductor micro-electromechanical system (MEMS) switch provided with noble metal contacts that act as an oxygen barrier to copper electrodes is described. The MEMS switch is fully integrated into a CMOS semiconductor fabrication line. The integration techniques, materials and processes are fully compatible with copper chip metallization processes and are typically, a low cost and a low temperature process (below 400° C.). The MEMS switch includes: a movable beam within a cavity, the movable beam being anchored to a wall of the cavity at one or both ends of the beam; a first electrode embedded in the movable beam; and a second electrode embedded in an wall of the cavity and facing the first electrode, wherein the first and second electrodes are respectively capped by the noble metal contact.Type: GrantFiled: February 21, 2006Date of Patent: September 1, 2009Assignee: International Business Machines CorporationInventors: Hariklia Deligianni, Panayotis Andricacos, L. Paivikki Buchwalter, John M. Cotte, Christopher Jahnes, Mahadevaiyer Krishnan, John H. Magerlein, Kenneth Stein, Richard P. Volant, James A. Tornello, Jennifer Lund
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Patent number: 7575998Abstract: Embodiments relate to a method for forming a wiring in a semiconductor device, that may include laminating a conductive layer for wiring formation on a semiconductor substrate, forming a photoresist layer pattern on the conductive layer, performing primary dry etching for the conductive layer after employing the photoresist layer pattern as a mask, thereby forming a wiring pattern, partially removing the photoresist layer pattern through secondary dry etching, thereby forming a passivation layer on a surface of the wiring pattern, performing tertiary dry etching for the wiring pattern and a diffusion barrier after employing the photoresist layer pattern as a mask, thereby forming a metal wiring, and removing the photoresist layer pattern.Type: GrantFiled: December 22, 2006Date of Patent: August 18, 2009Assignee: Dongbu HiTek Co., Ltd.Inventor: Jong Soon Lee
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Publication number: 20090200678Abstract: A device comprises a multi-layered thin film having excellent adhesion due to the method of fabricating the same. More particularly, the device includes a multi-layered thin film consisting of a tantalum nitride layer, a tantalum layer formed on the tantalum nitride layer, and a gold thin film formed on the tantalum layer.Type: ApplicationFiled: April 14, 2009Publication date: August 13, 2009Inventors: Ju-Yong Kim, Ho-Jin Kweon, Jae-Jeong Kim, Jin-Goo Ahn, Oh-Joong Kwon
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Patent number: 7566653Abstract: In general, the present invention provides an interconnect structure and method for forming the same. This present invention discloses an interconnect structure includes a Cu seeding layer embedded between a diffusion barrier layer and a grain growth promotion layer. Specifically, under the present invention, a diffusion barrier layer is formed on a patterned inter-level dielectric layer. A (Cu) seeding layer is then formed on the diffusion barrier layer, and a grain growth promotion layer is formed on the seeding layer. Once the grain growth promotion layer is formed, post-processing steps (e.g., electroplating and chemical-mechanical polishing) are performed.Type: GrantFiled: July 31, 2007Date of Patent: July 28, 2009Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Daniel C. Edelstein
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Publication number: 20090184425Abstract: The conductive line structure of a semiconductor device including a base; at least one patterned conductive layer formed over the base; a conductive line formed over the at least one patterned conductive layer; a protection layer that encompasses the top surface and sidewall of the conductive line to prevent undercut generated by etching. The structure further comprises an underlying layer under the conductive line. The underlying layer includes Ni, Cu or Pt. The conductive line includes gold or copper. The at least one patterned conductive layer includes at least Ti/Cu. The protection layer includes electro-less plating Sn, Au, Ag or Ni.Type: ApplicationFiled: January 17, 2008Publication date: July 23, 2009Inventors: Yu-Shan Hu, Ming-Chih Chen, Dyi-Chung Hu
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Patent number: 7560393Abstract: A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum (silicon) nitride barrier layer, on a substrate by using a vapor deposition process with a refractory metal precursor compound, a disilazane, and an optional silicon precursor compound.Type: GrantFiled: February 28, 2007Date of Patent: July 14, 2009Assignee: Micron Technology, Inc.Inventor: Brian A. Vaartstra
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Publication number: 20090166874Abstract: A semiconductor device and manufacturing method thereof are provided. The semiconductor device can include an interlayer dielectric layer on a substrate, a metal layer on the interlayer dielectric layer, and an impure anti-reflection film on the metal layer. The impure anti-reflection film can be formed through an in situ process.Type: ApplicationFiled: November 14, 2008Publication date: July 2, 2009Inventor: Jang Hyeon Seok
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Publication number: 20090163022Abstract: Multi-layered wiring for a larger flat panel display is formed by depositing molybdenum on a substrate in presence of a precursor gas containing at least one oxygen, nitrogen and carbon to form a molybdenum layer. An aluminum layer is deposited on the molybdenum layer. Another metal layer may be formed on the aluminum layer. The molybdenum layer has a face-centered cubic (FCC) lattice structure with a preferred orientation of (111).Type: ApplicationFiled: February 12, 2009Publication date: June 25, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Je-Hun LEE, Jae-Kyeong LEE, Chang-Oh JEONG, Beom-Seok CHO
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Patent number: 7550385Abstract: A method for forming a metal carbide layer begins with providing a substrate, an organometallic precursor material, at least one doping agent such as nitrogen, and a plasma such as a hydrogen plasma. The substrate is placed within a reaction chamber; and heated. A process cycle is then performed, where the process cycle includes pulsing the organometallic precursor material into the reaction chamber, pulsing the doping agent into the reaction chamber, and pulsing the plasma into the reaction chamber, such that the organometallic precursor material, the doping agent, and the plasma react at the surface of the substrate to form a metal carbide layer. The process cycles can be repeated and varied to form a graded metal carbide layer.Type: GrantFiled: September 30, 2005Date of Patent: June 23, 2009Assignee: Intel CorporationInventors: Adrien R. Lavoie, Valery M. Dubin, Juan E. Dominguez, Kevin P. O'Brien, Steven W. Johnston, John D. Peck, David M. Thompson, David W. Peters
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Publication number: 20090146143Abstract: A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.Type: ApplicationFiled: December 10, 2007Publication date: June 11, 2009Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, ADVANCED MICRO DEVICES, INC. (AMD)Inventors: Tibor Bolom, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Paul S. McLaughlin, Sujatha Sankaran, Andrew H. Simon, Theodorus E. Standaert, James Werking
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Patent number: 7538045Abstract: The present invention relates to a process for the deposition of protective coatings on complex shaped Si-based substrates which are used in articles and structures subjected to high temperature, aqueous environments comprises a non-line-of-sightprocess, particularly, electrophoretic deposition (EPD) process.Type: GrantFiled: February 10, 2006Date of Patent: May 26, 2009Assignee: United Technologies CorporationInventors: Tania Bhatia, Neil Baldwin, John E. Holowczak
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Patent number: 7531902Abstract: A multi-layered metal line of a semiconductor device has a lower metal line and an upper metal line. The upper metal line includes a diffusion barrier, which is made of a stack of a first WNx layer, a WCyNx layer and a second WNx layer.Type: GrantFiled: May 31, 2007Date of Patent: May 12, 2009Assignee: Hynix Semiconductor Inc.Inventors: Jeong Tae Kim, Baek Mann Kim, Soo Hyun Kim, Young Jin Lee, Dong Ha Jung
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Patent number: 7528066Abstract: An interconnect structure including a gouging feature at the bottom of one of the via openings and a method of forming the same are provided. In accordance with the present invention, the method of forming the interconnect structure does not disrupt the coverage of the deposited diffusion barrier in the overlying line opening, nor does it introduce damages caused by Ar sputtering into the dielectric material including the via and line openings. In accordance with the present invention, such an interconnect structure contains a diffusion barrier layer only within the via opening, but not in the overlying line opening. This feature enhances both mechanical strength and diffusion property around the via opening areas without decreasing volume fraction of conductor inside the line openings.Type: GrantFiled: March 1, 2006Date of Patent: May 5, 2009Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Terry A. Spooner, Oscar van der Straten
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Patent number: 7524756Abstract: A contact structure and a method of forming thereof for semiconductor devices or assemblies are described. The method provides process steps to create a contact structure encompassed by a sacrificial contact medium having an opening therein that is lined with a conductive spacer liner that effectively prevents the contact structure from being damaged during removal of the surrounding sacrificial contact medium material. The sacrificial contact medium is then replaced with a non-boron doped dielectric material.Type: GrantFiled: July 28, 2006Date of Patent: April 28, 2009Assignee: Micron Technology, Inc.Inventors: Grant S. Huglin, Robert J. Burke, Sanh D. Tang
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Patent number: 7521346Abstract: A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 ? classical), which cannot be achieved using TaSiN.Type: GrantFiled: October 19, 2007Date of Patent: April 21, 2009Assignee: International Business Machines CorporationInventors: Alessandro C. Callegari, Martin M. Frank, Rajarao Jammy, Dianne L. Lacey, Fenton R. McFeely, Sufi Zafar
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Patent number: 7514360Abstract: This invention relates to a semiconductor device making use of a highly thermal robust metal electrode as gate material. In particular, the development of Hafnium Nitride as a metal gate electrode (or a part of the metal gate stack) is taught and its manufacturing steps of fabrication with different embodiments are shown.Type: GrantFiled: March 17, 2004Date of Patent: April 7, 2009Inventors: Hong Yu Yu, Ming-Fu Li, Dim-Lee Kwong, Lakshmi Kanta Bera
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Patent number: 7514354Abstract: Methods are provided for forming dual damascene interconnect structures using different conductor materials to fill via holes and line trenches. For example, a method for forming an interconnection structure includes depositing dielectric material on a semiconductor substrate and etching the dielectric material to form a dual damascene recess structure including a via hole and trench. A layer of first conductive material is then conformally deposited to fill the via hole with the first conductive material, and the layer of first conductive material is etched to remove the first conductive material from the trench and an upper region of the via hole below the trench. A layer of second conductive material is then deposited to fill the trench and upper region of the via hole with the second conductive material.Type: GrantFiled: December 30, 2005Date of Patent: April 7, 2009Assignee: Samsung Electronics Co., LtdInventors: Ki-Chul Park, Ja-Hum Ku, Seung-Man Choi
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Patent number: 7510967Abstract: The present invention relates to a method for manufacturing a semiconductor device, comprising: forming a metal interconnect on a substrate; forming a refractory metal layer containing titanium (Ti) or tantalum (Ta) on a surface of the metal interconnect; forming an insulating interlayer so as to cover the refractory metal layer; selectively etching the insulating interlayer with an etchant gas containing an organic fluoride to form a hole, in which the refractory metal layer is exposed; treating an interior of the hole with an organic chemical solution to remove fluorinated compounds of Ti or Ta while leaving fluorocarbons on the surface of the refractory metal layer, the fluorinated compounds of Ti or Ta and the fluorocarbons being created during the etching step and present in the interior of the hole; and performing plasma-treatment for the interior of said hole to remove the fluorocarbon.Type: GrantFiled: May 25, 2007Date of Patent: March 31, 2009Assignee: NEC Electronics CorporationInventor: Kousei Ushijima
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Patent number: 7510966Abstract: The invention includes an electrically conductive line, methods of forming electrically conductive lines, and methods of reducing titanium silicide agglomeration in the fabrication of titanium silicide over polysilicon transistor gate lines. In one implementation, a method of forming an electrically conductive line includes providing a silicon-comprising layer over a substrate. An electrically conductive layer is formed over the silicon-comprising layer. An MSixNy-comprising layer is formed over the electrically conductive layer, where “x” is from 0 to 3.0, “y” is from 0.5 to 10, and “M” is at least one of Ta, Hf, Mo, and W. An MSiz-comprising layer is formed over the MSixNy-comprising layer, where “z” is from 1 to 3.0. A TiSia-comprising layer is formed over the MSiz-comprising layer, where “a” is from 1 to 3.0.Type: GrantFiled: March 7, 2005Date of Patent: March 31, 2009Assignee: Micron Technology, Inc.Inventors: Qi Pan, Jiutao Li, Yongjun Jeff Hu, Allen McTeer
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Patent number: 7498179Abstract: The present invention relates to the field of a semiconductor device having a ferroelectric material capacitor and method of making the same. The semiconductor device includes a capacitor having a triple-level oxygen barrier layer pattern formed by an oxygen barrier metal layer, a material layer formed of a conductive solid solution by compounding the oxygen barrier metal layer and oxygen, and an oxygen barrier metal on an interlayer dielectric with a contact plug. The capacitor also has an electrode and a ferroelectric film electrically contacting to the oxygen barrier layer. Further, a wetting layer is formed between the oxygen barrier layer and the contact plug, and an iridium oxygen layer is formed between the oxygen barrier layer and a capacitor electrode.Type: GrantFiled: September 2, 2005Date of Patent: March 3, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Yoon-Jong Song
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Patent number: 7491641Abstract: This invention includes methods of forming conductive lines, and methods of forming conductive contacts adjacent conductive lines. In one implementation, a method of forming a conductive line includes forming a conductive line within an elongated trench within first insulative material over a semiconductive substrate. The conductive line is laterally spaced from opposing first insulative material sidewall surfaces of the trench. The conductive line includes a second conductive material received over a different first conductive material. The second conductive material is recessed relative to an elevationally outer surface of the first insulative material proximate the trench. A second insulative material different from the first insulative material is formed within the trench over a top surface of the conductive line and within laterally opposing spaces received between the first insulative material and the conductive line.Type: GrantFiled: April 27, 2006Date of Patent: February 17, 2009Assignee: Micron Technology, Inc.Inventors: Scott A. Southwick, Alex J. Schrinsky, Terrence B. McDaniel
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Publication number: 20090008777Abstract: An interconnecting structure for a semiconductor die assembly, comprising: a substrate with pre-formed wiring circuit formed therein; a die having contact pads on an active surface; an adhesive material formed over the substrate to adhere the die over the substrate, wherein the substrate includes a via through the substrate and the adhesive material; and conductive material refilled into the via to couple the contact pads of the die to the wiring circuit of the substrate.Type: ApplicationFiled: July 6, 2007Publication date: January 8, 2009Inventors: Diann-Fang Lin, Wen-Kun Yang
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Patent number: 7473633Abstract: Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing and etching a dielectric layer to form a cavity, growing substantially parallel carbon nanotubes on the catalyst in the cavity, and filling the remaining voids in the cavity with copper. The next conductive layer is then formed over the via hole.Type: GrantFiled: July 20, 2006Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Mark Charles Hakey, David Vaclav Horak, Charles William Koburger, III, Mark Eliot Masters, Peter H Mitchell, Stanislav Polonsky