Silicide Patents (Class 438/649)
  • Patent number: 9941129
    Abstract: A semiconductor device and a method for manufacturing the device. The method includes: depositing a first dielectric layer on a semiconductor device; forming a plurality of first trenches through the first dielectric layer; depositing an insulating fill in the plurality of first trenches; planarizing the plurality of first trenches; forming a first gate contact between the plurality of first trenches; depositing a first contact fill in the first gate contact; planarizing the first gate contact; depositing a second dielectric layer on the device; forming a plurality of second trenches through the first and second dielectric layers; depositing a conductive fill in the plurality of second trenches; planarizing the plurality of second trenches; forming a second gate contact where the second gate contact is in contact with the first gate contact; depositing a second contact fill in the second gate contact; and planarizing the second gate contact.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, Paul Chang, Michael A. Guillorn
  • Patent number: 9793216
    Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: October 17, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Joyeeta Nag, Jim Shih-Chun Liang, Domingo A. Ferrer Luppi, Atsushi Ogino, Andrew H. Simon, Michael P. Chudzik
  • Patent number: 9450073
    Abstract: By reconfiguring material in a recess formed in drain and source regions of SOI transistors, the depth of the recess may be increased down to the buried insulating layer prior to forming respective metal silicide regions, thereby reducing series resistance and enhancing the stress transfer when the corresponding transistor element is covered by a highly stressed dielectric material. The material redistribution may be accomplished on the basis of a high temperature hydrogen bake.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: September 20, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andy Wei, Thorsten Kammler, Roman Boschke, Casey Scott
  • Patent number: 9165788
    Abstract: The methods and apparatus disclosed herein concern a process that may be referred to as a “soft anneal.” A soft anneal provides various benefits. Fundamentally, it reduces the internal stress in one or more silicon layers of a work piece. Typically, though not necessarily, the internal stress is a compressive stress. A particularly beneficial application of a soft anneal is in reduction of internal stress in a stack containing two or more layers of silicon. Often, the internal stress of a layer or group of layers in a stack is manifest as wafer bow. The soft anneal process can be used to reduce compressive bow in stacks containing silicon. The soft anneal process may be performed without causing the silicon in the stack to become activated.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: October 20, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Keith Fox, Bart J. Van Schravendijk, Dong Niu, Lucas B. Henderson, Joseph L. Womack
  • Patent number: 9023728
    Abstract: According to one embodiment, a method of manufacturing a metal silicide layer, the method includes forming a metal layer including impurities on a silicon layer by a vapor deposition method using a gas of a metal and a gas of the impurities, and forming a metal silicide layer including the impurities by chemically reacting the metal layer with the silicon layer. A thickness and a composition of the metal silicide layer are controlled by an amount of the impurities in the metal layer.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Makoto Honda
  • Patent number: 8999855
    Abstract: According one embodiment, a method for manufacturing a semiconductor device is provided, which includes forming a pair of element isolation insulation films on a semiconductor substrate, forming a gate electrode structure on sides of the gate electrode structure, selectively removing oxide films that are formed on a top surface of the diffusion layer and a top surface of the gate electrode by placing the substrate in a gas atmosphere selected from the group consisting of F, Cl, Br, I, H, O, Ar, or N; and irradiating the semiconductor substrate with microwave radiation. The method also includes depositing a metal film on a top surface of the diffusion layer and a top surface of the gate electrode, and a silicide film is formed by heating the substrate.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: April 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Honda, Tomonori Aoyama
  • Patent number: 8946081
    Abstract: Embodiments of the invention include a method of cleaning a semiconductor substrate of a device structure and a method of forming a silicide layer on a semiconductor substrate of a device structure. Embodiments include steps of converting a top portion of the substrate into an oxide layer and removing the oxide layer to expose a contaminant-free surface of the substrate.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Ahmet Serkan Ozcan, Viraj Yashawant Sardesai, Cung Do Tran
  • Patent number: 8927422
    Abstract: A method for forming a raised silicide contact including depositing a layer of silicon at a bottom of a contract trench using a gas cluster implant technique which accelerates clusters of silicon atoms causing them to penetrate a surface oxide on a top surface of the silicide, a width of the silicide and the contact trench are substantially equal; heating the silicide including the silicon layer to a temperature from about 300° C. to about 950° C. in an inert atmosphere causing silicon from the layer of silicon to react with the remaining silicide partially formed in the silicon containing substrate; and forming a raised silicide from the layer of silicon, wherein the thickness of the raised silicide is greater than the thickness of the silicide and the raised silicide protrudes above a top surface of the silicon containing substrate.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Nathaniel Berliner, Christian Lavoie, Kam-Leung Lee, Ahmet Serkan Ozcan
  • Patent number: 8912059
    Abstract: Various embodiments disclosed include semiconductor structures and methods of forming such structures. In one embodiment, a method includes: providing a semiconductor structure including: a substrate; at least one gate structure overlying the substrate; and an interlayer dielectric overlying the substrate and the at least one gate structure; removing the ILD overlying the substrate to expose the substrate; forming a silicide layer over the substrate; forming a conductor over the silicide layer and the at least one gate structure; forming an opening in the conductor to expose a portion of a gate region of the at least one gate structure; and forming a dielectric in the opening in the conductor.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, David V. Horak, Edward J. Nowak
  • Patent number: 8883583
    Abstract: Semiconductor devices, transistors, and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a gate dielectric disposed over a workpiece, a gate disposed over the gate dielectric, and a spacer disposed over sidewalls of the gate and the gate dielectric. A source region is disposed proximate the spacer on a first side of the gate, and a drain region is disposed proximate the spacer on a second side of the gate. A metal layer is disposed over the source region and the drain region. The metal layer extends beneath the spacers by about 25% or greater than a width of the spacers.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Kun Huang, Shih-Che Lin, Hung-Chih Yu
  • Patent number: 8877583
    Abstract: In a method of forming an ohmic layer of a DRAM device, the metal silicide layer between the storage node contact plug and the lower electrode of a capacitor is formed as the ohmic layer by a first heat treatment under a first temperature and an instantaneous second heat treatment under a second temperature higher than the first temperature. Thus, the metal silicide layer has a thermo-stable crystal structure and little or no agglomeration occurs on the metal silicide layer in the high temperature process. Accordingly, the sheet resistance of the ohmic layer may not increase in spite of the subsequent high temperature process.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Bum Kim, Young-Pil Kim, Kwan-Heum Lee, Sun-Ghil Lee
  • Patent number: 8865594
    Abstract: The invention provides a method of forming a film stack on a substrate, comprising performing a silicon containing gas soak process to form a silicon containing layer over the substrate, reacting with the silicon containing layer to form a tungsten silicide layer on the substrate, depositing a tungsten nitride layer on the substrate, subjecting the substrate to a nitridation treatment using active nitrogen species from a remote plasma, and depositing a conductive bulk layer directly on the tungsten nitride layer.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: October 21, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Sang-Hyeob Lee, Sang Ho Yu, Kai Wu
  • Patent number: 8865556
    Abstract: Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX and at least one active area formed in the wafer; a gate stack over a portion of the at least one active area which serves as a channel of the device; source and drain regions of the device adjacent to the gate stack, wherein the source and drain regions of the device include a semiconductor material selected from: silicon and silicon germanium; and silicide contacts to the source and drain regions of the device, wherein an interface is present between the silicide contacts and the semiconductor material, and wherein the interface has an interface roughness of less than about 5 nanometers.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joseph S. Newbury, Kenneth Parker Rodbell, Zhen Zhang, Yu Zhu
  • Patent number: 8859408
    Abstract: Generally, the present disclosure is directed to methods of stabilizing metal silicide contact regions formed in a silicon-germanium active area of a semiconductor device, and devices comprising stabilized metal silicides. One illustrative method disclosed herein includes performing an activation anneal to activate dopants implanted in an active area of a semiconductor device, wherein the active area comprises germanium. Additionally, the method includes, among other things, performing an ion implantation process to implant ions into the active area after performing the activation anneal, forming a metal silicide contact region in the active area, and forming a conductive contact element to the metal silicide contact region.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: October 14, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Clemens Fitz, Tom Herrmann
  • Patent number: 8846527
    Abstract: A method is provided for fabricating an MOS transistor. The method includes providing a semiconductor substrate, and forming a gate structure having a gate dielectric layer and a gate metal layer on the semiconductor substrate. The method also includes forming offset sidewall spacers at both sides of the gate structure, and forming lightly doped regions in semiconductor substrate at both sides of the gate structure. Further, the method includes forming a first metal silicide region in each of the lightly doped regions, and forming main sidewall spacers at both sides of the gate structure. Further, the method includes forming heavily doped regions in semiconductor substrate at both sides of the gate structure and the main sidewall spacers, and forming a second metal silicide region in each of the heavily doped regions.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Manufacturing International Corp.
    Inventor: Neil Zhao
  • Publication number: 20140284801
    Abstract: According to an embodiment, a semiconductor device, includes a substrate, an inter-layer insulating layer provided above the substrate, a first interconnect provided in a first trench, and a second interconnect provided in a second trench. The first interconnect is made of a first metal, and the first trench is provided in the inter-layer insulating layer on a side opposite to the substrate. The second interconnect is made of a second metal, and the second trench is provided in the inter-layer insulating layer toward the substrate. A width of the second trench is wider than a width of the first trench. A mean free path of electrons in the first metal is shorter than a mean free path of electrons in the second metal, and the first metal is a metal, an alloy or a metal compound, including at least one nonmagnetic element as a constituent element.
    Type: Application
    Filed: September 5, 2013
    Publication date: September 25, 2014
    Inventors: Masayuki KITAMURA, Atsuko SAKATA, Takeshi ISHIZAKI, Satoshi WAKATSUKI
  • Patent number: 8835309
    Abstract: A method of performing a silicide contact process comprises a forming a nickel-platinum alloy (NiPt) layer over a semiconductor device structure; performing a first rapid thermal anneal (RTA) so as to react portions of the NiPt layer in contact with semiconductor regions of the semiconductor device structure, thereby forming metal rich silicide regions; performing a first wet etch to remove at least a nickel constituent of unreacted portions of the NiPt layer; performing a second wet etch using a dilute Aqua Regia treatment comprising nitric acid (HNO3), hydrochloric acid (HCl) and water (H2O) to remove any residual platinum material from the unreacted portions of the NiPt layer; and following the dilute Aqua Regia treatment, performing a second RTA to form final silicide contact regions from the metal rich silicide regions.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: David F. Hilscher, Christian Lavoie, Ahmet S. Ozcan
  • Patent number: 8822332
    Abstract: A method for forming gate, source, and drain contacts on a MOS transistor having an insulated gate including polysilicon covered with a metal gate silicide, this gate being surrounded with at least one spacer made of a first insulating material, the method including the steps of a) covering the structure with a second insulating material and leveling the second insulating material to reach the gate silicide; b) oxidizing the gate so that the gate silicide buries and covers the a silicon oxide; c) selectively removing the second insulating material; and d) covering the structure with a first conductive material and leveling the first conductive material all the way to a lower level at the top of the spacer.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: September 2, 2014
    Assignees: STMicroelectronics S.A., Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Heimanu Niebojewski, Yves Morand, Cyrille Le Royer, Fabrice Nemouchi
  • Patent number: 8772162
    Abstract: Native oxides and associated residue are removed from surfaces of a substrate by sequentially performing two plasma cleaning processes on the substrate in a single processing chamber. The first plasma cleaning process removes native oxide formed on a substrate surface by generating a cleaning plasma from a mixture of ammonia (NH3) and nitrogen trifluoride (NF3) gases, condensing products of the cleaning plasma on the native oxide to form a thin film that contains ammonium hexafluorosilicate ((NH4)2SiF6), and subliming the thin film off of the substrate surface. The second plasma cleaning process removes remaining residues of the thin film by generating a second cleaning plasma from nitrogen trifluoride gas. Products of the second cleaning plasma react with a few angstroms of the bare silicon present on the surface, forming silicon tetrafluoride (SiF4) and lifting off residues of the thin film.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: July 8, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Bo Zheng, Arvind Sundarrajan, Xinyu Fu
  • Patent number: 8759213
    Abstract: A method for forming a metal-semiconductor alloy layer uses particular thermal annealing conditions to provide a stress free metal-semiconductor alloy layer through interdiffusion of a buried semiconductor material layer and a metal-semiconductor alloy forming metal layer that contacts the buried semiconductor material layer within an aperture through a capping layer beneath which is buried the semiconductor material layer. A resulting semiconductor structure includes the metal-semiconductor alloy layer that further includes an interconnect portion beneath the capping layer and a contiguous via portion that penetrates at least partially through the capping layer. Such a metal-semiconductor alloy layer may be located interposed between a substrate and a semiconductor device having an active doped region.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: June 24, 2014
    Assignee: International Business Machines Corporation
    Inventors: Christian Lavoie, Francois Pagette, Anna W. Topol
  • Patent number: 8735282
    Abstract: The present invention discloses a semiconductor device and a manufacturing method therefor. Conventionally, platinum is deposited in a device substrate to suppress diffusion of nickel in nickel silicide. However, introducing platinum by means of deposition makes the platinum only stay on the surface but fails to effectively suppress the diffusion of nickel over a desirable depth. According to the present invention, a semiconductor device is formed by implanting platinum into a substrate and forming NiSi in a region of the substrate where platinum is implanted. With the present invention, platinum can be distributed over a desirable depth range so as to more effectively suppress nickel diffusion.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: May 27, 2014
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Bing Wu
  • Patent number: 8736054
    Abstract: A wiring structure for a semiconductor device includes a multilayer metallization having a total thickness of at least 5 ?m and an interlayer disposed in the multilayer metallization with a first side of the interlayer adjoining one layer of the multilayer metallization and a second opposing side of the interlayer adjoining a different layer of the multilayer metallization. The interlayer includes at least one of W, WTi, Ta, TaN, TiW, and TiN or other suitable compound metal or a metal silicide such as WSi, MoSi, TiSi, and TaSi.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: May 27, 2014
    Assignee: Infineon Technologies AG
    Inventors: Manfred Schneegans, Jürgen Förster
  • Patent number: 8673778
    Abstract: A tungsten film forming method for forming a tungsten film on a surface of a substrate while heating the substrate in a depressurized atmosphere in a processing chamber includes forming an initial tungsten film for tungsten nucleation on the surface of the substrate by alternately repeating a supply of WF6 gas which is raw material of tungsten and a supply of H2 gas which is a reducing gas in the processing chamber while performing a purge in the processing chamber between the supplies of the WF6 gas and the H2 gas and adsorbing a gas containing a material for nucleation onto a surface of the initial tungsten film. The film forming method further includes depositing a crystallinity blocking tungsten film for blocking crystallinity of the initial tungsten film by supplying the WF6 gas and the H2 gas into the processing chamber.
    Type: Grant
    Filed: November 23, 2012
    Date of Patent: March 18, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Kohichi Satoh
  • Patent number: 8658530
    Abstract: An epitaxial Ni silicide film that is substantially non-agglomerated at high temperatures, and a method for forming the epitaxial Ni silicide film, is provided. The Ni silicide film of the present disclosure is especially useful in the formation of ETSOI (extremely thin silicon-on-insulator) Schottky junction source/drain FETs. The resulting epitaxial Ni silicide film exhibits improved thermal stability and does not agglomerate at high temperatures.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: February 25, 2014
    Assignees: International Business Machines Corporation, GlobalFoundries Inc.
    Inventors: Marwan H. Khater, Christian Lavoie, Bin Yang, Zhen Zhang
  • Patent number: 8658485
    Abstract: There is provided a semiconductor device and a method of fabricating the same. The method of fabricating a semiconductor device according to the present invention comprises: forming a transistor structure including a gate, and source and drain regions on a semiconductor substrate; carrying out a first silicidation to form a first metal silicide layer on the source and drain regions; depositing a first dielectric layer on the substrate, the top of the first dielectric layer being flush with the top of the gate region; forming contact holes at the portions corresponding to the source and drain regions in the first dielectric layer; and carrying out a second silicidation to form a second metal silicide at the gate region and in the contact holes, wherein the first metal silicide layer is formed to prevent silicidation from occurring at the source and drain regions during the second silicidation.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: February 25, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zhijiong Luo, Haizhou Yin, Huilong Zhu
  • Patent number: 8603881
    Abstract: A contact via hole is formed through at least one dielectric layer over a semiconductor substrate. A semiconductor material is deposited at the bottom of the contact via hole and atop the at least one dielectric layer by ion cluster deposition. An angled oxygen cluster deposition is performed to convert portions of the semiconductor material on the top surface of the at least one dielectric layer into a semiconductor oxide, while oxygen is not implanted into the deposited semiconductor material at the bottom of the contact via hole. A metal semiconductor alloy is formed at the bottom of the contact hole by deposition of a metal and an anneal. The semiconductor oxide at the top of the at least one dielectric layer can be removed during a preclean before metal deposition, a postclean after metal semiconductor alloy formation, and/or during planarization for forming contact via structures.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: December 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Ahmet S. Ozcan, Viraj Y. Sardesai, Cung D. Tran
  • Patent number: 8598033
    Abstract: The present invention provides a method for forming a salicide layer. First, a metal-atom-containing layer is formed on a substrate, a first rapid thermal process (RTP) is then performed to the metal-atom-containing layer to form a transitional salicide layer on a specific region. The metal-atom-containing layer is then removed, a thermal conductive layer is formed on the surface of the transitional salicide layer, and a second RTP is performed on the transitional salicide layer.
    Type: Grant
    Filed: October 7, 2012
    Date of Patent: December 3, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Kuo-Chih Lai, Chia Chang Hsu, Bor-Shyang Liao, Chun-Ling Lin, Shu Min Huang, Min-Chung Cheng, Chi-Mao Hsu
  • Patent number: 8592305
    Abstract: Provided are methods of providing aluminum-doped TaSix films. Doping TaSix films allows for the tuning of the work function value to make the TaSix film better suited as an N-metal for NMOS applications. One such method relates to soaking a TaSix film with an aluminum-containing compound. Another method relates to depositing a TaSix film, soaking with an aluminum-containing compound, and repeating for a thicker film. A third method relates to depositing an aluminum-doped TaSix film using tantalum, aluminum and silicon precursors.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: November 26, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Xinliang Lu, Seshadri Ganguli, Shih Chung Chen, Atif Noori, Maitreyee Mahajani, Mei Chang
  • Patent number: 8569170
    Abstract: It is an object of the present invention to obtain a transistor with a high ON current including a silicide layer without increasing the number of steps. A semiconductor device comprising the transistor includes a first region in which a thickness is increased from an edge on a channel formation region side and a second region in which a thickness is more uniform than that of the first region. The first and second region are separated by a line which is perpendicular to a horizontal line and passes through a point where a line, which passes through the edge of the silicide layer and forms an angle ? (0°<?<45°) with the horizontal line, intersects with an interface between the silicide layer and an impurity region, and the thickness of the second region to a thickness of a silicon film is 0.6 or more.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: October 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Hajime Tokunaga
  • Publication number: 20130273734
    Abstract: A method of manufacturing salicide layers includes the following steps. Firstly, a silicon substrate with a patterned stack structure of a silicon layer and a first cap layer sequentially formed thereon is provided. Then, a second cap layer is formed on the exposed silicon substrate. The materials of the first cap layer and the second cap layer are different. Then, the first cap layer is removed to expose the silicon layer. Then, a first metal layer is formed on the silicon layer and reacted with the silicon layer to produce a first salicide layer. Afterward, the second cap layer is removed, and a second metal layer is formed over the surface of the silicon substrate and reacted with the silicon substrate to produce a second salicide layer.
    Type: Application
    Filed: April 12, 2012
    Publication date: October 17, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tse-Yi LU, Chih-Ming CHIEN, Li-Jen YAO
  • Patent number: 8536010
    Abstract: Methods for fabricating a semiconductor device are disclosed. A metal-rich silicide and/or a mono-silicide is formed on source/drain (S/D) regions. A millisecond anneal is provided to the metal-rich silicide and/or the mono-silicide to form a di-silicide with limited spikes at the interface between the silicide and substrate. The di-silicide has an additive which can lower the electron Schottky barrier height.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: September 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Nieh, Hung-Chang Hsu, Wen-Chi Tsai, Mei-Yun Wang, Chii-Ming Wu, Wei-Jung Lin, Chih-Wei Chang
  • Patent number: 8466064
    Abstract: A system, method, and layout for a semiconductor integrated circuit device allows for improved scaling down of various back-end structures, which can include contacts and other metal interconnection structures. The resulting structures can include a semiconductor substrate, a buried diffusion region formed on the semiconductor substrate, and at least one of a silicide film, for example tungsten silicide (WSix), and a self-aligned silicide (salicide) film, for example cobalt silicide (CoSi) and/or nickel silicide (NiSi), above the buried diffusion (BD) layer. The semiconductor integrated circuit can also include a memory gate structure formed over at least a portion of the contact layer.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: June 18, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu-Fong Huang, Tzung-Ting Han, Wen-Pin Lu
  • Patent number: 8455352
    Abstract: Native oxides and associated residue are removed from surfaces of a substrate by sequentially performing two plasma cleaning processes on the substrate in a single processing chamber. The first plasma cleaning process removes native oxide formed on a substrate surface by generating a cleaning plasma from a mixture of ammonia (NH3) and nitrogen trifluoride (NF3) gases, condensing products of the cleaning plasma on the native oxide to form a thin film that contains ammonium hexafluorosilicate ((NH4)2SiF6), and subliming the thin film off of the substrate surface. The second plasma cleaning process removes remaining residues of the thin film by generating a second cleaning plasma from nitrogen trifluoride gas. Products of the second cleaning plasma react with a few angstroms of the bare silicon present on the surface, forming silicon tetrafluoride (SiF4) and lifting off residues of the thin film.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: June 4, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Bo Zheng, Arvind Sundarrajan, Xinyu Fu
  • Patent number: 8409989
    Abstract: A structure and method to fabricate a body contact on a transistor is disclosed. The method comprises forming a semiconductor structure with a transistor on a handle wafer. The structure is then inverted, and the handle wafer is removed. A silicided body contact is then formed on the transistor in the inverted position. The body contact may be connected to neighboring vias to connect the body contact to other structures or levels to form an integrated circuit.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: April 2, 2013
    Assignee: International Business Machines Corporation
    Inventors: Chengwen Pei, Roger Allen Booth, Jr., Kangguo Cheng, Joseph Ervin, Ravi M. Todi, Geng Wang
  • Patent number: 8357611
    Abstract: A semiconductor device having good TFT characteristics is realized. By using a high purity target as a target, using a single gas, argon (Ar), as a sputtering gas, setting the substrate temperature equal to or less than 300° C., and setting the sputtering gas pressure from 1.0 Pa to 3.0 Pa, the film stress of a film is made from ?1×1010 dyn/cm2 to 1×1010 dyn/cm2. By thus using a conducting film in which the amount of sodium contained within the film is equal to or less than 0.3 ppm, preferably equal to or less than 0.1 ppm, and having a low electrical resistivity (equal to or less than 40 ??·cm), as a gate wiring material and a material for other wirings of a TFT, the operating performance and the reliability of a semiconductor device provided with the TFT can be increased.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: January 22, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Keiji Sato, Shunpei Yamazaki
  • Patent number: 8358144
    Abstract: A manufacturing method of a semiconductor device capable of efficiently inspecting whether a metal silicide layer is sufficiently formed is provided. The manufacturing method is provided with the steps of forming a metal layer over a semiconductor layer containing silicon; forming a metal silicide layer over a surface of the semiconductor layer by heating the semiconductor layer and the metal layer; generating image data by performing color imaging of the metal silicide layer from above the metal silicide layer; calculating saturation of the metal silicide layer by processing the image data; and judging the formation amount of the metal silicide layer on the basis of the calculated saturation.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: January 22, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hotaka Maruyama, Masumi Mitsubori, Kaoru Kato
  • Patent number: 8349718
    Abstract: According to certain embodiments, a silicide layer is formed after the fabrication of a functional gate electrode using a gate-last scheme. An initial semiconductor structure has at least one impurity regions formed on a semiconductor substrate, a sacrifice film formed over the impurity region, an isolation layer formed over the sacrifice film and a dielectric layer formed over the isolation film. A via is patterned into the dielectric layer of the initial semiconductor structure and through the thickness of the isolation layer such that a contact opening is formed in the isolation layer. The sacrifice film underlying the isolation layer is then removed leaving a void space underlying the isolation layer. Then, a metal silicide precursor is placed within the void space, and the metal silicide precursor is converted to a silicide layer through an annealing process.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: January 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihiro Uozumi
  • Patent number: 8338292
    Abstract: Contact with a floating body of an FET in SOI may be formed in a portion of one of the two diffusions of the FET, wherein the portion of the diffusion (such as N?, for an NFET) which is “sacrificed” for making the contact is a portion of the diffusion which is not immediately adjacent (or under) the gate. This works well with linked body FETs, wherein the diffusion does not extend all the way to BOX, hence the linked body (such as P?) extends under the diffusion where the contact is being made. An example showing making contact for ground to two NFETs (PG and PD) of a 6T SRAM cell is shown.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: December 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Yue Tan, Zhibin Ren, Richard A. Wachnik, Haining S. Yang
  • Patent number: 8304319
    Abstract: Methods for fabricating a semiconductor device are disclosed. A metal-rich silicide and/or a mono-silicide is formed on source/drain (S/D) regions. A millisecond anneal is provided to the metal-rich silicide and/or the mono-silicide to form a di-silicide with limited spikes at the interface between the silicide and substrate. The di-silicide has an additive which can lower the electron Schottky barrier height.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: November 6, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Nieh, Hung-Chang Hsu, Wen-Chi Tsai, Mei-Yun Wang, Chii-Ming Wu, Wei-Jung Lin, Chih-Wei Chang
  • Patent number: 8293643
    Abstract: A semiconductor device or a photovoltaic cell having a contact structure, which includes a silicon (Si) substrate; a metal alloy layer deposited on the silicon substrate; a metal silicide layer and a diffusion layer formed simultaneously from thermal annealing the metal alloy layer; and a metal layer deposited on the metal silicide and barrier layers.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: October 23, 2012
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., John M. Cotte, Kathryn C. Fisher, Laura L. Kosbar, Christian Lavoie, Zhu Liu, Kenneth P. Rodbell, Xiaoyan Shao
  • Patent number: 8258035
    Abstract: A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: September 4, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, John J. Hackenberg, David C. Sing, Tab A. Stephens, Daniel G. Tekleab, Vishal P. Trivedi
  • Patent number: 8236685
    Abstract: A phase change memory device having multiple metal silicide layers which enhances the current driving capability of switching elements and a method of manufacturing the same are presented. The device also includes switching elements, heaters, stack patterns, top electrodes, bit lines, word line contacts and word lines. The bottom of the switching elements are in electrical contact with the lower metal silicide layer and with an active area of silicon substrate. An upper metal silicide layer is interfaced between the top of the switching elements and the heaters. The stack patterns include phase change layers and top electrodes and are between the heaters and the top electrodes are in electrical contact with the top electrodes. The bit lines contact with the top electrode contacts. The word line contacts to the lower metal silicide film.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: August 7, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Nam Kyun Park
  • Patent number: 8202799
    Abstract: A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening. The metal-silicide layer may then be annealed.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: June 19, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chaing-Ming Chuang, Shau-Lin Shue
  • Patent number: 8173540
    Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: May 8, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tan-Chen Lee, Bor-Wen Chan
  • Patent number: 8158473
    Abstract: To provide a semiconductor device which can reduce an electrical resistance between a plug and a silicide region, and a manufacturing method thereof. At least one semiconductor element having a silicide region, is formed over a semiconductor substrate. An interlayer insulating film is formed over the silicide region. A through hole having an inner surface including a bottom surface comprised of the silicide regions is formed in the interlayer insulating film. A Ti(titanium) film covering the inner surface of the hole is formed by a chemical vapor deposition method. At least a surface of the Ti film is nitrided so as to form a barrier metal film covering the inner surface. A plug is formed to fill the through hole via the barrier metal film.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: April 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuhito Ichinose, Yukari Imai
  • Patent number: 8148248
    Abstract: There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: April 3, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Tsutsumi, Tomonori Okudaira, Keiichiro Kashihara, Tadashi Yamaguchi
  • Patent number: 8084359
    Abstract: A semiconductor package includes a semiconductor chip having first and second pads, a first insulation layer pattern formed on the semiconductor chip and having first and second openings that expose the first and the second pads, respectively, a first conductive layer pattern elongated along the first insulation layer pattern from the first pad, a first external terminal formed on the first conductive layer pattern, a second insulation layer pattern formed on the first conductive layer pattern and the first insulation layer pattern to expose the first external terminal and having a third opening in communication with the second opening, a second conductive layer pattern elongated along the second insulation layer pattern from the second pad, and a second external terminal formed on the second conductive layer pattern.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: December 27, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-Ho You, Ki-Won Choi, Eun-Seok Song
  • Patent number: 8076239
    Abstract: A method of manufacturing a semiconductor device, includes the steps of forming an insulating film on a semiconductor substrate having a silicide layer, forming a hole in the insulating film on the silicide layer, cleaning an inside of the hole and a surface of the silicide layer, forming a titanium layer on a bottom surface and an inner peripheral surface of the hole by a CVD method, forming a copper diffusion preventing barrier metal layer on the titanium layer in the hole, and burying a copper layer in the hole.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: December 13, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazuo Kawamura, Shinichi Akiyama, Satoshi Takesako
  • Patent number: 8030210
    Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal layer on top of, and physical contacting, the silicide region; an inter-layer dielectric (ILD) over the metal layer; and a contact opening in the ILD. The metal layer is exposed through the contact opening. The metal layer further extends under the ILD. The semiconductor structure further includes a contact in the contact opening.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: October 4, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Ya Wang, Chung-Hu Ke, Wen-Chin Lee
  • Patent number: 8021944
    Abstract: A method for fabricating a semiconductor device is disclosed. The method includes: forming a photoresist film on a semiconductor substrate including a silicide forming region and non-silicide forming region; forming a photoresist pattern as a non-salicide pattern by patterning the photoresist film, so as to cover the non-silicide forming region and open the silicide forming region, with an overhang structure that a bottom is removed more compared to a top; forming a metal film on a top of the photoresist pattern and overall the semiconductor substrate in the silicide forming region; stripping the photoresist pattern and the metal film on the photoresist pattern; and forming a silicide metal film by annealing the metal film remaining on the semiconductor substrate. Therefore, the present invention simplifies a salicide process of a semiconductor device, making it possible to improve yields.
    Type: Grant
    Filed: November 29, 2008
    Date of Patent: September 20, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: In-Cheol Baek