Abstract: A photoresist (6) is formed on an element isolation insulating film (2) so as to cover the upper and side surfaces of a polysilicon film (4R) which functions as a resistance element. With the photoresist (6) as an implantation mask, n-type impurities (7) such as phosphorus are ion-implanted from a direction substantially normal to the upper surface of a silicon substrate (1). The dose is in the order of 1013/cm2. Through this processing, an LDD region (8) of MOSFET is formed inside the upper surface of the silicon substrate (1) within a transistor forming region. The impurities (7) are also implanted in a polysilicon film (4G). On the other hand, as the polysilicon film (4R) is covered by the photoresist (6), the impurities (7) are not implanted into the polysilicon film (4R).

Abstract: A process for manufacturing an integrated device comprises the steps of: forming, in a first wafer of semiconductor material, integrated structures including semiconductor regions and isolation regions; forming, on a second wafer of semiconductor material, interconnection structures of a metal material including plug elements having at least one bonding region of a metal material capable of reacting with the semiconductor regions of the first wafer; and bonding the first and second wafers together by causing the bonding regions of the plug elements to react directly with the semiconductor regions so as to form a metal silicide. Thereby, the metallurgical operations for forming the interconnection structures are completely independent of the operations required for processing silicon, so that there is no interference whatsoever between the two sets of operations.

Abstract: A method of forming a crystalline phase material includes, a) providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase; and b) annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. The stress inducing material preferably induces compressive stress within the first crystalline phase during the anneal to the second crystalline phase to lower the required activation energy to produce a more dense second crystalline phase. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials for providing into layers are Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material.

Abstract: A process of making a buried digit line stack is disclosed. The process includes forming a silicon-lean metal silicide first film over a polysilicon plug, followed by a silicide compound barrier second film. The silicide compound barrier second film is covered with a refractory metal third film. A salicidation process causes the first film to salicide with the polysilicon plug. In one embodiment, all the aforementioned deposition processes are carried out by physical vapor deposition (“PVD”).

Abstract: Methods of forming an electrically conductive line include providing a stress inducing material within or a compressive stress inducing layer operatively adjacent a crystalline material of a first crystalline phase. In addition, such methods include annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. Some methods also include providing stress inducing materials into a refractory metal layer. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials include Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material. Example and preferred crystalline phase materials having two phases are refractory metal silicides, such as TiSix.

Abstract: After a silicidation blocking pattern is formed on a substrate including silicon, the silicidation blocking pattern is hardened by a thermal annealing process. The substrate is rinsed to remove a native oxide film formed on the substrate, and then a silicide film is formed on a portion of the substrate exposed by the silicidation blocking pattern. The silicide film can thus be formed in an exact portion of the substrate, and the substrate is not damaged during rinsing.

Abstract: An aspect of the present invention provides a method of manufacturing a semiconductor device, including, forming an insulating film on a silicide layer formed at the surface of a silicon semiconductor substrate, etching the insulating film to form a contact hole in which the silicide layer is exposed, forming a metal nitride film on the bottom and side wall of the contact hole, carrying out a first heating process at 600° C. or lower on the substrate, carrying out, during the first heating process, a second heating process for 10 msec or shorter with light whose main wavelength is shorter than a light absorbing end of silicon, forming a contact conductor in the contact hole after the second heating process, and forming, on the insulating film, wiring that is electrically connected to the substrate through the contact conductor.

Abstract: Gate wiring is formed serving as first gate wiring in a DRAM-forming area, and gate wiring 33 is formed as second gate wiring in a logic-forming area. Then, cobalt silicide layer 37 is formed over a source/drain diffused layer in the DRAM-forming area, and cobalt silicide layer is formed over a source/drain diffused layer and the gate wiring in the logic-forming area. Such formation of the cobalt silicide layer reduces the resistance of the gate wiring and the contact resistance, and thereby enables the high-speed operation of a semiconductor device even if the device is microfabricated.

Abstract: Disclosed are structures and processes which are related to asymmetric, self-aligned silicidation in the fabrication of integrated circuits. A pre-anneal contact stack includes a silicon substrate, a metal source layer such as titanium-rich titanium nitride (TiNx), and a silicon layer. The metal nitride layer is deposited on the substrate by sputtering a target metal reactively in nitrogen and argon ambient. A N:Ar ratio is selected to deposit a uniform distribution of the metal nitride in an unsaturated mode (x<1) over the silicon substrate. The intermediate substrate structure is sintered to form a metal silicide. The silicidation of metal asymmetrically consumes less of the underlying silicon than the overlying silicon layer. The resulting structure is a mixed metal silicide/nitride layer which has a sufficient thickness to provide low sheet resistance without excessively consuming the underlying substrate.

Abstract: A method of forming a crystalline phase material includes, a) providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase; and b) annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. The stress inducing material preferably induces compressive stress within the first crystalline phase during the anneal to the second crystalline phase to lower the required activation energy to produce a more dense second crystalline phase. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials for providing into layers are Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material.

Abstract: The present invention is generally directed to various methods of controlling the formation of metal silicide regions, and a system for performing same. In one illustrative embodiment, the method comprises forming a layer of refractory metal above a feature, performing at least one anneal process to convert a portion of the layer of refractory metal to at least one metal silicide region on the feature, and measuring at least one characteristic of at least one metal silicide region while the anneal process is being performed. In another illustrative embodiment, the method comprises forming a layer of refractory metal above a feature, performing at least one anneal process to convert a portion of the layer of refractory metal to at least one metal silicide region on the feature, and performing at least one scatterometric measurement of the metal silicide region after at least a portion of the anneal process is performed to determine at least one characteristic of the metal silicide region.

Abstract: After an etching stop layer and an interlayer dielectric film are formed on a semiconductor substrate including a contact formation portion, a polysilicon film and a anti-reflective layer are successively formed on the interlayer dielectric film. A second mask pattern exposing the polysilicon film is formed after etching the anti-reflective layer exposed through a first mask pattern. A third mask pattern is formed by attaching polymer on a sidewall of the second mask pattern. A contact hole exposing the contact formation portion is formed by etching the polysilicon film and the interlayer dielectric film using the third mask pattern as an etching mask. A conductive material is filled in the contact hole to form the contact. By attaching the polymer to the second mask pattern, a contact hole with a minute size can be formed.

Abstract: A MOS field effect transistor for reducing the resistance between a source and a drain includes a gate insulation layer and a gate electrode sequentially formed on a semiconductor substrate includes deep source/drain regions formed in upper portions of the semiconductor substrate at both sides of the gate electrode. Source/drain extension regions are formed in upper portions of the semiconductor substrate extending from the deep source/drain regions toward a channel region below the gate electrode to be thinner than the deep source/drain regions. A first silicide layer having a first thickness is formed on the surface of each of the deep source/drain regions. A second silicide layer having a second thickness thinner than the first thickness of the first silicide layer is formed to extend from the first silicide layer in a predetermined upper portion of each of the source/drain extension regions.

Abstract: A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.

Abstract: A method of fabricating contact holes on a semiconductor chip with a plurality of gates and a first mask layer includes filling a dielectric layer into the inter-gate space of two gates, polishing the dielectric layer until the surface of the dielectric layer is coplanar with the gates, depositing a second mask layer, etching the second mask layer to form a bit line opening in an array area and simultaneously forming a gate opening and a substrate opening in a periphery area, removing a portion of the dielectric layer through the bit line opening and the substrate opening to form a bit line contact hole and a substrate contact hole, filling a metal layer into the bit line contact hole and the substrate contact hole, and etching the first mask layer through the gate opening to form a gate contact hole.

Abstract: A method and system for fabricating a capacitor utilized in a semiconductor device. A salicide gate is designated for use with the semiconductor device. A self-aligned contact (SAC) may also be configured for use with the semiconductor device. The salicide gate and the self-aligned contact are generally in a memory cell area of the semiconductor device to thereby permit the efficient shrinkage of memory cell size without an additional mask or weakening of associated circuit performance. Combining, the self-aligned contact and the salicide gate in the same memory cell area can effectively reduce gate resistance.

Abstract: Tungsten silicide layers are formed on a substrate and a semiconductor component has deep trench capacitors with a filling of tungsten silicide. The tungsten silicide layers are deposited on the substrate at a temperature of less than 400° C. and at a pressure of less than 10 torr from the vapor phase. The vapor phase hs a tungsten-containing precursor substance and a silicon-containing precursor substance. The molar ratio of the silicon-containing precursor compound to the tungsten-containing precursor compound in the vapor phase is selected to be greater than 500.

Abstract: Semiconductor devices, such as transistors, with a supersaturated concentration of dopant in the source/drain extension and metal silicide contacts enable the production of smaller, higher speed devices. Supersaturated source/drain extensions are subject to dopant diffusion out from the source/drain extension during high temperature metal silicide contact formation. The formation of lower temperature metal silicide contacts, such as nickel silicide contacts, prevents dopant diffusion and maintains the source/drain extensions in a supersaturated state throughout semiconductor device manufacturing.

Abstract: The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. In one aspect, the invention includes a method of forming a conductive line comprising: a) forming a polysilicon layer; forming a silicide layer against the polysilicon layer; b) providing a conductivity-enhancing impurity within the silicide layer; and c) providing the polysilicon layer and the silicide layer into a conductive line shape. In another aspect, the invention includes a programmable-read-only-memory device comprising: a) a first dielectric layer over a substrate; b) a floating gate over the first dielectric layer; c) a second dielectric layer over the floating gate; d) a conductive line over the second dielectric layer; and e) a metal-silicide layer over the conductive line, the metal-silicide layer comprising a Group III dopant or a Group V dopant.

Abstract: A method for forming an epitaxial cobalt silicide layer on a MOS device includes sputter depositing cobalt in an ambient to form a first layer of cobalt suicide on a gate and source/drain regions of the MOS device. Subsequently, cobalt is sputter deposited again in an ambient of argon to increase the thickness of the cobalt silicide layer to a second thickness.

Abstract: A method is described for filling of high aspect ratio contact vias provided over silicon containing areas. A via is formed in an insulating layer over the silicon containing area and a silicide forming material is deposited in the via. A silicide region is formed over the silicon containing area, the silicide forming material is removed from the via leaving the silicide region. The via is then filled with a conductor using an electroless plating process.

Abstract: A MOSFET gate or a MOSFET source or drain region comprises silicon germanium or polycrystalline silicon germanium. Silicidation with nickel is performed to form a nickel germanosilicide that preferably comprises the monosilicide phase of nickel silicide. The inclusion of germanium in the silicide provides a wider temperature range within which the monosilicide phase may be formed, while essentially preserving the superior sheet resistance exhibited by nickel monosilicide. As a result, the nickel germanosilicide is capable of withstanding greater temperatures during subsequent processing than nickel monosilicide, yet provides approximately the same sheet resistance and other beneficial properties as nickel monosilicide.

Abstract: Methods for reducing the contact resistance presented by the interface between a silicide and a doped silicon region are presented. In a first method, a silicide layer and a doped silicon region form an interface. Either a damage-only species or a heavy, metal is implanted through the silicide layer into the doped silicon region immediately adjacent the interface. In a second method, a second metal is added to the refractory metal before formation of the silicide. After annealing the refractory metal and the doped silicon region, the second metal diffuses into the doped silicion region immediately adjacent the interface without forming additional phases in the silicide.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The structure of a semiconductor device includes gate electrodes having a T-shaped structure comprised of first and second gate electrodes having low gate resistance and low parasitic capacitance and a halo ion-implanted region in which a short channel effect can be effectively suppressed. The method for manufacturing the device is capable of performing high angle ion implantation without extending gate-to-gate space.

Abstract: A low resistance Co silicide layer with less leakage current is formed over the surface of the source and drain of a MISFET by optimizing the film forming conditions and annealing conditions upon formation of Co (cobalt) silicide. Described specifically, low resistance source and drain (n+ type semiconductor regions, p+ type semiconductor regions) with less junction leakage current are formed by, upon formation of a Co silicide layer by heat treating a Co film deposited over the source and drain (n+ type semiconductor regions, p+ type semiconductor regions) of the MISFET, depositing the Co film at a temperature as low as 200° C. or less, carrying out heat treatment in three stages to convert the Co silicide layer from a dicobalt silicide (CO2Si) layer to a cobalt monosilicide (CoSi) layer and then to a cobalt disilicide (CoSi2) layer successively.

Abstract: Direct focused ion beam (FIB) mixing is given as a method for patterning of metal silicide structures on a silicon surface. This technique allows the fabrication of submicron structures without the use of resist-based lithography methods. VLSI containing metal silicide connects, interconnects and structures may be prepared by the method. Fast semiconductor devices having good circuit speed and reduced RC time delay including the technologies MEMS, MOSFET, CMOS, pMOS, nMOS and BiCMOS result.

Abstract: A method for forming silicide at source and drain. The method includes providing a semiconductor substrate having an active region and peripheral region, wherein gates with source and drain on two sides are formed in the peripheral region, conformally forming a barrier layer to cover the active region and the peripheral region, forming a mask layer to cover the barrier layer at the active region, removing the barrier layer from the peripheral region; removing the mask layer, forming a metal layer to cover the peripheral region, and subjecting the metal layer to thermal process such that silicon reacts with the metal to form silicide at the source and the drain.

Abstract: A method for forming a gate silicide portion comprising the following steps. A substrate having a gate oxide layer formed is provided. A gate layer is formed over the gate oxide layer. An RPO layer is formed over the gate layer. A patterned photoresist layer is formed over the RPO layer exposing a portion of the RPO layer. The portion of the RPO layer having a patterned photoresist residue thereover. The structure is subjected to a dry plasma or gas treatment to clean the exposed portion of the RPO layer and removing the patterned photoresist residue. The RPO layer is etched using the patterned photoresist layer as a mask to expose a portion of the gate layer. The dry plasma or gas treatment preventing formation of defects or voids in the RPO layer and the poly gate layer during etching of the RPO layer. A metal layer is formed over at least the exposed portion of the gate layer.

Abstract: The present invention provides a structure in which a glue layer is formed on an active area and a shallow trench isolation with a glue layer interposed therebetween. A P-type silicon substrate includes the active area partitioned by the shallow trench isolation. An N+-type semiconductor region is formed in the active area. An interlayer insulation film is formed on the shallow trench isolation and active area, and has an opening to which the shallow trench isolation, active area, and a boundary between them are exposed. A glue layer is formed in the opening. Local interconnect wiring is formed in the opening and electrically connected to the N+-type semiconductor region through the glue layer. The active area overlaps the shallow trench isolation, and the glue layer has a portion opposed to the N+-type semiconductor region through the shallow trench isolation underlying the overlap of the active area.

Abstract: In highly sophisticated MOS transistors including nickel silicide portions for reducing the silicon sheet resistance, nickel silicide stingers may lead to short circuits between the drain and source region and the channel region, thereby significantly lowering production yield. By substantially amorphizing corresponding portions of the source and drain regions, the creation of clustered point defects may effectively be avoided during curing implantation induced damage, wherein a main diffusion path for nickel during the nickel silicide formation is interrupted. Thus, nickel silicide stingers may be significantly reduced or even completely avoided.

Abstract: Methods for making a semiconductor structure are discussed. The methods include forming openings in a high-density area and a high-speed area, and forming a metallization layer simultaneously into the high-density area and the high-speed area. The metallization layer includes a combination of substances and compounds that reduce vertical resistance, reduce horizontal resistance, and inhibit cross-diffusion.

Abstract: A first dielectric layer is formed over a first transistor gate and a second transistor source/drain region. Contact openings are formed in the first dielectric layer to the first transistor gate and to the second transistor source/drain region. A second dielectric layer is formed over the first dielectric layer and to within the contact openings. The second dielectric layer is etched selectively relative to the first dielectric layer to form at least a portion of a local interconnect outline within the second dielectric layer to extend between the first transistor gate and the second transistor source/drain region. The etching removes at least some of the second dielectric layer within the contact openings. Conductive material is formed within the local interconnect outline within the second dielectric layer which electrically connects the first transistor gate with the second transistor source/drain region. Other aspects are disclosed.

Abstract: A method for the fabrication of a gate stack, in particular in very large scale integrated semiconductor memories, uses a combination of a damascene process and a CMP process to produce a gate stack which includes a polysilicon section, a silicide section and a covering-layer section thereabove. The gate stack can be fabricated by using conventional materials, has a very low sheet resistance of <1 ohm/unit area and may carry self-aligning contact sections.

Abstract: Silicide interfaces for integrated circuits, thin film devices, and backend integrated circuit testing devices are formed using a barrier layer, such as titanium nitride, disposed over a porous, thin dielectric layer which is disposed between a silicon-containing substrate and a silicidable material which is deposited to form the silicide interfaces for such devices. The barrier layer prevents the formation of a silicide material within imperfections or voids which form passages through the thin dielectric layer when the device is subjected to a high temperature anneal to form the silicide contact from the reaction of the silicidable material and the silicon-containing substrate.

Abstract: The introduction of a barrier diffusion material, such as nitrogen, into a silicon-containing conductive region, for example the drain and source regions and the gate electrode of a field effect transistor, allows the formation of nickel silicide, which is substantially thermally stable up to temperatures of 500° C. Thus, the device performance may significantly improve as the sheet resistance of nickel silicide is significantly less than that of nickel disilicide.

Abstract: An integrated semiconductor device has an improved reliability and is adapted to a higher degree of integration without reducing the accumulated electric charge of each information storage capacity element. The semiconductor device is provided with a DRAM having memory cells, each comprising an information storage capacity element C connected in series to a memory cell selection MISFET Qs formed on a main surface of a semiconductor substrate 1 and having a lower electrode 54, a capacity insulating film 58 and an upper electrode 59. The lower electrode 54 is made of ruthenium film oriented in a particular plane bearing, e.g., a (002) plane, and the capacity insulating film 58 is made of a polycrystalline tantalum film obtained by thermally treating an amorphous tantalum oxide film containing crystal of tantalum oxide in an as-deposited state for crystallization.

Abstract: Integrated circuit memory devices include a memory cell field effect transistor in an integrated circuit substrate, a conductive plug that electrically contacts the memory cell field effect transistor and a titanium nitride bit line that electrically contacts the conductive plug opposite the memory cell filed effect transistor. Titanium nitride also may be used to electrically contact field effect transistors in the peripheral region of the integrated circuit memory device. Titanium nitride can be used as a bit line metal instead of conventional tungsten, and as a conductive plug to contact both p+-type and n+-type source/drain regions in the peripheral region of the memory device. The titanium nitride conductive plugs and bit lines may be formed simultaneously.

Abstract: In accordance with one embodiment of the present invention, a method of interfacing a poly-metal stack and a semiconductor substrate is provided where an etch stop layer is provided in a polysilicon region of the stack. The present invention also addresses the relative location of the etch stop layer in the polysilicon region and a variety of stack materials and oxidation methods. The etch stop layer may be patterned within the poly or may be a continuous conductive etch stop layer in the poly. The present invention also relates more broadly to a process for forming wordline architecture of a memory cell. In accordance with another embodiment of the present invention, a semiconductor structure is provided comprising a poly-metal stack formed over a semiconductor substrate where the interface between an oxidation barrier placed over the stack and an oxidized portion of the stack lies along the sidewall of the poly.

Abstract: A method for making a flexible metal silicide local interconnect structure. The method includes forming an amorphous or polycrystalline silicon layer on a substrate including at least one gate structure, forming a layer of silicon nitride over the silicon layer, removing a portion of the silicon nitride layer, oxidizing the exposed portion of the silicon layer, removing the remaining portion of the silicon nitride layer, optionally removing the oxidized silicon layer, forming a metal layer over the resulting structure, annealing the metal layer in an atmosphere comprising nitrogen, and removing any metal nitride regions. The local metal silicide interconnect structure may overlie the at least one gate structure. The methods better protect underlying silicon regions (e.g., substrate), as well as form TiSix local interconnects with good step coverage. Intermediate and resulting structures are also disclosed.

Abstract: A contact interface having a substantially continuous profile along a bottom and lower sides of the active surface of the semiconductor substrate formed within a contact opening is provided. The contact interface is formed by depositing a layer of conductive material, such as titanium, using both a high bias deposition and a low bias deposition. The high bias and low bias deposition may be effected as a two-step deposition or may be accomplished by changing the bias from a high level to a low level during deposition, or vice versa. The conductive material may be converted to a silicide by an annealing process to form the contact interface.

Abstract: A semiconductor process is provided that creates transistors having polycide gates in a first region of a semiconductor substrate and transistors having salicide gates in a second region of the semiconductor substrate. A polysilicon layer having a first portion in the first region and a second portion in the second region is formed over the semiconductor substrate. Then, a first dielectric layer is formed over the second portion of the polysilicon layer. Metal silicide is deposited over first portion of the polysilicon layer and the first dielectric layer. The metal silicide overlying the first dielectric layer is removed as is the first dielectric layer. The metal silicide and the polysilicon layer are etched to form polycide gates in the first region and polysilicon gates in the second region. A second dielectric layer is formed over the first region. Refractory metal is then deposited over the resulting structure and reacted. As a result, salicide is formed on the polysilicon gates of the second region.

Abstract: A layer comprising a second metal silicide as a major constituent element or a layer comprising a second metal as a major constituent element is formed simultaneously by one single chemical vapor deposition process to the bottom surface of two out of there groups of openings etched in a dielectric film on a substrate. A surface comprising silicon as a major constituent element is exposed at each bottom (“through holes or local interconnection holes”) of the first group of openings, a surface comprising a first metal silicide as a major constituent element is exposed at each bottom of the second group of openings, and a surface comprising a first metal as a major constituent element is exposed at each bottom of the third group of openings. The manufacturing method provides low contact resistance and sufficiently small junction leakage current from a diffusion layer in connection with plugs or local interconnections, even if the etched area of the openings are of different depths, shapes, or sizes.

Abstract: A process for forming high temperature stable self-aligned suicide layer that not only establishes itself smoothly and uniformly despite the use of a high temperature in the siliciding reaction, but also can withstand other subsequent high temperature thermal processing operations and maintaining a stable metal silicide layer profile thereafter. Moreover, desired thickness and uniformity of the metal suicide layer can be obtained by suitably adjusting the amorphous implant parameters, while the use of a titanium nitride cap layer help to stabilize the metal silicide layer during high temperature formation and that a stable and uniform metal suicide layer profile can be ensured even if subsequent high temperature processing operations are performed.

Abstract: A method for forming a silicide layer of a semiconductor memory device is disclosed. A silicide layer is formed in an impurity junction region through a contact hole exposing the impurity junction region on a semiconductor substrate. Here, two thermal annealing processes are performed on the semiconductor substrate on which a metal layer is deposited, by using low and high temperature up speeds and maintaining the semiconductor substrate under the highest temperature for less than one second, and then dropping the temperature at high speed. The process for removing a portion of the metal layer which did not react is carried out. As a result, a shallow junction can be formed in a very small devices, and deterioration of an electrical property of the semiconductor device is minimized by reducing junction leakage current, which results in the rapid operation of the device.

Abstract: A ternary metal silicide layer is formed between a silicon substrate and a barrier layer, in a contact structure including: a substrate having a silicon part; an insulating layer formed on the substrate, and having a connection hole that reaches the silicon part, a barrier layer formed at least on an inner surface of the connection hole; and a conductive member buried inside the barrier layer.

Abstract: A method for manufacturing a semiconductor device can simply form a silicide film for reducing ohmic contact between a metal line and a substrate and a ternary phase thin film as an amorphous diffusion prevention film between a metal line and the silicide film. The method for manufacturing a semiconductor device includes the steps of sequentially forming a first refractory metal and a second refractory metal on a semiconductor substrate, forming a silicide film on an interface between the semiconductor substrate and the first refractory metal, and reacting the semiconductor substrate with the first and second refractory metals on the silicide film to form a ternary phase thin film.

Abstract: A semiconductor device is fabricated by providing a substrate, and providing a dielectric layer on the substrate. A polysilicon body is formed on the dielectric layer, and a metal layer is provided on the polysilicon body. A silicidation process is undertaken to silicidize substantially the entire polysilicon body to form a gate on the dielectric. In an alternative process, a cap layer is provided on the polysilicon body, which cap layer is removed prior to the silicidation process. The polysilicon body is doped with a chosen specie prior to the silicidation process, which dopant, during the silicidation process, is driven toward the dielectric layer to form a gate portion having a high concentration thereof adjacent the dielectric, the type and concentration of this specie being instrumental in determining the work function of the formed gate.

Abstract: An embodiment of the present invention teaches a method used in a semiconductor fabrication process to form a memory cell in a semiconductor device comprising the steps of: subjecting a layered structure comprising a silicon gate insulating layer, a conductively doped polysilicon gate layer and a refractory metal silicide gate film to a thermal processing step; forming a sheet resistance capping layer directly on the refractory metal silicide film during at least a period of time of the thermal processing step, the sheet resistance capping layer forming a substantially uniform surface on the refractory metal silicide film; patterning and etching the layered structure to form the transistor gate; forming source and drain regions aligned to opposing sides of the transistor gate and formed into an underlying silicon substrate; and forming a storage capacitor (such as a stacked capacitor or a container cell) connecting to one of the source and drain regions.

Abstract: Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices are fomxed by a salicide process wherein a blanket nickel layer is formed in contact with the exposed portions of the substrate surface adjacent the sidewall spacers, the top surface of the gate electrode, and the sidewall spacers. Embodiments include forming the blanket layer of nickel is formed by the sequential steps of: (i) forming a layer of nickel by sputtering with nitrogen gas; and, (ii) forming a layer of nickel by sputtering with argon gas. The two step process for forming the blanket layer of nickel advantageously prevents the formation of nickel silicide on the outer surfaces of the insulative sidewall spacers.

Abstract: In one aspect of the present invention, a layer stack comprising at least three material layers is provided on a silicon-containing conductive region to form a silicide portion on and in the silicon-containing conductive region, wherein the layer next to the silicon provides the metal atoms for the chemical reaction, and wherein the following layers provide for a sufficient inertness of the chemical reaction. The method may be carried out as an in situ method, thereby significantly improving throughput and deposition tool performance compared to typical prior art processes, in which at least two deposition chambers have to be used.