Abstract: The present invention relates to an electrically conductive film stack for semiconductors and methods and apparatus for providing same. A film stack comprising a first layer of a platinum-rhodium alloy deposited by metal organic chemical vapor deposition (MOCVD) in the presence of a reducer, such as hydrogen (H2) gas, and a second layer of the platinum-rhodium alloy deposited in the presence of an oxidizing gas, such as ozone (O3), provides an electrical conductor that is also a relatively good barrier to oxygen. The platinum-rhodium film stack can be used as an electrode or capacitor plate for a capacitor with a high-k dielectric material. The electrode formed with alternating reducing and oxidizing agents produces a rough surface texture, which enhances the memory cell capacitance.

Abstract: The invention includes a method of forming a metal-comprising mass for a semiconductor construction. A semiconductor substrate is provided, and a metallo-organic precursor is provided proximate the substrate. The precursor is exposed to a reducing atmosphere to release metal from the precursor, and subsequently the released metal is deposited over the semiconductor substrate. The invention also includes capacitor constructions, and methods of forming capacitor constructions.

Abstract: Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate.

Abstract: A method for making an integrated circuit device includes forming at least one interconnect structure adjacent a semiconductor substrate and including a copper portion and at least one barrier layer adjacent to the copper portion, and displacement plating surface portions of the copper portion with a plating metal more noble than copper and different than copper. The method including displacement plating provides selective and self-limiting thickness plating and enhances the electromigration resistance of the interconnect structure. The displacement plating may include subjecting the copper portion to a plating bath including the plating metal. Because displacement plating is used and is not an electroless plating process, the concentration of the metal in the aqueous plating bath and the plating time are not critical. The method may further include annealing the integrated circuit device after the displacement plating to diffuse the plating metal into the copper portion.

Abstract: There are included a semiconductor substrate provided with a desirable element region, an electrode pad formed to come in contact with a surface of the semiconductor substrate or a wiring layer provided on the surface of the semiconductor substrate, a bump formed on a surface of the electrode pad through an intermediate layer, and a resin insulating film formed in at least a peripheral portion of the bump to cover an interface of the bump and the intermediate layer which is exposed to a side surface of the bump.

Abstract: A semiconductor substrate with a plurality of semiconductor devices formed therein is processed by initially forming a silicon nitride insulating layer over the semiconductor devices. Interconnect holes are formed in the insulating layer. The interconnect holes are filled with a silver-based conductive material so that portions of the silver-based conductive material extend beyond the uppermost boundary of the interconnect holes. The device is then chemically and mechanically planarized with a processing slurry selected to be minimally selective of silicon nitride and relatively highly selective of the silver-based conductive material. The processing slurry comprises an abrasive and an oxidizer. In this manner, the portions of the silver-based conductive material extending beyond said uppermost boundary of the interconnect holes are removed.

Abstract: A gold wire having a non-pure gold core member and a layer of pure gold coating covering the non-pure gold core member. The fabrication method of the gold wire includes the procedures of (1) selecting a non-pure gold wire rod, (2) gold-plating the non-pure gold wire rod with a layer of pure gold coating of thickness about 10˜100 &mgr;in, (3) drawing the pure gold-coated wire rod into a gold wire of thickness about 40˜4000 &mgr;in, (4) examining the material properties of the gold wire so as to obtained the desired finished product.

Abstract: The present invention provides a system and method for creating self-doping contacts to silicon devices in which the contact metal is coated with a layer of dopant and subjected to high temperature, thereby alloying the silver with the silicon and simultaneously doping the silicon substrate and forming a low-resistance ohmic contact to it. A self-doping negative contact may be formed from unalloyed silver which may be applied to the silicon substrate by either sputtering, screen printing a paste or evaporation. The silver is coated with a layer of dopant. Once applied, the silver, substrate and dopant are heated to a temperature above the Ag-Si eutectic temperature (but below the melting point of silicon). The silver liquefies more than a eutectic proportion of the silicon substrate. The temperature is then decreased towards the eutectic temperature.

Abstract: A CMP slurry for ruthenium and a polishing process using the same. In a process technology below 0.1 &mgr;m, when a capacitor using a (Ba1−xSrx)TiO3 film as a dielectric film is fabricated, the slurry is used to polish a ruthenium film deposited as a lower electrode according to a CMP process. The CMP process is performed by using the slurry, to improve a polishing speed of ruthenium under a low polishing pressure. In addition, the CMP process is performed according to an one-step process by using one kind of slurry. As a result, defects on an insulating film are reduced and a polishing property is improved, thereby simplifying the CMP process.

Abstract: A method for the formation of rhodium films with good step coverage is disclosed. Rhodium films are formed by a low temperature atomic layer deposition technique using a first gas of rhodium group metal precursor followed by an oxygen exposure. The invention provides, therefore, a method for forming smooth and continuous rhodium films which also have good step coverage and a reduced carbon content.

Abstract: An underlying conductive film made of iridium and having a thickness of about 0.1 &mgr;m is formed in a contact hole formed in an insulating film covering a transistor formed in a substrate, except in the top portion of the contact hole. The underlying conductive film covers the sidewall portions of the contact hole and the top surface of the drain region but does not completely fill in the contact hole. A plug made of platinum is filled in the contact hole up to the top portion thereof. Over the contact hole of the insulating film, there is formed a capacitor composed of a lower electrode made of platinum, a capacitor insulating film made of SrBi2Ta2O9, and an upper electrode made of platinum in contact relation with the respective upper ends of the underlying conductive film and the plug.

Abstract: In a method for manufacturing a semiconductor device in which wiring layers are formed by a damascene method, certain embodiments relate to a manufacturing method and a semiconductor device, in which a bonding pad section having a multiple-layered structure can be formed by a simple method without increasing the number of process steps. One embodiment includes a method for manufacturing a semiconductor device in which at least an uppermost wiring layer is formed by a damascene method.

Abstract: A platinum film orientation-controlled to (111), (200) and/or (220) is provided by depositing the platinum film under an atmosphere containing an oxygen component such as O2, O3, N2O , N2+O2, or mixtures thereof as well as an inert gas (Ar, Ne, Kr, or Xe) on a substrate heated to a temperature ranged from room temperature to 700° C., and annealing to remove the gases introduced into the platinum film during the deposition thereof. The platinum film formed in this process has excellent electrical conductivity (resistivity is lower than 15 &mgr;&OHgr;-cm), good enough adhesion strength to be used for electronic devices, and does not show hillocks, voids or pinholes.

Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additives over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2layer in said structure.

Abstract: An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used.

Abstract: This invention relates to manufacturing of integrated circuits (ICs) and especially conductive layers suitable for use in an IC. According to the preferred method a metal oxide thin film is deposited on a substrate surface and reduced thereafter essentially into a metallic form with an organic reducing agent. The metal oxide is preferably deposited according to the principles of atomic layer deposition (ALD) using a metal source chemical and an oxygen source chemical. The reduction step is preferably carried out in an ALD reactor using one or more vaporized organic compounds that contain at least one functional group selected from the group consisting of —OH, —CHO and —COOH.

Abstract: An inverted PCRAM cell is formed by plating the bottom electrode, made of copper for example, with a conductive material, such as silver. Chalcogenide material is disposed over the plated electrode and subjected to a conversion process so that ions from the plated material diffuse into the chalcogenide material.

Abstract: A method for manufacturing a metal interconnection includes the steps of, preparing an active matrix provided with a substrate, an insulating layer and an opening formed through the insulating layer, forming a diffusion barrier layer on surfaces of the opening and the insulating layer, forming a protection layer on the diffusion barrier layer, forming a first metal layer into the opening and upon the protection layer, forming a second metal layer on the first metal layer, and polishing back the first and the second metal layer to a top surface of the insulating layer, thereby forming a metal interconnection.

Abstract: For fabricating an interconnect structure formed within an interconnect opening surrounded by dielectric material, a layer of diffusion barrier material is formed on at least one wall of the interconnect opening. An activation layer comprised of palladium is formed on the layer of diffusion barrier material when the interconnect opening is immersed in an activation bath comprised of tin ions and palladium ions. The tin ions have a tin ion concentration in the activation bath that is greater than a palladium ion concentration in the activation bath. A layer of seed material is deposited on the activation layer in an electroless deposition process, and the interconnect opening is filled with a conductive fill material grown from the layer of seed material. A layer of silicon rich material may be formed on the layer of diffusion barrier material before deposition of the activation layer such that the activation layer is formed on the layer of silicon rich material.

Abstract: In a method for fabricating a thin film transistor array substrate, a glass substrate undergoes an oxygen plasma treatment. A silver or silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a gate line assembly proceeding in the horizontal direction. The gate line assembly includes gate lines, gate electrodes, and gate pads. Thereafter, a silicon nitride-based gate insulating layer is deposited onto the substrate, and a semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. The semiconductor layer and the ohmic contact layer are HF-treated. A silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a data line assembly. The data line assembly includes data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads.

Abstract: A method of forming an iridium-containing film on a substrate, such as a semiconductor wafer using complexes of the formula LyIrXz, wherein: each L group is independently a neutral or anionic ligand; each Y group is independently a pi bonding ligand selected from the group of CO, NO, CN, CS, N2, PX3, PR3, P(OR)3, AsX3, AsR3, As(OR)3, SbX3, SbR3, Sb(OR)3, NHxR3-x, CNR, and RCN, wherein R is an organic group and X is a halide; y=1 to 4; z=1 to 4; x=0 to 3.

Abstract: In the case of providing a contact hole (2a) in an insulting film (2) on the substrate (1), and forming a wiring on the insulting film to be connected to an exposed portion by the contact hole, a tin film (4) is formed on a location where the wiring is formed, and a paradium film (5) is formed on a location where the wiring is formed by immersing a portion where the tin film is provided in a solution containing a paradium ion (Pd2+). Then, the paradium film is used as a reaction start layer to form a copper film (6) by the electroless plating method. Furthermore, a second copper film may be formed by the electroplating by using the copper film as the feeder layer. By doing so, there is provided a semiconductor device wherein the diffusion of elements of the reaction start layer (the seed layer) into the film is prevented, a copper film having a small specific resistance and excellent conductivity formed with good reliability, and a higher integration can be provided with further fine wiring.

Abstract: The reliability and elecrtromigration resistance of planarized metallization patterns, e.g., of copper, in-laid in the surface of a layer of dielectric material, are enhanced by a process comprising blanket-depositing on the planarized, upper surfaces of the metallization features and the dielectric layer at least one thin layer comprising at least one alloying element for the metal of the features, and then uniformly diffusing at least a minimum amount of the at least one thin layer for a minimum depth below the upper surfaces of the metallization features to effect alloying therewith. The alloyed portions of the metallization features advantageously reduce electromigration therefrom. Planarization, as by CMP, may be performed subsequent to diffusion/alloying to remove any remaining elevated, alloyed or unalloyed portions of the at least one thin layer.

Abstract: The present invention pertains to systems and methods for reducing the agglomeration of copper deposited by physical vapor deposition. More specifically, the invention pertains to systems and methods for depositing copper seed layers on a semiconductor wafer. The invention involves the use of an anti-agglomeration agent, so that the copper deposition is completed in an even, continuous and conformal manner.

Abstract: A method for removing a portion of an upper layer of one material from an underlying layer of another material to form a uniformly planar surface on a semiconductor wafer. In accordance with one embodiment of the invention, an upper section of the upper layer is etched to an intermediate point in the upper layer. The etching step removes the upper section of the upper layer and leaves only a lower section of the upper layer on the wafer. The lower section of the upper layer is then planarized to a final endpoint. The etching step preferably moves the majority of the upper layer from the wafer so that the remaining portion of the upper layer is thick enough to allow the planarization step to produce a uniformly planar finished surface on the wafer.

Abstract: The substrate according to the present invention is comprised of a silver/gold/grain element alloy layer, wherein the alloy forms an outside layer of the product. The grain element is selected from a group consisting of selenium, antimony, bismuth, nickel, cobalt, indium and combination thereof. The present invention has a particular application in forming the outside layer of various items, including a lead frame, a ball grid array, a header, a printed circuit board, a reed switch and a connector.

Abstract: The present invention provides a method for producing atomic ridges on a substrate comprising: depositing a first metal on a substrate; heating the substrate to form initial nanowires of the first metal on the substrate; depositing a second metal on the initial nanowires of the first metal to form thickened nanowires that are more resistant to etching than the initial nanowires; and etching the substrate to form atomic ridges separated by grooves having a pitch of 0.94 to 5.35 nm. The present invention also provides a method for forming Au and other metal nanowires that may be used for electrical conductors and both positive and negative etch masks to form a plurality of ridges at a pitch of 0.94 to 5.35 nm containing at least two adjacent grooves with widths of 0.63 to 5.04 nm.

Abstract: A semiconductor device for use in a memory cell includes an active matrix provided with a silicon substrate, a transistor formed on the silicon substrate and isolation regions for isolating the transistor, a capacitor structure formed on top of the active matrix and a metal interconnection for electrically connecting the capacitor structure to the transistor, wherein the capacitor structure includes a bottom and a top electrodes and a capacitor thin film sandwiched therebetween. In the semiconductor device, the bottom electrode is made of a material such as iridium, ruthenium or the like. In order to improve the adhesion between the bottom electrode and insulating layers adjacent thereto, the bottom electrode is encompassed with a metal oxide such as a iridium oxide, ruthenium oxide or the like.

Abstract: The present invention provides a method for forming a substantially carbon- and oxygen-free conductive layer, wherein the layer can contain a metal and/or a metalloid material. According to the present invention, a substantially carbon- and oxygen-free conductive layer is formed in an oxidizing atmosphere in the presence of an organometallic catalyst using, for example, a chemical vapor deposition process. Such layers are particularly advantageous for use in memory devices, such as dynamic random access memory (DRAM) devices.

Abstract: In a method for manufacturing a semiconductor device in which wiring layers are formed by a damascene method, certain embodiment relate to a manufacturing methods and semiconductor devices, in which a bonding pad section having a multiple-layered structure can be formed by a simple method without increasing the number of process steps.

Abstract: An Ir—M—O composite film has been provided that is useful in forming an electrode of a ferroelectric capacitor, where M includes a variety of refractory metals. The Ir combination film effectively prevents oxygen diffusion, and is resistant to high temperature annealing in oxygen environments. When used with an underlying barrier layer made from oxidizing the same variety of M transition metals, the resulting conductive barrier also suppresses the diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. The Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. The Ir—M—O conductive electrode/barrier structures are useful in nonvolatile MFMIS (metal/ferro/metal/insulator/silicon) memory devices, DRAMs, capacitors, pyroelectric infrared sensors, optical displays, and piezoelectric transducers.

Abstract: In a semiconductor device, an opening having a high aspect ratio from a back surface of a GaAs substrate and is formed by anisotropic dry etching. After an Au film is deposited on the entire back surface of the GaAs substrate, including inside of the opening, a Ni alloy is non-electrolytically plated. The Ni film can also be deposited on the inner wall and bottom of the opening. An IC substrate or FET may have the Ni film only at an area corresponding to the via hole. The back surface of the IC substrate or FET and the front surface of a package substrate are bonded to each other by AuSn solder poorly wetting the Ni film.

Abstract: A semiconductor device having: a first interconnect or electrode formed on a substrate; an organic insulation film which is formed covering the first interconnect or electrode and in which an interconnect trench and an interlayer connection hole reaching from the interconnect trench to the first interconnect or electrode are formed; an inorganic insulation film which is formed covering the side of the interconnect trench and the interlayer connection hole, and into at least surface part of which nitrogen is introduced; a second interconnect or electrode buried into the interconnect trench through the inorganic insulation film; and a buried conductive layer which is formed in the interlayer connection hole and connects between the between the first interconnect or electrode and the second interconnect or electrode.

Abstract: A single step electroplating process for interconnect via fill and metal line formation on a semiconductor substrate is disclosed. In this process, a barrier layer is formed onto a surface of a substrate that has at least one via and then a conductive layer is formed onto the barrier layer. Next, a photoresist layer is applied and patterned on top of the conductive layer. The via plugs and metal lines are then deposited on the substrate simultaneously using an electroplating process. After the electroplating process is completed, the photoresist and the conductive layer between the deposited metal lines are removed. The process provides a simple, economical and highly controllable means of forming metal interconnect systems while avoiding the difficulties associated with depositing and patterning metal by traditional semiconductor fabrication techniques.

Abstract: A method for growing smooth metal films using a first process phase favorable to nucleation, agglomeration and initiation of smooth metal film growth and a second process phase favorable to continued smooth metal film growth, a system for performing the method, and semiconductor devices so produced.

Abstract: A method of forming a membrane for use in conjunction with a semiconductor carrier and the membrane which includes an electrically insulating substrate and an interconnect pattern formed on the substrate. A stud is coupled to the interconnect pattern over the substrate by forming a gold ball, preferably by gold ball bonding techniques, and coating a portion of the gold ball with a compliant material, preferably an epoxy resin. The coating is filled with a material having sufficient hardness to be capable of penetrating the oxide film on the contact pads of semiconductor devices. The flakes are preferably silver or silver-based.

Abstract: A method is provided for forming semiconductor copper seed layers with the copper alloyed with one of the metals from the group comprising tin, magnesium, and aluminum. The alloy further has a graded nitrogen content with the highest concentration of nitrogen proximate a tungsten nitride barrier layer. The high concentration of nitrogen in the copper alloy provides good adhesion of the seed layer to the barrier layer while the lack of nitrogen away from the barrier layer allows the copper conductive to have good adhesion with the pure copper conductive material.

Abstract: A method for fabricating semiconductor memory cells such as dynamic random access memory (DRAM) and ferroelectric random access memory (FRAM) with improved contact between the capacitor electrode and the underneath device area. It includes the following main steps of: (1) forming a first dielectric layer on a wafer surface; (2) forming at least one through opening in the first dielectric layer; (3) forming a ruthenium based plug in the through opening; and (4) forming a capacitor in contact with the ruthenium based plug. The ruthenium based plug can be made of ruthenium metal, conductive ruthenium oxide, or a stack of conductive ruthenium oxide and ruthenium metal. The method allows the memory cell to be made without the need for a barrier, which is required to protect the storage electrode from reacting with Si atoms during the fabrication process.

Abstract: A method for achieving a uniform planar surface by a chemical mechanical polish includes surrounding an active area or array to be polished with a border of the active material such that the border is wider than a single active area within the array and is preferably spaced from the outermost active area by the same distance as the distance between active areas within the array.

Abstract: An electrode for a capacitor having two electrodes and a capacitor insulation layer formed of a dielectric film sandwiched between the two electrodes, at least one of the electrodes being formed of a metal layer and a metal oxide layer, and the metal oxide layer being formed by oxidizing a surface of the metal layer on the basis of a diffusion-controlling reaction and being positioned in an interface to the capacitor insulation layer.

Abstract: The present invention discloses a method for forming a capacitor of a semiconductor device which can increase a capacitance and prevent a leakage current at the same time.

Abstract: A method is proposed for bonding a BGA (Ball Grid Array) package to a circuit board without causing the collapsing of the BGA package against the circuit board. The proposed method is characterized in the use of two groups of solder balls of different reflow collapse degrees, which are arranged in an interspersed manner among each other in the ball grid array. In one embodiment, the first group of solder balls are homogenously made of a solder material of a specific melting point; and the second group of solder balls each include an outer portion and a core portion, with the outer portion having substantially the same melting point as the first group of solder balls, and the core portion being greater in melting point than the outer portion. In another embodiment, the second group of solder balls are greater in melting point than the first group of solder balls.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. After planarization of the conductor core and the barrier layer, a plasma treatment is performed at 300° C. to reduce the conductor core material. A portion of a cap layer is deposited at 300° C. and the remainder is deposited at 400° C.

Abstract: According to one embodiment, a solid state amplifying device is disclosed. The amplifying device comprises a first input bond pad and a first input connection bonded to the first input bond pad. The amplifying device also includes a second input bond pad and a second input connection bonded to the second input bond pad. An equivalent magnitude of current is supplied to the first and second input bond pads.

Abstract: This invention relates to manufacturing of integrated circuits (ICs) and especially conductive layers suitable for use in an IC. According to the preferred method a metal oxide thin film is deposited on a substrate surface and reduced thereafter essentially into a metallic form with an organic reducing agent. The metal oxide is preferably deposited according to the principles of atomic layer deposition (ALD) using a metal source chemical and an oxygen source chemical. The reduction step is preferably carried out in an ALD reactor using one or more vaporized organic compounds that contain at least one functional group selected from the group consisting of —OH, —CHO and —COOH.

Abstract: The invention provides a polishing simulation in which calculation is proceeded while polishing rate parameter is successively updated as an offset shape of a substrate varies as polishing proceeds. When an uneven surface of a substrate is to be leveled by polishing, a deformation amount of a polishing cloth is determined on the assumption that a deformed shape of the polishing cloth by a convex of the substrate is a truncated cone, and a distribution of a polishing force is determined based on the deformation amount of the polishing cloth. Then, a distribution of a polishing amount of the substrate after a fixed interval of time is determined from the distribution of the polishing pressure, and a distribution of a height of the substrate is determined from the distribution of the polishing amount after the fixed interval of time. Finally, an expression for determination of an offset of the substrate is determined from the distribution of the height of the substrate.

Abstract: A method of forming a generally conformal iridium layer (preferably, an iridium metal layer optionally containing oxides of iridium) on a substrate, such as a semiconductor wafer, using complexes of the formula CpIr(CO)2 wherein Cp is a substituted or unsubstituted cyclopentadienyl ligand; and forming a generally conformal iridium layer on a surface of the substrate, wherein the layer is formed from the precursor composition in the presence of one or more carrier gases and one or more oxidizing gases.

Abstract: A method for use in the fabrication of integrated circuits includes providing a substrate assembly having a surface and forming a barrier layer over at least a portion of the surface. The barrier layer is formed of a platinum(x):ruthenium(1−x) alloy, where x is in the range of about 0.60 to about 0.995; preferably, x is in the range of about 0.90 to about 0.98. The barrier layer may be formed by chemical vapor deposition and the portion of the surface upon which the barrier layer is formed may be a silicon containing surface. The method is used in formation of capacitors, storage cells, contact liners, etc.

Abstract: A noble metal electrode structure having a cup-like, approximately cylindrical shape, roughened inner and outer surfaces, and a surface area of at least 1 sq. micron or greater is provided as well as a capacitor which includes the noble metal electrode as a bottom electrode. The high-surface area noble metal electrode is formed by electroplating into annular channels that have roughened sidewalls formed by the oxidation of vapor-deposited Si nuclei.

Abstract: A Ni film for a ground metal film is formed on an insulating substrate by direct current magnetron sputtering process, which prevents occurrence of minute protrusions on a surface of the ground metal film. Next, a Ni film is patterned into a specified interconnection form to obtain a patterned Ni film. Then, an anti-corrosive Au film having low resistance is formed on the patterned Ni film by electroless plating process. Further, an inexpensive Cu film having low resistance is formed on the Au film by electroplating process.