Abstract: A semiconductor manufacturing method and a semiconductor manufacturing apparatus capable of manufacturing semiconductor devices without the need of specifically determining an optimal configuration of a gas mixing chamber (6) with care or elaboration. A ruthenium raw gas feed pipe (4) and an oxygen-containing gas feed pipe (5) are merged with each other at a location upstream of a gas mixing chamber (6), so that the ruthenium raw gas and the gas containing oxygen atoms (e.g., oxygen (O2), ozone (O3), etc.) are mixed with each other prior to entering the gas mixing chamber (6).

Abstract: A method for the production of a semiconductor device having an electrode line formed in a semiconducting substrate is disclosed which comprises preparing a semiconducting substrate having trenches and/or contact holes formed preparatorily in a region destined to form the electrode line, forming a conductive film formed mainly of at least one member selected from among Cu, Ag, and Au on the surface of the semiconducting substrate, heat-treating the superposed Cu film while supplying at least an oxidizing gas thereto thereby flowing the Cu film and causing never melting to fill the trenches and/or contact holes, and removing by polishing the part of the conductive film which falls outside the region of the electrode line and completing the electrode lines consequently.

Abstract: A hard Al oxide film having a high melting point, which grows on the surface of an Al—Cu film during a wafer is carried in atmospheric air, obstructs the burying of a viahole with the Al—Cu film by high pressure reflow, with a result that a void remains in the hole. The present invention is intended to remove such an Al oxide film grown on the Al—Cu film formed by sputtering, by Ar+ sputtering/etching directly before high pressure reflow. Moreover, when a Ti oxide film is present on the surface of a Ti based underlying film formed by CVD, an Al oxide film is possibly grown at the boundary between the Ti based underlying film and an Al—Cu film laminated thereon. In this case, the Ti oxide film is similarly removed directly before formation of the Al—Cu film, thereby preventing the growth of the Al oxide film.

Abstract: A method of forming electrical contacts includes the step of implanting ions into a contact hole at an angle to create an enlarged plug enhancement region at the bottom of a contact hole. Thus, even if the contact hole is misaligned, over-sized, or over-etched, the enlarged plug enhancement region contains subsequently formed barrier layers and other conductive materials to reduce current leakage into the underlying substrate or into adjacent circuit elements.

Abstract: A semiconductor, and manufacturing method therefor, is provided with a barrier/adhesion layer, having cobalt, nickel, or palladium for semiconductors having conductive materials of copper, silver or gold. The barrier/adhesion layer can be alloyed with between about 0.2% and 4% tantalum, molybdenum, or tungsten to increase barrier effectiveness and lower resistivity.

Abstract: An underlying conductive film made of iridium and having a thickness of about 0.1 &mgr;m is formed in a contact hole formed in an insulating film covering a transistor formed in a substrate, except in the top portion of the contact hole. The underlying conductive film covers the sidewall portions of the contact hole and the top surface of the drain region but does not completely fill in the contact hole. A plug made of platinum is filled in the contact hole up to the top portion thereof. Over the contact hole of the insulating film, there is formed a capacitor composed of a lower electrode made of platinum, a capacitor insulating film made of SrBi2Ta2O9, and an upper electrode made of platinum in contact relation with the respective upper ends of the underlying conductive film and the plug.

Abstract: The present invention provides a method for forming a substantially carbon- and oxygen-free conductive layer, wherein the layer can contain a metal and/or a metalloid material. According to the present invention, a substantially carbon- and oxygen-free conductive layer is formed in an oxidizing atmosphere in the presence of an organometallic catalyst using, for example, a chemical vapor deposition process. Such layers are particularly advantageous for use in memory devices, such as dynamic random access memory (DRAM) devices.

Abstract: A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula LyRhYz is provided. Also provided is a chemical vapor co-deposited platinum-rhodium alloy barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The alloy barriers protect surrounding materials from oxidation during oxidative recrystallization steps and protect cell dielectrics from loss of oxygen during high temperature processing steps. Also provided are methods for CVD co-deposition of platinum-rhodium alloy diffusion barriers.

Abstract: A method for manufacturing a semiconductor device for use in a memory cell including the steps of preparing an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs; patterning the insulating layer into a first predetermined configuration to form contact holes; forming a diffusion barrier layer on an entire surface including the contact holes; forming a seed layer on top of the diffusion barrier layer; forming a first conductive layer and a conductive plug on top of the seed layer; carrying out a thermal treatment for changing grains of the conductive plug into a granular type; removing the first conductive layer, the diffusion barrier layer, and the seed layer until a top surface of the insulating layer is exposed; forming a second conductive layer on the conductive plug and the diffusion barrier layer; patterning the second conductive layer into a second predetermined configura

Abstract: A plasma enhanced chemical vapor deposition (PECVD) method for depositing high quality conformal tantalum nitride (TaNx) films from inorganic tantalum pentahalide (TaX5) precursors and nitrogen is described. The inorganic tantalum halide precursors are tantalum pentafluoride (TaF5), tantalum pentachloride (TaCl5) and tantalum pentabromide (TaBr5). A TaX5 vapor is delivered into a heated chamber. The vapor is combined with a process gas containing nitrogen to deposit a TaNx film on a substrate that is heated to 300° C.-500° C. The deposited TaNx film is useful for integrated circuits containing copper films, especially in small high aspect ratio features. The high conformality of these films is superior to films deposited by PVD.

Abstract: A method of forming metallic layers on a substrate includes the steps of forming a first layer including a first metal on the substrate; cooling the first layer for a period of time sufficient to suppress formation of an intermetallic phase; and forming a second layer including a second metal distinct from the first metal on the first layer. The cooling step decreases the roughness of the resultant stacked structure by suppressing the formation of an intermetallic phase layer between the two metallic layers and by suppressing “bumps” or other surface irregularities that may form at relatively reactive grain boundaries in the first layer.

Abstract: The capacitor of semiconductor devices includes a first electrode, a dielectric layer formed of a metal oxide layer including a Ta2O5 layer, and a second electrode composed of first and second metal nitride layers sequentially stacked. First and second metal nitride layers are a TiN layer and a WN layer. The second electrode of the capacitor is a double-layered structure having the first and second metal nitride layers, and thus annealing after forming the second electrode is performed at 750° C. or less to avoid increasing an equivalent oxide thickness of the dielectric layer.

Abstract: A method of forming an iridium-containing film on a substrate, such as a semiconductor wafer using complexes of the formula LyIrXz, wherein: each L group is independently a neutral or anionic ligand; each Y group is independently a pi bonding ligand selected from the group of CO, NO, CN, CS, N2, PX3, PR3, P(OR)3, AsX3, AsR3, As(OR)3, SbX3, SbR3, Sb(OR)3, NHxR3-x, CNR, and RCN, wherein R is an organic group and X is a halide; y=1 to 4; z=1 to 4; x=0 to 3.

Abstract: A dielectric layer (27) is formed between a semiconductor surface (24) and an electrical contact (26) to promote adhesion of the contact (26). The dielectric layer (27) is formed by cleaning operation followed by a chemical oxidation.

Abstract: An Ir combination film has been provided that is useful in forming an electrode of a ferroelectric capacitor. The combination film includes tantalum and oxygen, as well as iridium. The Ir combination film effectively prevents oxygen diffusion, and is resistant to high temperature annealing in oxygen environments. When used with an underlying Ta or TaN layer, the resulting conductive barrier also suppresses to diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. That is, the Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. A method for forming an Ir composite film barrier layer and Ir composite film ferroelectric electrode are also provided.

Abstract: The method and apparatus for heat treating and etching refractory metal and silicides of the refractory metal include integrated multi-chamber, multi-processing of substrates to react refractory metal and exposed silicon in self-aligned silicidation operations. Unreacted refractory metal on silicon oxide regions is selectively etched away distinctively from reacted silicide to yield highly precise self-aligned regions of silicide. Subsequent heat treatment at elevated temperatures reduces the sheet resistance of the silicide to yield highly conductive regions that are conducive to formation of conductor lines less than 0.25 &mgr;m wide.

Abstract: The semiconductor of the present invention comprises at least an oxide film and a metal thin film on the surface of the semiconductor. The metal thin film includes a metal serving as an oxidation catalyst and has a thickness in the range of 0.5-30 nm. The oxide film comprises a metal serving as an oxidation catalyst and having a thickness in the range of 1-20 nm. Thus, a high-quality oxide film can be formed on the surface of the semiconductor substrate with high controllability without conducting a high temperature heat treatment. The invention employs the method of manufacturing the semiconductor has a steps of forming the first oxidation film having thickness in the range of 0.1-2.5 nm on the semiconductor substrate; forming the metal thin film (for example platinum film) serving as an oxide catalyst to the thickness in the range of 0.5-30 nm on the first oxide thin film; and then forming the second oxide film by heat treating in an oxidizing atmosphere at temperatures from 25 to 600° C.

Abstract: The present invention relates to a method of soldering a semiconductor chip to a substrate, such as to a capsule in an RF-power transistor, for instance. The semiconductor chip is provided with an adhesion layer consisting of a first material composition. A solderable layer consisting of a second material composition is disposed on this adhesion layer. An antioxidation layer consisting of a third material composition is disposed on said solderable layer. The antioxidation layer is coated with a layer of gold-tin solder. The chip is placed on a solderable capsule surface, via said gold-tin solder. The capsule and chip are exposed to an inert environment to which a reducing gas is delivered and the capsule and chip are subjected to a pressure substantially beneath atmospheric pressure whilst the gold-tin solder is heated to a temperature above its melting point.

Abstract: A method of depositing a platinum based metal film by CVD deposition includes bubbling a non-reactive gas through an organic platinum based metal precursor to facilitate transport of precursor vapor to the chamber. The platinum based film is deposited onto a non-silicon bearing substrate in a CVD deposition chamber in the presence of ultraviolet light at a predetermined temperature and under a predetermined pressure. The film is then annealed in an oxygen atmosphere at a sufficiently low temperature to avoid oxidation of substrate. The resulting film is free of silicide and consistently smooth and has good step coverage.

Abstract: A method is provided for forming semiconductor copper seed layers with the copper alloyed with one of the metals from the group comprising tin, magnesium, and aluminum. The alloy further has a graded nitrogen content with the highest concentration of nitrogen proximate a tungsten nitride barrier layer. The high concentration of nitrogen in the copper alloy provides good adhesion of the seed layer to the barrier layer while the lack of nitrogen away from the barrier layer allows the copper conductive to have good adhesion with the pure copper conductive material.

Abstract: A method for manufacturing an integrated circuit using damascene processes is provided in which conductive material surfaces subject to chemical-mechanical polishing are passivated after polishing with a dry, low energy, ion implantation passivating process to prevent oxidation and to eliminate a high dielectric constant protective layer. In particular, copper conductive material is subject to nitrogen implantation at or below 100 KeV to produce a protective copper nitride.

Abstract: The specification describes a metal contact material optimized for diffused contacts to the buried emitter-base junction in DHBT devices. The metal contact material is a multilayer structure of Pd--Pt--Au which gives the required critical diffusion properties for low resistance contacts to the buried base layer without shorting to the collector layer.

Abstract: A wire and method of making the wire for use in conjunction with the fabrication of semiconductor devices which consists essentially of forming one of an alloy or composite of from a finite amount approaching zero to about 50 percent by weight of at least one of carbon and the metals taken from the class consisting of platinum, silver and electrically conductive base metals and the rest gold. A wire is then formed from the alloy or composite. The noble metal alloyed with gold is preferably silver and the base metals that can be used are preferably copper or aluminum.

Abstract: The specification describes source/drain contact material that is compatible with organic semiconductors in thin film transistor integrated circuits. The contact material is nickel/gold wherein the nickel is plated as Ni--P on a base conductor, preferably TiN.sub.x, by electroless plating, and the gold overlay is deposited by displacement plating. It was found, unexpectedly, that forming Ni/Au contacts in this way extends the lifetime of TFT devices substantially.

Abstract: An improved contact structure and process for forming an improved contact structure for a semiconductor device. A metal (14) is formed on a first metal layer (12) positioned on a substrate (10) The metal (14) is a Group VIIB or Group VIII metal or metal oxide and increases the electrically conductive surface area (25) of the first metal layer (12). In one embodiment, a Group VIIB or Group VIII metal layer is deposited onto the first metal layer and the Group VIIB or Group VIII metal layer is anisotropically etched to form sidewall spacers (24). An insulating layer (16) is deposited overlying the first conductive layer (12) and the sidewall spacers (24). A via opening (18) is formed in the insulation layer (16) to expose a portion of the electrically conductive surface area (25). A second metal layer (22) fills the opening (18) and forms a metallurgical contact to the first metal layer (12).

Abstract: The present invention is a method related to the deposition of a metallization layer in a trench in a semiconductor substrate. The focus of the invention is to sequentially perform heated deposition and etch unit processes to provide a good conformal film of metal on the inner surfaces of a via or trench. The deposition and etch steps can also be performed simultaneously.

Abstract: A multilayer ceramic substrate electronic component is provided having high temperature superconductor material circuitry. The high temperature superconductor material is preferably yttrium-barium-copper-oxide and is encased within a noble metal such as silver or gold when forming the surface circuitry or filling of the vias. The noble metal layers preferably have through-openings to enable direct connection of circuitry to the encased superconductor layer. A method is also provided for fabricating such multilayer ceramic substrate electronic components.

Abstract: A method for fabricating a semiconductor device using a high dielectric material as a dielectric film of a capacitor wherein an etch stopping layer such as BST having a good dry etch selectivity with respect to an interlayer insulating film is formed on the adhesion layer formed on an upper electrode. This etch stopping layer prevents the upper electrode of a capacitor from being exposed to be etched during forming a metal contact.

Abstract: A method for the production of a semiconductor device having an electrode line formed in a semiconducting substrate is disclosed which comprises preparing a semiconducting substrate having trenches and/or contact holes formed preparatorily in a region destined to form the electrode line, forming a conductive film formed mainly of at least one member selected from among Cu, Ag, and Au on the surface of the semiconducting substrate, heat-treating the superposed Cu film while supplying at least an oxidizing gas thereto thereby flowing the Cu film to fill the trenches and/or contact holes, and removing by polishing the part of the conductive film which falls outside the region of the electrode line and completing the electrode lines consequently. During the heat treatment, a reducing gas is supplied in addition to the oxidizing gas to induce a local oxidation-reduction reaction and fluidify and/or flow the conductive film and consequently accomplish the embodiment of the conductive film in the trenches.

Abstract: A palladium contact and a gasket are formed on a first wafer. The gasket and contact are simultaneously engaged with a silicon layer of a second wafer. The wafers are then heated to a temperature that both forms a bond between the palladium contact of the first wafer with the silicon layer of the second wafer and that fuses the gasket to the second wafer. Therefore, when the temperature is decreased, the palladium-silicon bond maintains the alignment of the two wafers with respect to one another, and the gasket hardens to form seal around a periphery of the two wafers. By placing the two wafers in a vacuum environment prior to engaging the two wafers, the space encompassed by the gasket and the two wafers forms a sealed vacuum during the heating process. Therefore, the heating process not only forms a palladium-silicon bond between the two wafers, but it also forms a vacuum seal around selected components included within either of the two wafers.

Abstract: Disclosed is a semiconductor device, comprising a semiconductor substrate, a cell transistor formed in the semiconductor substrate, an interlayer dielectric film in which is formed a contact hole communicating with a part of the cell transistor, a contact plug buried in the contact hole formed in the interlayer dielectric film, a capacitor lower electrode formed of a ruthenium/tantalum laminate film consisting of a tantalum film and a ruthenium film formed on the tantalum film, the lower electrode being formed on interlayer dielectric film and connected to the contact plug, a capacitor dielectric film formed on the ruthenium film included in the capacitor lower electrode and consisting of a metal oxide, and a capacitor upper electrode formed on the capacitor dielectric film, the ruthenium film exhibiting (00n) dominant orientation, where n denotes a positive integer.

Abstract: A method and substrate structure for fabricating highly conductive components on microelectronic devices. In one embodiment in accordance with the principles of the present invention, a first dielectric layer is formed over a base layer of a substrate, a second dielectric layer is deposited onto the first dielectric layer, and a third dielectric layer is deposited onto the second dielectric layer. The first, second and third dielectric layers define a dielectric stratum in which the first and second dielectric layers may be selectively etchable from one another so that the second dielectric layer etches at a faster rate than the first layer in the presence of a selective etchant. After the dielectric layers are deposited onto the substrate, a void is etched through the second and third dielectric layers.

Abstract: A method for fabricating highly integrated semiconductor devices with capacitors having a dielectric film comprised of a thin film exhibiting a high dielectric constant to obtain a sufficient capacitance, involving the formation of an under electrode over a wafer formed with an oxide film at a high temperature, and annealing the resulting wafer in a vacuum such that the under electrode has a tight and smooth structure. By virtue of the tight and smooth structure of the under electrode, subsequent processing steps can be easily carried out. It is also possible to achieve an improvement in the reliability and uniformity of semiconductor devices as well as a high integration of such semicoductor devices.

Abstract: The present invention relates to a method of depositing a platinum thin-film on a silicon wafer. The method includes the steps of depositing a platinum layer on an insulating oxide layer under an oxidation atmosphere to form a mixture film consisted of platinum grains, platinum oxide grains and oxygen adhered to those grains (hereinafter, "the mixture film" to be referred as "oxygen containing platinum thin-film"); depositing an additional platinum thin-film to a desired thickness on the oxygen containing platinum thin-film under a complete inert atmosphere; and annealing the silicon substrate at a temperature of 400 to 1,300.degree. C. in order to remove oxygen present in the independent form or in platinum oxide form within the oxygen containing platinum thin-film and to stabilize the entire platinum thin-film.

Abstract: Disclosed is a method for forming a silicide film on bit lines or word lines in a semiconductor device. The method includes the steps of: placing a substrate within a reacting chamber, the substrate having an objective layer on which a metal silicide film is to be formed; and supplying a first source gas for silicon component of the metal silicide and a second source gas for metal component of the metal silicide into the reacting chamber with maintaining a flow rate of the first source gas and with varying a flow rate of the second source gas, wherein the first and second source gases are discretely supplied into the reacting chamber, a reacting zone of the reacting chamber being maintained at a constant temperature range for a selected time.

Abstract: Two metallization schemes of PtSi/TiW/TiW(N)/Au (Type I) and PtSi/TiW/TiW(N)/TiW/Au (Type II) and associated process are described for microcircuit interconnections. The metallization schemes and process are capable of IC-interconnections with a metal-pitch as small as 1.5 .mu.m, or even smaller. The metallization schemes are reliable for continuous high temperature and high current operations.

Abstract: A method for forming a dynamic random access memory device includes the step of forming a memory cell access transistor on a semiconductor substrate wherein the memory cell access transistor includes a source/drain region at a surface of the semiconductor substrate. An insulating layer is formed on the semiconductor substrate and on the memory cell access transistor wherein the insulating layer has a contact hole therein exposing a portion of the source/drain region of the substrate. A first conductive layer is chemical vapor deposited on the exposed portion of the source/drain region of the substrate, and a second conductive layer is physical vapor deposited on the first conductive layer opposite the substrate. A dielectric layer is formed on the second conductive layer opposite the substrate, and a third conductive layer is formed on the dielectric layer opposite the substrate.

Abstract: Methods of forming integrated circuit capacitors include the steps of forming an electrically insulating layer having a contact hole therein, on a face of a semiconductor substrate and then forming a polysilicon contact plug in the contact hole. A first capacitor electrode is then formed in electrical contact with the polysilicon contact plug. The first capacitor electrode may be formed by etching a composite of a diffusion barrier metal layer containing a nitride material (or silicide material) and a first electrically conductive layer. Alternatively, the first capacitor electrode may be formed by etching the diffusion barrier metal layer without the first electrically conductive layer thereon. The diffusion barrier metal layer inhibits parasitic migration of silicon from the polysilicon plug to the first electrically conductive layer. A protective layer of a preferred material is then electroplated onto an upper surface and on sidewalls of the first capacitor electrode.

Abstract: A thin film (at least one atomic layer to about 400 .ANG.) of nickel is electrolytically plated on top of electrolytically-plated gold electrodes in GaAs monolithic microwave integrated circuits (MMICs) without any additional photoresist masking step. The thin electrolytically-plated nickel film improves adhesion of a passivating dielectric layer (e.g., silicon dioxide, silicon nitride, and silicon oxynitride) formed on the electrolytically-plated gold electrodes. The electrolytically-plated nickel film can be removed locally to facilitate the fabrication of plated silver bumps (for off-chip electrical connections and thermal paths) on passivated flip chip MMICs.

Abstract: A thin-film microcircuit comprising fabricating a substrate of high-purity, densely packed alumina ceramic with a fine grain size, and metallization deposited thereon and applying a vacuum anneal to the metallization.

Abstract: A ceramic substrate having on the surface thereof a plurality of pads to be attached to terminal members is provided. Each pad includes a metallic layer formed on the surface of the substrate and a connecting layer made of a nickel base alloy and formed on the metallic layer. A gold-nickel layer made of a gold base alloy containing nickel is formed on the connecting layer. The gold-nickel layer may be formed by first forming a gold layer on the connecting layer and then making nickel in the connecting layer to diffuse into the gold layer by heat treatment. A method of producing such a ceramic substrate is also provided.

Abstract: Noble metal plating on a preexisting seed layer is used in the fabrication of electrodes for DRAM and FRAM. The plating may be spatially selective or nonselective. In the nonselective case, a blanket film is first plated and then patterned after deposition by spatially selective material removal. In the selective case, the plated deposits are either selectively grown in lithographically defined areas by a through-mask plating technique, or selectively grown as a conformal coating on the exposed regions of a preexisting electrode structure. A diamond-like carbon mask can be used in the plating process. A self-aligned process is disclosed for selectively coating insulators in a through-mask process.

Abstract: A circuit pattern 2a, made of copper foil, is arranged on a substrate 1. A nickel-containing barrier metal layer 2b is formed on the.circuit pattern 2a. A gold layer 2c is formed on the barrier metal layer 2b by electroless substitution plating. Then, substrate 1 is heated up to impel nickel contained in the gold layer 2c to move toward a surface zone of the gold layer 2c to deposit nickel compound in the surface zone of the gold layer 2c, thereby enhancing the fineness of a remaining part of the gold layer 2c at at least an inside zone immediately below the surface zone. Then, the surface zone containing the crowded nickel compound is removed off the gold layer 2c so as to expose a purified surface of the inside zone of the gold layer 2c. Therefore, it becomes possible to form an excellent electrode having satisfactory bondability to the wire by using a less amount of gold at low costs.

Abstract: A process for producing components having a contact structure provides for vertical contact-making, in which, for the connection of a metal contact of a first component to a metal contact of a second component, the substrate is etched out, starting from the top, in a region provided for a vertical, conductive connection, this recess is filled with a metal so that said metal is connected to the surface of the metal contact, the rear side of the substrate is removed until the metal projects beyond the rear side, a metallization layer made of a metal having a low melting point, for example AuIn, is applied to the metal contact of the second component, the surface of the second component is provided with a planar layer, the two components are arranged vertically with respect to one another and a permanent contact is produced between the metal of the first component and the metallization layer of the second component by pressing one onto the other and heating.

Abstract: The present invention provides a semiconductor device including an improved buried electrode formed by selective CVD. In this semiconductor device, a first insulation layer is formed on a semiconductor substrate. A first conductive layer is formed along an inner surface of a recess of an opening formed on the first insulation layer. A second conductive layer is formed on the first conductive layer in the recess of the opening. The second conductive layer is flush with the first insulation layer. The surfaces of the first and second conductive layers are coated with a third conductive layer. A second insulation layer is formed on the first insulation layer and the third conductive layer. A via hole is formed through the second insulation layer and the third conductive layer and reaches to the second conductive layer. A buried electrode layer is grown in the via hole and formed in contact with the second conductive layer.

Abstract: In a semiconductor device having gold interconnections for connecting elements formed on a substrate with each other, the improvement is that the average dimension of gold grains constituting the gold interconnections is determined to be 0.17 through 0.25 times as large as width of the gold interconnections. In addition, the average dimension of the gold grains is determined so that the mean time to failure is not less than a predetermined period of time.

Abstract: In a semiconductor device and a method for manufacturing the same according to the present invention, for example, an insulating film is deposited on a silicon substrate, and a concave groove is formed in the insulating film in accordance with a predetermined wiring pattern. Titanium and palladium are deposited in sequence on the insulating film to form a titanium film and a palladium film, respectively. A silver film is formed on the palladium film by electroplating, and a groove-shaped silver wiring layer is formed by polishing. The resultant structure is annealed at a temperature of about 700.degree. C., and an intermetallic compound is formed by alloying the titanium film and palladium film with each other. Consequently, a burying type wiring layer whose resistance is lower than that of aluminum, is constituted by the silver wiring layer and intermetallic compound.