Having Refractory Group Metal (i.e., Titanium (ti), Zirconium (zr), Hafnium (hf), Vanadium (v), Niobium (nb), Tantalum (ta), Chromium (cr), Molybdenum (mo), Tungsten (w), Or Alloy Thereof) Patents (Class 438/656)
  • Patent number: 10316410
    Abstract: A method of filling recesses in a substrate with tungsten includes preparing the substrate within a chamber of a film forming apparatus, performing a first cycle at least once, the first cycle comprising introducing a tungsten-containing precursor gas into the chamber, purging the chamber, introducing a hydrogen-containing gas into the chamber, and purging the chamber, and performing a second cycle at least once after the first cycle is performed at least once, the second cycle comprising introducing the tungsten-containing precursor gas into the chamber, purging the chamber, introducing the hydrogen-containing gas into the chamber, and purging the chamber. A pressure in the chamber when the second cycle is performed is set to a pressure lower than a pressure in the chamber when the first cycle is performed.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: June 11, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kensaku Narushima, Katsumasa Yamaguchi
  • Patent number: 10211211
    Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a barrier layer in the trench; performing a soaking process to reduce chlorine concentration in the barrier layer; and forming a conductive layer to fill the trench.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: February 19, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Kai-Jiun Chang, Yi-Wei Chen, Tsun-Min Cheng, Chia-Chen Wu, Pin-Hong Chen, Chih-Chieh Tsai, Tzu-Chieh Chen, Yi-An Huang
  • Patent number: 9773709
    Abstract: A method of making a semiconductor device includes forming a first trench contact over a first source/drain region of a first transistor; forming a second trench contact over a second source/drain region of a second transistor; depositing a first liner material within the first trench contact; and depositing a second liner material within the second trench contact; wherein the first liner material and the second liner material include different materials.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: September 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Zuoguang Liu, Tenko Yamashita
  • Patent number: 9406554
    Abstract: A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to a first pulse of a nitrogen-rich plasma to form a first TiN layer with a first nitrogen concentration making a lower portion of the TiN diffusion barrier, the first nitrogen concentration of the first TiN layer is increased by the first pulse of the nitrogen-rich plasma reducing a reactivity of the lower portion of the TiN diffusion barrier to prevent fluorine diffusion. The first TiN layer is exposed to second pulses of the titanium-containing precursor and the nitrogen-rich plasma to form a second TiN layer with a second nitrogen concentration above the first TiN layer making an upper portion of the TiN diffusion barrier, the first pulse of the nitrogen-rich plasma has a substantially longer duration than the second pulse of the nitrogen-rich plasma.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: August 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: Brett H. Engel, Domingo A. Ferrer, Arun Vijayakumar, Keith Kwong Hon Wong
  • Patent number: 9337089
    Abstract: A semiconductor device includes a semiconductor substrate having an active region defined by an isolation layer, a gate line defining a bit line contact region in the active region and extending in one direction, and a dielectric layer covering the semiconductor substrate and the gate line formed in the semiconductor substrate. The semiconductor device is provided with a bit line contact hole formed in the dielectric layer and exposing the bit line contact region. In order to alleviate a self-aligned contact (SAC) fails caused by a conductive material remaining in a contact hole, the semiconductor device contains a bit line contact spaced apart from a sidewall of the bit line contact hole and formed in the bit line contact hole.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: May 10, 2016
    Assignee: SK Hynix Inc.
    Inventor: Hyun-Shik Cho
  • Patent number: 9230857
    Abstract: A method of forming a semiconductor device is disclosed. The method including providing a substrate with at least one insulating layer disposed thereon, the at least one insulating layer including a trench; forming at least one liner layer on the at least one insulating layer; forming a nucleation layer on the at least one liner layer; forming a first metal film on a surface of the nucleation layer; etching the first metal film; and depositing a second metal film on the etched surface of the first metal film, the second metal film substantially forming an overburden above the trench.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: January 5, 2016
    Assignees: International Business Machines Corporation, St. Microelectronics Inc.
    Inventors: Lindsey H. Hall, Michael Hatzistergos, Ahmet S. Ozcan, Filippos Papadatos, Yiyi Wang
  • Patent number: 9040416
    Abstract: A manufacturing method of a wire including: forming a lower layer on a substrate; forming a middle layer on the lower layer; forming an upper layer on the middle layer; forming, exposing, and developing a photoresist layer on the upper layer to form a photoresist pattern; and etching the upper layer, the middle layer, and the lower layer by using the photoresist pattern as a mask to form a wire such that the upper layer covers an end of the middle layer.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 26, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Dong-Jin Son
  • Patent number: 9041118
    Abstract: A CMOS device that includes an nFET portion, a pFET portion and an interlayer dielectric between the nFET portion and pFET portion. The nFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer in direct physical contact with the barrier layer and a gate metal filling the remainder of the recess. The pFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer on the barrier layer, a third titanium nitride layer in direct physical contact with the second titanium nitride layer and a gate metal filling the remainder of the recess.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: May 26, 2015
    Assignees: International Business Machines Corporation, Global Foundries, Inc
    Inventors: Takashi Ando, Kisik Choi, Vijay Narayanan
  • Patent number: 9034760
    Abstract: Methods, apparatus, and systems for depositing tensile or compressive tungsten films are described. In one aspect, a method includes providing a substrate to a chamber. The substrate has a field region and a feature recessed from the field region. Then, the substrate is exposed to an organometallic tungsten precursor. The organometallic tungsten precursor not adsorbed onto the substrate is removed from the chamber. The substrate is treated with a first treatment including a heat treatment or a plasma treatment to form a tungsten layer on the substrate. After treating the substrate, residual gasses are removed from the chamber. The tungsten layer on the substrate is treated with a second treatment including a heat treatment or a plasma treatment.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: May 19, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Feng Chen, Tsung-Han Yang, Juwen Gao, Roey Shaviv, Raashina Humayun, Deqi Wang
  • Publication number: 20150118842
    Abstract: Methods of fabricating a semiconductor device are described. The method includes forming a patterned oxide layer having a plurality of openings over a substrate, depositing a metal layer in the openings to form metal plugs, depositing a global transformable (GT) layer on the oxide layer and the metal plugs, and depositing a capping layer directly on the GT layer without exposing the GT layer to ambient air. The GT layer on the oxide layer transforms into a dielectric oxide and the GT layer on the metal plugs remains conductive during deposition of the capping layer.
    Type: Application
    Filed: October 25, 2013
    Publication date: April 30, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ya-Lien Lee
  • Patent number: 9018750
    Abstract: Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact with the titanium thin film outer layer of the metal stack seed layer, the resist layer forming circuitry. A method for manufacturing a package is further disclosed. A metal stack seed layer having a titanium thin film outer layer is formed. A resist layer is formed so as to be in contact with the titanium thin film outer layer of the metal stack seed layer, and circuitry is formed from the resist layer.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: April 28, 2015
    Assignee: Flipchip International, LLC
    Inventors: Robert Forcier, Douglas Scott
  • Publication number: 20150084198
    Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ?1 and the core material exhibits a second resistivity ?2 and ?2 is less than ?1.
    Type: Application
    Filed: September 26, 2013
    Publication date: March 26, 2015
    Inventors: HUI JAE YOO, TEJASWI K. INDUKURI, RAMANAN V. CHEBIAM, JAMES S. CLARKE
  • Patent number: 8980742
    Abstract: Provided are methods and apparatuses for manufacturing a multilayer metal thin film without additional heat treatment processes. The method of manufacturing a multilayer metal thin film including steps of: (a) forming a first metal layer on a substrate by flowing a first metal precursor into a first reaction container; and (b) forming a second metal layer on the first metal layer by flowing a second metal precursor into a second reaction container, wherein the step (b) is performed in a range of a heat treatment temperature of the first metal layer so that the second metal layer is formed as the first metal layer is heat-treated.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: March 17, 2015
    Assignee: Wonik IPS Co., Ltd.
    Inventors: Jung Wook Lee, Young Hoon Park
  • Patent number: 8980743
    Abstract: A wafer level semiconductor device and manufacturing method including providing a semiconductor device wafer substrate having a backside, applying to the backside a conductive metallization layer, and applying to the backside over the conductive metallization layer a protective metal layer of titanium, titanium alloys, nickel, nickel alloys, chromium, chromium alloys, cobalt. cobalt alloys, palladium, and palladium alloys.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: March 17, 2015
    Assignee: FlipChip International LLC
    Inventors: Guy F. Burgess, Shannon D. Buzard, Anthony P. Curtis, Douglas M. Scott
  • Patent number: 8981332
    Abstract: A nonvolatile resistive memory element includes an oxygen-gettering layer. The oxygen-gettering layer is formed as part of an electrode stack, and is more thermodynamically favorable in gettering oxygen than other layers of the electrode stack. The Gibbs free energy of formation (?fG°) of an oxide of the oxygen-gettering layer is less (i.e., more negative) than the Gibbs free energy of formation of an oxide of the adjacent layers of the electrode stack. The oxygen-gettering layer reacts with oxygen present in the adjacent layers of the electrode stack, thereby preventing this oxygen from diffusing into nearby silicon layers to undesirably increase an SiO2 interfacial layer thickness in the memory element and may alternately be selected to decrease such thickness during subsequent processing.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 17, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Tony P. Chiang, Dipankar Pramanik, Milind Weling
  • Publication number: 20150069580
    Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.
    Type: Application
    Filed: November 14, 2014
    Publication date: March 12, 2015
    Inventors: Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Fang Wen Tsai, Weng-Jin Wu, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 8975184
    Abstract: Methods of filling features with low-resistivity tungsten layers having good fill without use of a nucleation layer are provided. In certain embodiments, the methods involve an optional treatment process prior to chemical vapor deposition of tungsten in the presence of a high partial pressure of hydrogen. According to various embodiments, the treatment process can involve a soaking step or a plasma treatment step. The resulting tungsten layer reduces overall contact resistance in advanced tungsten technology due to elimination of the conventional tungsten nucleation layer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: March 10, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Feng Chen, Tsung-Han Yang, Juwen Gao, Michal Danek
  • Patent number: 8975180
    Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: March 10, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Thomas R. Boussie, David E. Lazovsky, Sandra G. Malhotra
  • Patent number: 8969195
    Abstract: Processes for improving adhesion of films to semiconductor wafers and a semiconductor structure are provided. By implementing the processes of the invention, it is possible to significantly suppress defect creation, e.g., decrease particle generation, during wafer fabrication processes. More specifically, the processes described significantly reduce flaking of a TaN film from edges or extreme edges (bevel) of the wafer by effectively increasing the adhesion properties of the TaN film on the wafer. The method increasing a mol percent of nitride with respect to a total tantalum plus nitride to 25% or greater during a barrier layer fabrication process.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Felix P. Anderson, Steven P. Barkyoumb, Edward C. Cooney, III, Thomas L. McDevitt, William J. Murphy, David C. Strippe
  • Patent number: 8969196
    Abstract: A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Ho Park, Gil-Heyun Choi, Byung-Lyul Park, Jong-Myeong Lee, Zung-Sun Choi, Hye-Kyung Jung
  • Publication number: 20150048383
    Abstract: An Ni2Si layer and a TiC layer formed by sintering after deposition of a thin layer including Ni and a thin layer including Ti on a silicon carbide substrate have a structure in which the TiC layer is precipitated on a surface of the Ni2Si layer. A multilayer thin film including a Ti layer as a first thin film and an Ni layer as a second thin film is formed on the TiC layer surface in the structure. A TiC-derived C composition ratio is set to 15% or more at an interface between the TiC layer and the Ti layer of the multilayer thin film. As a result, a silicon carbide semiconductor element can be provided without occurrence of peeling after wafer dicing and subsequent picking up by a dicing tape.
    Type: Application
    Filed: March 18, 2013
    Publication date: February 19, 2015
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Tsuji, Akimasa Kinoshita, Kenji Fukuda
  • Patent number: 8956972
    Abstract: A method for manufacturing a semiconductor thick metal structure includes a thick metal deposition step, a metal patterning step, and a passivation step. In the thick metal deposition step, a Ti—TiN laminated structure is used as an anti-reflection layer to implement 4 ?m metal etching without residue. In the metal patterning step, N2 is used for the protection of a sidewall to implement on a 4 ?m metal concave-convex structure a tilt angle of nearly 90 degrees, and a main over-etching step is added to implement the smoothness of the sidewall of the 4 ?m metal concave-convex structure. A half-filled passivation filling structure is used to implement effective passivation protection of 1.5 um metal gaps having less than 4 um of metal thickness. Manufacturing of the 4 ?m thick metal structure having a linewidth/gap of 1.5 ?m/1.5 ?m is finally implemented.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: February 17, 2015
    Assignee: CSMC Technologies Fab1 Co., Ltd.
    Inventors: Hsiao-Chia Wu, Shilin Fang, Tse-Huang Lo, Zhengpei Chen, Shu Zhang
  • Patent number: 8946082
    Abstract: Embodiments of methods for forming a semiconductor device are provided. The method includes forming a metal layer overlying a dielectric material. A thickness of the metal layer is reduced including oxidizing an exposed outer portion of the metal layer to form a metal oxide portion overlying a remaining portion of the metal layer and removing the metal oxide portion.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: February 3, 2015
    Assignee: Globalfoundries, Inc.
    Inventor: Errol T. Ryan
  • Patent number: 8946047
    Abstract: A method for fabricating a capacitor includes: forming a storage node contact plug over a substrate; forming an insulation layer having an opening exposing a surface of the storage node contact plug over the storage contact plug; forming a conductive layer for a storage node over the insulation layer and the exposed surface of the storage node contact plug through two steps performed at different temperatures; performing an isolation process to isolate parts of the conductive layer; and sequentially forming a dielectric layer and a plate electrode over the isolated conductive layer.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: February 3, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jin-Hyock Kim, Seung-Jin Yeom, Ki-Seon Park, Han-Sang Song, Deok-Sin Kil, Jae-Sung Roh
  • Patent number: 8941091
    Abstract: A semiconductor device includes a gate electrode which is formed on a substrate, and contains Al and Zr, a gate insulating film which is formed to cover at least the upper surface of the gate electrode, and contains Al and Zr, and an insulator layer formed on the substrate to surround the gate electrode.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: January 27, 2015
    Assignee: National University Corporation Tohoku University
    Inventor: Tadahiro Ohmi
  • Publication number: 20150017801
    Abstract: One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a substrate; forming a dielectric layer over the substrate; forming a first opening and a second opening at least partially simultaneously through the dielectric layer over the substrate; and forming a third opening through the bottom surface of the first opening and into at least a portion of the substrate.
    Type: Application
    Filed: September 2, 2014
    Publication date: January 15, 2015
    Inventors: Gunther MACKH, Uwe SEIDEL, Rainer LEUSCHNER
  • Publication number: 20140377949
    Abstract: The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50.degree. C. or less, with the deposition taking place at a power level of 300 W or less.
    Type: Application
    Filed: June 25, 2014
    Publication date: December 25, 2014
    Inventors: Wen YU, Stephen B. ROBIE, Jeremias D. ROMERO
  • Publication number: 20140377948
    Abstract: The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50.degree. C. or less, with the deposition taking place at a power level of 300 W or less.
    Type: Application
    Filed: June 24, 2014
    Publication date: December 25, 2014
    Inventors: Wen YU, Stephen B. ROBIE, Jeremias D. ROMERO
  • Patent number: 8907484
    Abstract: According to an embodiment, a semiconductor device, includes a substrate, an inter-layer insulating layer provided above the substrate, a first interconnect provided in a first trench, and a second interconnect provided in a second trench. The first interconnect is made of a first metal, and the first trench is provided in the inter-layer insulating layer on a side opposite to the substrate. The second interconnect is made of a second metal, and the second trench is provided in the inter-layer insulating layer toward the substrate. A width of the second trench is wider than a width of the first trench. A mean free path of electrons in the first metal is shorter than a mean free path of electrons in the second metal, and the first metal is a metal, an alloy or a metal compound, including at least one nonmagnetic element as a constituent element.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: December 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Kitamura, Atsuko Sakata, Takeshi Ishizaki, Satoshi Wakatsuki
  • Publication number: 20140353832
    Abstract: An object is to use an electrode made of a less expensive material than gold (Au). A semiconductor device comprises: a first titanium layer that is formed to cover at least part of a semiconductor layer and is made of titanium; an aluminum layer that is formed on the first titanium layer on opposite side of the semiconductor layer and mainly consists of aluminum; a titanium nitride layer that is formed on the aluminum layer on opposite side of the first titanium layer and is made of titanium nitride; and an electrode layer that is formed on the titanium nitride layer on opposite side of the aluminum layer and is made of copper.
    Type: Application
    Filed: May 16, 2014
    Publication date: December 4, 2014
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Noriaki Murakami, Toru Oka
  • Patent number: 8900899
    Abstract: Novel processing methods for production of high-refractive index contrast and low loss optical waveguides are disclosed. In one embodiment, a “channel” waveguide is produced by first depositing a lower cladding material layer with a low refractive index on a base substrate, a refractory metal layer, and a top diffusion barrier layer. Then, a trench is formed with an open surface to the refractory metal layer. The open surface is subsequently oxidized to form an oxidized refractory metal region, and the top diffusion barrier layer and the non-oxidized refractory metal region are removed. Then, a low-refractive-index top cladding layer is deposited on this waveguide structure to encapsulate the oxidized refractory metal region. In another embodiment, a “ridge” waveguide is produced by using similar process steps with an added step of depositing a high-refractive-index material layer and an optional optically-transparent layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: December 2, 2014
    Inventor: Payam Rabiei
  • Publication number: 20140346568
    Abstract: The disclosure relates to a method for manufacturing an Au-free ohmic contact for an III-nitride (III-N) device on a semiconductor substrate and to a III-N device obtainable therefrom. The III-N device includes a buffer layer, a channel layer, a barrier layer, and a passivation layer. A 2DEG layer is formed at an interface between the channel layer and the barrier layer. The method includes forming a recess in the passivation layer and in the barrier layer up to the 2DEG layer, and forming an Au-free metal stack in the recess. The metal stack comprises a Ti/Al bi-layer, with a Ti layer overlying and in contact with a bottom of the recess, and a Al layer overlying and in contact with the Ti layer. A thickness ratio of the Ti layer to the Al layer is between 0.01 to 0.1. After forming the metal stack, a rapid thermal anneal is performed. Optionally, prior to forming the Ti/Al bi-layer, a silicon layer may be formed in contact with the recess.
    Type: Application
    Filed: May 22, 2014
    Publication date: November 27, 2014
    Applicant: IMEC
    Inventors: Brice De Jaeger, Marleen Van Hove, Stefaan Decoutere
  • Patent number: 8895434
    Abstract: A method of fabricating a replacement metal gate structure for a CMOS device including forming a dummy gate structure on an nFET portion and a pFET portion of the CMOS device; depositing an interlayer dielectric between the dummy gate structures; removing the dummy gate structures from the nFET and pFET portions, resulting in a recess on the nFET portion and a recess on the pFET portion; conformally depositing a gate dielectric into the recesses on the nFET and pFET portions; depositing sequential layers of a first titanium nitride, tantalum nitride and a second titanium nitride into the recesses on the nFET and pFET portions; removing the second layer of titanium nitride from the nFET portion only; depositing a third layer of titanium nitride into the recesses on the nFET and pFET portions; and filling the remainder of the cavity on the nFET and pFET portions with a metal.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: November 25, 2014
    Assignees: International Business Machines Corporation, Global Foundries Inc
    Inventors: Takashi Ando, Kisik Choi, Vijay Narayanan
  • Patent number: 8896136
    Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: November 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Fang Wen Tsai, Weng-Jin Wu, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Publication number: 20140339702
    Abstract: Structures and methods of forming the same are disclosed herein. In one embodiment, a structure can comprise a region having first and second oppositely facing surfaces. A barrier region can overlie the region. An alloy region can overlie the barrier region. The alloy region can include a first metal and one or more elements selected from the group consisting of silicon (Si), germanium (Ge), indium (Id), boron (B), arsenic (As), antimony (Sb), tellurium (Te), or cadmium (Cd).
    Type: Application
    Filed: May 20, 2013
    Publication date: November 20, 2014
    Applicant: INVENSAS CORPORATION
    Inventors: Charles G. Woychik, Cyprian Emeka Uzoh, Michael Newman, Pezhman Monadgemi, Terrence Caskey
  • Publication number: 20140335691
    Abstract: A manufacturing method of a wire including: forming a lower layer on a substrate; forming a middle layer on the lower layer; forming an upper layer on the middle layer; forming, exposing, and developing a photoresist layer on the upper layer to form a photoresist pattern; and etching the upper layer, the middle layer, and the lower layer by using the photoresist pattern as a mask to form a wire such that the upper layer covers an end of the middle layer.
    Type: Application
    Filed: September 5, 2013
    Publication date: November 13, 2014
    Applicant: Samsung Display Co., Ltd.
    Inventor: Dong-Jin SON
  • Publication number: 20140332776
    Abstract: A manufacturing method of a wire including: forming a lower layer on a substrate; forming a middle layer on the lower layer; forming an upper layer on the middle layer; forming, exposing, and developing a photoresist layer on the upper layer to form a photoresist pattern; and etching the upper layer, the middle layer, and the lower layer by using the photoresist pattern as a mask to form a wire such that the upper layer covers an end of the middle layer.
    Type: Application
    Filed: March 21, 2014
    Publication date: November 13, 2014
    Applicant: Samsung Display Co., Ltd.
    Inventors: Su Yeon YUN, Dong Jin SON
  • Publication number: 20140335692
    Abstract: The present invention provides a method for forming a resist under layer film used in a lithography process, comprising: a process for applying a composition for forming a resist under layer film containing an organic compound having an aromatic unit on a substrate; and a process for heat-treating the resist under layer film applied in an atmosphere whose oxygen concentration is 10% or more at 150° C. to 600° C. for 10 to 600 seconds after heat-treating the same in an atmosphere whose oxygen concentration is less than 10% at 50 to 350° C. There can be provided a method for forming a resist under layer film having excellent filling/flattening properties so that unevenness on a substrate can be flattened even in complex processes such as multi-layer resist method and double patterning.
    Type: Application
    Filed: April 15, 2014
    Publication date: November 13, 2014
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Shiori NONAKA, Seiichiro TACHIBANA, Daisuke KORI, Toshihiko FUJII, Tsutomu OGIHARA
  • Patent number: 8883633
    Abstract: Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, flouroalkyl groups, heteroarlyl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: November 11, 2014
    Assignee: Intermolecular, Inc.
    Inventors: David E. Lazovsky, Tony P. Chiang, Majid Keshavarz
  • Patent number: 8883637
    Abstract: A method for filling a recessed feature of a substrate includes a) at least partially filling a recessed feature of a substrate with tungsten-containing film using at least one of chemical vapor deposition (CVD) and atomic layer deposition (ALD); b) at a predetermined temperature, using an etchant including activated fluorine species to selectively etch the tungsten-containing film more than an underlying material of the recessed feature without removing all of the tungsten-containing film at a bottom of the recessed feature; and c) filling the recessed feature using at least one of CVD and ALD.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: November 11, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Esther Jeng, Anand Chandrashekar, Raashina Humayun, Michal Danek, Ronald Powell
  • Publication number: 20140327142
    Abstract: Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.
    Type: Application
    Filed: October 18, 2012
    Publication date: November 6, 2014
    Inventors: Walter A Harrison, Paul A. Clifton, Andreas Goebel, R. Stockton Gaines
  • Publication number: 20140327018
    Abstract: It is an object of the present invention to provide a power semiconductor device, which is capable of being operable regardless of thermal stress generation, reducing a heat generation from wire, securing the reliability of bonding portion when the device is used for dealing with a large amount current and/or under a high temperature atmosphere, a method of manufacturing the device and a bonding wire. In a power semiconductor device in which a metal electrode (die electrode 3) on a power semiconductor die 2 and another metal electrode (connection electrode 4) are connected by metal wire 5 using wedge bonding connection, the metal wire is Ag or Ag alloy wire of which diameter is greater than 50 ?m and not greater than 2 mm and the die 3 has thereon one or more metal and/or alloy layers, each of the layer(s) being 50 ? or more in thickness and a metal for the layer is selected from Ni, Cr, Cu, Pd, V, Ti, Pt, Zn, Ag, Au, W and Al.
    Type: Application
    Filed: February 22, 2013
    Publication date: November 6, 2014
    Inventors: Kohei Tatsumi, Takashi Yamada, Daizo Oda
  • Patent number: 8865594
    Abstract: The invention provides a method of forming a film stack on a substrate, comprising performing a silicon containing gas soak process to form a silicon containing layer over the substrate, reacting with the silicon containing layer to form a tungsten silicide layer on the substrate, depositing a tungsten nitride layer on the substrate, subjecting the substrate to a nitridation treatment using active nitrogen species from a remote plasma, and depositing a conductive bulk layer directly on the tungsten nitride layer.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: October 21, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Sang-Hyeob Lee, Sang Ho Yu, Kai Wu
  • Publication number: 20140308766
    Abstract: A contact to a semiconductor including sequential layers of Cr, Ti, and Al is provided, which can result in a contact with one or more advantages over Ti/Al-based and Cr/Al-based contacts. For example, the contact can: reduce a contact resistance; provide an improved surface morphology; provide a better contact linearity; and/or require a lower annealing temperature, as compared to the prior art Ti/Al-based contacts.
    Type: Application
    Filed: June 27, 2014
    Publication date: October 16, 2014
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Remigijus Gaska, Xuhong Hu, Michael Shur
  • Patent number: 8860147
    Abstract: One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: October 14, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Amitava Chatterjee, Howard Tigelaar, Victor Sutcliffe
  • Patent number: 8858763
    Abstract: Disclosed are apparatus and method embodiments for achieving etch and/or deposition selectivity in vias and trenches of a semiconductor wafer. That is, deposition coverage in the bottom of each via of a semiconductor wafer differs from the coverage in the bottom of each trench of such wafer. The selectivity may be configured so as to result in punch through in each via without damaging the dielectric material at the bottom of each trench or the like. In this configuration, the coverage amount deposited in each trench is greater than the coverage amount deposited in each via.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: October 14, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Erich R. Klawuhn, Robert Rozbicki, Girish A. Dixit
  • Patent number: 8853075
    Abstract: Methods of forming titanium-containing layers on substrates are disclosed. In the disclosed methods, the vapor of a precursor compound having the formula Ti(Me5Cp)(OR)3, wherein R is selected from methyl, ethyl, or isopropyl is provided. The vapor is reacted with the substrate according to an atomic layer deposition process to form a titanium-containing complex on the surface of the substrate.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: October 7, 2014
    Assignee: L'Air Liquide Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude
    Inventors: Satoko Gatineau, Christian Dussarrat, Christophe Lachaud, Nicolas Blasco, Audrey Pinchart, Ziyun Wang, Jean-Marc Girard, Andreas Zauner
  • Publication number: 20140295664
    Abstract: One illustrative method disclosed herein includes forming a seed layer above a structure, forming a nucleation layer on the seed layer, forming a plurality of spaced-apart, vertically oriented alloy structures that are comprised of materials from the seed layer and the nucleation layer, forming a sacrificial material layer above the nucleation layer and around the alloy structures, performing an etching process to remove the alloy structures and portions of the seed layer so as to thereby define a plurality of openings, forming an initial masking structure in each of the openings, performing an etching process to remove the sacrificial material layer and the nucleation layer so as to thereby expose the structure and define a masking layer comprised of the initial masking structures, and performing at least one process operation on the structure through the masking layer.
    Type: Application
    Filed: March 28, 2013
    Publication date: October 2, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventor: Manfred Heinrich Moert
  • Patent number: 8835310
    Abstract: Electrodes, which contain molybdenum dioxide (MoO2) can be used in electronic components, such as memory or logic devices. The molybdenum-dioxide containing electrodes can also have little or no molybdenum element, together with a portion of molybdenum oxide, e.g., MoOx with x between 2 and 3. The molybdenum oxide can be present as molybdenum trioxide MoO3, or in Magneli phases, such as Mo4O11, MO8O23, or Mo9O26. The molybdenum-dioxide containing electrodes can be formed by annealing a multilayer including a layer of molybdenum and a layer of molybdenum oxide. The oxygen content of the multilayer can be configured to completely, or substantially completely, react with molybdenum to form molybdenum dioxide, together with leaving a small excess amount of molybdenum oxide MoOx with x>2.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: September 16, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Sergey Barabash, Dipankar Pramanik, Xuena Zhang
  • Publication number: 20140252571
    Abstract: A wafer-level package device and techniques are described that include utilizing a dry-etch process for mitigating metal seed layer undercut. In an implementation, a process for fabricating the wafer-level package device that employs the techniques of the present disclosure includes processing a substrate, depositing a metal seed layer on the substrate, depositing and patterning a resist layer, depositing a redistribution layer structure, removing the photoresist layer, and dry-etching the metal seed layer. In implementations, the wafer-level package device that employs example techniques in accordance with the present disclosure includes a substrate, a metal seed layer disposed on the substrate, and a redistribution layer structure formed on the metal seed layer. The metal seed layer is dry-etched so that undercut is mitigated.
    Type: Application
    Filed: March 6, 2013
    Publication date: September 11, 2014
    Applicant: Maxim Integrated Products, Inc.
    Inventor: Maxim Integrated Products, Inc.