Having Adhesion Promoting Layer Patents (Class 438/654)
  • Patent number: 10700036
    Abstract: Encapsulated stress mitigation layers and assemblies having the same are disclosed. An assembly that includes a first substrate, a second substrate, an encapsulating layer disposed between the first and second substrates, and a stress mitigation layer disposed in the encapsulating layer such that the stress mitigation layer is encapsulated within the encapsulating layer. The stress mitigation layer has a lower melting temperature relative to a higher melting temperature of the encapsulating layer. The assembly includes an intermetallic compound layer disposed between the first substrate and the encapsulating layer such that the encapsulating layer is separated from the first substrate by the intermetallic compound layer. The stress mitigation layer melts into a liquid when the assembly operates at a temperature above the low melting temperature of the stress mitigation layer and the encapsulating layer maintains the liquid of the stress mitigation layer within the assembly.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: June 30, 2020
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Shailesh N. Joshi, Naoya Take
  • Patent number: 10366955
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: July 30, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Yeol Kim, Ji Won Kang, Chung Hwan Shin, Jin Il Lee, Sang Jin Hyun
  • Patent number: 9558999
    Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a pair of ultra-thin metal wires in an opening using a selective deposition process.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: January 31, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Juntao Li, Chih-Chao Yang, Yunpeng Yin
  • Patent number: 9236297
    Abstract: Provided are methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature chemical vapor deposition (CVD) process to fill the features with tungsten. In certain embodiments, the process temperature is maintained at less than about 350° C. during the chemical vapor deposition to fill the feature. The reduced-temperature CVD tungsten fill provides improved tungsten fill in high aspect ratio features, provides improved barriers to fluorine migration into underlying layers, while achieving similar thin film resistivity as standard CVD fill. Also provided are methods of depositing thin tungsten films having low-resistivity. According to various embodiments, the methods involve performing a reduced temperature low resistivity treatment on a deposited nucleation layer prior to depositing a tungsten bulk layer and/or depositing a bulk layer via a reduced temperature CVD process followed by a high temperature CVD process.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: January 12, 2016
    Assignee: Novellus Systems, Inc.
    Inventors: Feng Chen, Raashina Humayun, Michal Danek, Anand Chandrashekar
  • Publication number: 20150140809
    Abstract: The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 21, 2015
    Inventors: David A. DeMuynck, Zhong-Xiang He, Daniel R. Miga, Matthew D. Moon, Daniel S. Vanslette, Eric J. White
  • Publication number: 20150108645
    Abstract: A method including forming a first dielectric layer above a conductive pad and above a metallic structure, the conductive pad and the metallic structure are each located within an interconnect level above a substrate, forming a first opening and a second opening in the first dielectric layer, the first opening is aligned with and exposes the conductive pad and the second opening is aligned with and exposes the metallic structure, and forming a metallic liner on the conductive pad, on the metallic structure, and above the first dielectric layer. The method may further include forming a second dielectric layer above the metallic liner, and forming a third dielectric layer above the second dielectric layer, the third dielectric layer is thicker than either the first dielectric layer or the second dielectric layer.
    Type: Application
    Filed: October 22, 2013
    Publication date: April 23, 2015
    Applicant: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter
  • Publication number: 20150079785
    Abstract: A plating method can improve adhesivity with a substrate. The plating method of performing a plating process on the substrate includes forming a vacuum-deposited layer 2A on the substrate 2 by performing a vacuum deposition process on the substrate 2; forming an adhesion layer 21 and a catalyst adsorption layer 22 on the vacuum-deposited layer 2A of the substrate 2; and forming a plating layer stacked body 23 having a first plating layer 23a and a second plating layer 23b which function as a barrier film on the catalyst adsorption layer 22 of the substrate 2. By forming the vacuum-deposited layer 2A, a surface of the substrate 2 can be smoothened, so that the vacuum-deposited layer 2A serving as an underlying layer can improve the adhesivity.
    Type: Application
    Filed: February 22, 2013
    Publication date: March 19, 2015
    Inventors: Nobutaka Mizutani, Takashi Tanaka, Yuichiro Inatomi, Yusuke Saito, Mitsuaki Iwashita
  • Patent number: 8975180
    Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: March 10, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Thomas R. Boussie, David E. Lazovsky, Sandra G. Malhotra
  • Publication number: 20150041983
    Abstract: Provided are a semiconductor device and semiconductor-device manufacturing method that make it possible to improve the contact between an insulating film and a wiring member and the reliability thereof. This method for manufacturing a semiconductor device (100) includes a step in which a CF film (106) is formed on top of a semiconductor substrate (102), a step in which grooves (C) corresponding to a wiring pattern (P) are formed in the CF film (106), and a step in which a copper wiring member (114) is embedded in the grooves (C).
    Type: Application
    Filed: February 21, 2013
    Publication date: February 12, 2015
    Applicants: TOKYO ELECTRON LIMITED, TOHOKU UNIVERSITY, ZEON CORPORATION
    Inventors: Takenao Nemoto, Takehisa Saito, Yugo Tomita, Hirokazu Matsumoto, Akihide Shirotori, Akinobu Teramoto, Xun Gu
  • Publication number: 20140377947
    Abstract: When a recess is formed in a SiCOH film, C is removed from the film to form a damage layer. If the damage layer is removed by hydrofluoric acid or the like, the surface becomes hydrophobic. By supplying a boron compound gas, a silicon compound gas or a gas containing trimethyl aluminum to the SiCOH film, B, Si or Al is adsorbed on the SiCOH film. These atoms bond with Ru and a Ru film is easily formed on the SiCOH film. The Ru film is formed using, for example, Ru3(CO)12 gas and CO gas. Copper is filled in the recess and an upper side wiring structure is formed by carrying out CMP processing.
    Type: Application
    Filed: January 24, 2013
    Publication date: December 25, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Tadahiro Ishizaka, Atsushi Gomi, Kenji Suzuki, Tatsuo Hatano, Yasushi Mizusawa
  • Patent number: 8900992
    Abstract: Methods for forming ruthenium films and semiconductor devices, such as capacitors, that include the films are provided.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: December 2, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vishwanath Bhat, Dan Gealy, Vassil Antonov
  • Patent number: 8871636
    Abstract: A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via cavity either by a plasma treatment that removes fluorine from exposed surfaces of the FSG layer, or by deposition of a substantially fluorine-free dielectric layer. Metal is deposited within the line trough and the via cavity to form a metal line and a metal via. The fluorine depleted adhesion layer provides enhanced adhesion to the metal line compared with prior art structures in which a metal line directly contacts a FSG layer. The enhanced adhesion of metal with an underlying dielectric layer provides higher resistance to delamination for a semiconductor package employing lead-free C4 balls on a metal interconnect structure.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Emily R. Kinser
  • Patent number: 8865591
    Abstract: A method for forming an n-type contact electrode, which includes an n-type nitride semiconductor such as AlxInyGazN (with x, y, and z being rational numbers that sum to 1.0 and fulfill the relations 0<x?1.0, 0?y?0.1, and 0?z<1.0), includes: a step in which a first electrode metal layer including at least one metal selected from titanium, vanadium, and tantalum is formed on a layer of the aforementioned n-type semiconductor and then heat-treated at a temperature between 800° C. and 1200° C.; and a step in which a second electrode metal layer is formed on top of the first electrode metal layer and then heat-treated at a temperature between 700° C. and 1000° C. The second electrode metal layer contains a layer comprising a metal, such as aluminum, that has a work function between 4.0 and 4.8 eV and a resistivity between 1.5×10?6 ?·cm and 4.0×10?6 ?·cm.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: October 21, 2014
    Assignee: Tokuyama Corporation
    Inventors: Naoki Tamari, Toru Kinoshita
  • Patent number: 8866313
    Abstract: A substrate includes a die-bonding zone and a glue spreading pattern. The die-bonding zone is set to bond a die. The glue spreading pattern is placed in the die-bonding zone and includes a containing space. The die is placed on the glue spreading pattern, an area of a bottom of the die is greater than an area of an opening of the glue spreading pattern, the containing room of the glue spreading pattern is filled with a glue, and the die is bonded to the substrate by means of the glue.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: October 21, 2014
    Assignee: Unistars Corporation
    Inventors: Tien-Hao Huang, Hsin-Hsie Lee, Yi-Chun Wu, Shang-Yi Wu
  • Patent number: 8865594
    Abstract: The invention provides a method of forming a film stack on a substrate, comprising performing a silicon containing gas soak process to form a silicon containing layer over the substrate, reacting with the silicon containing layer to form a tungsten silicide layer on the substrate, depositing a tungsten nitride layer on the substrate, subjecting the substrate to a nitridation treatment using active nitrogen species from a remote plasma, and depositing a conductive bulk layer directly on the tungsten nitride layer.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: October 21, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Sang-Hyeob Lee, Sang Ho Yu, Kai Wu
  • Patent number: 8859421
    Abstract: There is provided a manganese oxide film forming method capable of forming a manganese oxide film having high adhesivity to Cu. In the manganese oxide film forming method, a manganese oxide film is formed on an oxide by supplying a manganese-containing gas onto the oxide. A film forming temperature for forming the manganese oxide film is set to be equal to or higher than about 100° C. and lower than about 400° C.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: October 14, 2014
    Assignees: Tokyo Electron Limited, Tohoku University
    Inventors: Koji Neishi, Junichi Koike, Kenji Matsumoto
  • Patent number: 8841212
    Abstract: A method patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber. Next, sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening. A second Tantalum Nitride layer is formed on the conductor, the Tantalum layer, and the first Tantalum Nitride layer, again in the first chamber. After the second Tantalum Nitride layer is formed, the methods herein form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer in a second, different chamber.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Takeshi Nogami, Thomas M. Shaw, Andrew H. Simon, Jean E. Wynne, Chih-Chao Yang
  • Patent number: 8835311
    Abstract: Embodiments of the invention provide an improved process for depositing tungsten-containing materials. In one embodiment, the method for forming a tungsten-containing material on a substrate includes forming an adhesion layer containing titanium nitride on a dielectric layer disposed on a substrate, forming a tungsten nitride intermediate layer on the adhesion layer, wherein the tungsten nitride intermediate layer contains tungsten nitride and carbon. The method further includes forming a tungsten barrier layer (e.g., tungsten or tungsten-carbon material) from the tungsten nitride intermediate layer by thermal decomposition during a thermal annealing process (e.g., temperature from about 700° C. to less than 1,000° C.).
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: September 16, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Joshua Collins, Murali K. Narasimhan, Jingjing Liu, Sang-Hyeob Lee, Kai Wu, Avgerinos V. Gelatos
  • Patent number: 8828863
    Abstract: A method for providing metal filled features in a layer is provided. A nonconformal metal seed layer is deposited on tops, sidewalls, and bottoms of the features, wherein more seed layer is deposited on tops and bottoms of features than sidewalls. The metal seed layer are etched back on tops, sidewalls, and bottoms of the features, wherein some metal seed layer remains on tops and bottoms of the features. Deposition on the seed layer on tops of the features is suppressed. An electroless “bottom up” deposition of metal is provided to fill the features.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: September 9, 2014
    Assignee: Lam Research Corporation
    Inventors: William T. Lee, Xiaomin Bin
  • Patent number: 8828861
    Abstract: Methods for fabricating conductive metal lines of a semiconductor device are described herein. In one embodiment, such a method may comprise depositing a conductive material over a substrate, and depositing a first barrier layer on the conductive layer. Such a method may also comprise patterning a mask on the first barrier layer, the pattern comprising a layout of the conductive lines. Such an exemplary method may also comprise etching the conductive material and the first barrier layer using the patterned mask to form the conductive lines. In addition, a low temperature post-flow may be performed on the structure. The method may also include depositing a dielectric material over and between the patterned conductive lines.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: September 9, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Tuung Luoh, Ming Da Cheng, Chin-Ta Su, Tahone Yang, Kuang-Chao Chen
  • Patent number: 8829524
    Abstract: An exemplary thin film transistor array substrate (200) includes a substrate (210) and a gate electrode (220) formed on the substrate. The gate electrode includes an adhesive layer (226) formed on the substrate, a conductive layer (224) formed on the adhesive layer and a barrier layer (222) formed on the conductive layer, the adhesive layer and the barrier layer both have sandwich structures. A central core of the adhesive layer, the conductive layer, and a central core of the barrier layer are made of a same material.
    Type: Grant
    Filed: October 1, 2007
    Date of Patent: September 9, 2014
    Assignee: Innolux Corporation
    Inventor: Shuo-Ting Yan
  • Publication number: 20140235052
    Abstract: Methods for fabricating semiconductor devices having through electrodes are provided. The method may comprise forming a via hole which opens towards an upper surface of a substrate and disconnects with a lower surface of the substrate; forming a via isolation layer which extends along an inner surface of the via hole and covers the upper surface of the substrate; forming a seed layer on the via isolation layer which extends along the via isolation layer; annealing the seed layer in-situ after forming the seed layer; forming a conductive layer, filling the via hole, by an electroplating using the seed layer; and planarizing the upper surface of the substrate to form a through electrode surrounded by the via isolation layer in the via hole.
    Type: Application
    Filed: February 19, 2014
    Publication date: August 21, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kunsang Park, Sukyoung Kim, Jisoon Park, Ju-Il Choi, Byung Lyul Park, Gilheyun Choi
  • Patent number: 8772155
    Abstract: High aspect ratio trenches may be filled with metal that grows more from the bottom than the top of the trench. As a result, the tendency to form seams or to close off the trench at the top during filling may be reduced in some embodiments. Material that encourages the growth of metal may be formed in the trench at the bottom, while leaving the region of the trench near the top free of such material to encourage growth upwardly from the bottom.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Shai Haimson, Avi Rozenblat, Dror Horvitz, Maor Rotlain, Rotem Drori
  • Publication number: 20140186983
    Abstract: A method of cleaning a mask includes preparing a mask on which a first metal layer and a second metal layer are stacked sequentially, and lifting off the second metal layer by removing the first metal layer.
    Type: Application
    Filed: July 17, 2013
    Publication date: July 3, 2014
    Inventors: Eung Do KIM, Won Jong KIM, Kyu Hwan HWANG, Seok Gyu YOON, Dong Chan KIM, Bo Ra JUNG, Dong Kyu SEO, Young Woo SONG, Jong Hyuk LEE
  • Patent number: 8765602
    Abstract: A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Dyer, Daniel C. Edelstein, Tze-man Ko, Andrew H. Simon, Wei-tsu Tseng
  • Patent number: 8765597
    Abstract: A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via cavity either by a plasma treatment that removes fluorine from exposed surfaces of the FSG layer, or by deposition of a substantially fluorine-free dielectric layer. Metal is deposited within the line trough and the via cavity to form a metal line and a metal via. The fluorine depleted adhesion layer provides enhanced adhesion to the metal line compared with prior art structures in which a metal line directly contacts a FSG layer. The enhanced adhesion of metal with an underlying dielectric layer provides higher resistance to delamination for a semiconductor package employing lead-free C4 balls on a metal interconnect structure.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Emily R. Kinser
  • Patent number: 8735276
    Abstract: Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: May 27, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Hyun-Soo Chung, Jae-Shin Cho, Dong-Ho Lee, Dong-Hyeon Jang, Seong-Deok Hwang, Seung-Duk Baek
  • Patent number: 8716127
    Abstract: A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. The metal alloy capping layer is also reflowed on the copper. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy capping layer, and a dielectric cap.
    Type: Grant
    Filed: May 11, 2013
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Marc A. Bergendahl, Steven J. Holmes, David V. Horak, Charles W. Koburger, Shom Ponoth
  • Patent number: 8709943
    Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: April 29, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Thomas R. Boussie, David E. Lazovsky, Sandra G. Malhotra
  • Patent number: 8691690
    Abstract: Disclosed are embodiments of a contact formation technique that incorporates a preventative etch step to reduce interlayer dielectric material flaking (e.g., borophosphosilicate glass (BPSG) flaking) and, thereby to reduce surface defects. Specifically, contact openings, which extend through a dielectric layer to semiconductor devices in and/or on a center portion of a substrate, can be filled with a conductor layer deposited by chemical vapor deposition (CVD). Chemical mechanical polishing (CMP) of the conductor layer can be performed to complete the contact structures. However, before the CMP process is performed (e.g., either before the contact openings are ever formed or before the contact openings are filled), a preventative etch process can be performed to remove any dielectric material from above the edge portion of the substrate. Removing the dielectric material from above the edge portion of the substrate prior to CMP reduces the occurrence of surface defects caused by dielectric material flaking.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: April 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yoba Amoah, Brian M. Czabaj, Thomas J. Dunbar, Jeffrey P. Gambino, Molly J. Leitch, Polina A. Razina
  • Patent number: 8673773
    Abstract: A method for producing a nanoporous layer comprises applying a plating base with adhesion strengthening onto a substrate, depositing a layer made of gold and silver onto the substrate, the composition being in the range of 20% to 40% gold and 80% to 60% silver, and selectively removing the silver in order to produce a nanoporous gold layer.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: March 18, 2014
    Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
    Inventors: Hermann Oppermann, Lothar Dietrich, Gunter Engelmann, Wolf Jürgen
  • Patent number: 8669182
    Abstract: An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not substantially extend onto an upper surface of the dielectric material that is adjacent to the at least one conductive region, and the noble cap material does not be deposited on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 300° C. or less) chemical deposition process is also provided.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: March 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Daniel C. Edelstein
  • Publication number: 20140061921
    Abstract: A method of manufacturing comprising providing a semiconductor layer having metal adhesion layer on a planar surface of the semiconductor layer and an alloy layer on the metal adhesion layer, the alloy layer comprising an alloy of gold and a non-gold metal. The method comprises removing a portion of the non-gold metal from the alloy layer to form a porous gold layer. The method comprises applying pressure between the porous gold layer and a metal layer to form a bond between the semiconductor layer and the metal layer.
    Type: Application
    Filed: September 5, 2012
    Publication date: March 6, 2014
    Applicant: Alcatel-Lucent USA, Incorporated
    Inventor: Nagesh Basavanhally
  • Patent number: 8647982
    Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: February 11, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, James M. Wark, William M. Hiatt
  • Patent number: 8617985
    Abstract: Embodiments of the invention provide an improved process for depositing tungsten-containing materials. In one embodiment, the method for forming a tungsten-containing material on a substrate includes forming an adhesion layer containing titanium nitride on a dielectric layer disposed on a substrate, forming a tungsten nitride intermediate layer on the adhesion layer, wherein the tungsten nitride intermediate layer contains tungsten nitride and carbon. The method further includes forming a tungsten barrier layer (e.g., tungsten or tungsten-carbon material) from the tungsten nitride intermediate layer by thermal decomposition during a thermal annealing process (e.g., temperature from about 700° C. to less than 1,000° C.).
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: December 31, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Joshua Collins, Murali K. Narasimhan, Jingjing Liu, Sang-Hyeob Lee, Kai Wu, Avgerinos V. Gelatos
  • Patent number: 8586485
    Abstract: Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, flouroalkyl groups, heteroarlyl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: November 19, 2013
    Assignee: Intermolecular, Inc.
    Inventors: David E. Lazovsky, Tony P. Chiang, Majid Keshavarz
  • Patent number: 8586480
    Abstract: A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: November 19, 2013
    Assignee: IXYS Corporation
    Inventor: Nathan Zommer
  • Patent number: 8580679
    Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: November 12, 2013
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Sridhar Balakrishnan, Mark Bohr
  • Patent number: 8575005
    Abstract: A method of manufacturing an electronic device on a plastic substrate includes: providing a carrier as a rigid support for the electronic device; providing a metallic layer on the carrier; forming the plastic substrate on the metallic layer, the metallic layer guaranteeing a temporary bonding of the plastic substrate to the carrier; forming the electronic device on the plastic substrate; and releasing the carrier from the plastic substrate. Releasing the carrier comprises immersing the electronic device bonded to the carrier in a oxygenated water solution that breaks the bonds between the plastic substrate and the metallic layer.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: November 5, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Corrado Accardi, Stella Loverso, Sebastiano Ravesi, Noemi Graziana Sparta
  • Publication number: 20130288476
    Abstract: Semiconductors are electrochemically etched in solutions containing sources of bifluoride and nickel ions. The electrochemical etching may form pores in the surface of the semiconductor in the nanometer range. The etched semiconductor is then nickel plated.
    Type: Application
    Filed: June 22, 2013
    Publication date: October 31, 2013
    Inventors: Gary HAMM, Jason A. REESE, George R. ALLARDYCE
  • Patent number: 8569888
    Abstract: Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Fen Chen, Jeffrey P. Gambino, Anthony K. Stamper, Timothy D. Sullivan
  • Patent number: 8563432
    Abstract: A method for forming a TSV structure includes providing a silicon substrate with an interlayer dielectric layer formed thereon, forming a hard mask structure including a first hard mask layer including a metal element on the interlayer dielectric layer and a second hard mask layer on the first hard mask layer; forming an opening through the hard mask structure and the interlayer dielectric layer, the opening has a bottom and sidewalls in the silicon substrate. The method further includes depositing an insulating material on the hard mask structure and on the bottom and the sidewalls of the opening, subsequently removing the insulating material and the second hard mask layer until the first hard mask layer is exposed, and filling a conductive material into the opening. The method also includes removing the conductive material and the first hard mask layer by a CMP process until the interlayer dielectric layer is exposed.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: October 22, 2013
    Assignee: Semiconductor Manufacturing International Corp.
    Inventor: Zhongshan Hong
  • Patent number: 8563423
    Abstract: A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via cavity either by a plasma treatment that removes fluorine from exposed surfaces of the FSG layer, or by deposition of a substantially fluorine-free dielectric layer. Metal is deposited within the line trough and the via cavity to form a metal line and a metal via. The fluorine depleted adhesion layer provides enhanced adhesion to the metal line compared with prior art structures in which a metal line directly contacts a FSG layer. The enhanced adhesion of metal with an underlying dielectric layer provides higher resistance to delamination for a semiconductor package employing lead-free C4 balls on a metal interconnect structure.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Emily R. Kinser
  • Patent number: 8501620
    Abstract: Top-down methods of increasing reflectivity of tungsten films to form films having high reflectivity, low resistivity and low roughness are provided. The methods involve bulk deposition of tungsten followed by a removing a top portion of the deposited tungsten. In particular embodiments, removing a top portion of the deposited tungsten involve exposing it to a fluorine-containing plasma. The methods produce low resistivity tungsten bulk layers having lower roughness and higher reflectivity. The smooth and highly reflective tungsten layers are easier to photopattern than conventional low resistivity tungsten films. Applications include forming tungsten bit lines.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: August 6, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Raashina Humayun
  • Patent number: 8492274
    Abstract: A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. The metal alloy capping layer is also reflowed on the copper. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy capping layer, and a dielectric cap.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Marc A. Bergendahl, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Shom Ponoth
  • Patent number: 8481425
    Abstract: A method for fabricating through-silicon via structure is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a through-silicon via in the semiconductor substrate; covering a liner in the through-silicon via; performing a baking process on the liner; forming a barrier layer on the liner; and forming a through-silicon via electrode in the through-silicon via.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: July 9, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Yen-Liang Lu, Chun-Ling Lin, Chi-Mao Hsu, Chin-Fu Lin, Chun-Hung Chen, Tsun-Min Cheng, Meng-Hong Tsai
  • Publication number: 20130168864
    Abstract: A tungsten nucleation film is formed on a surface of a semiconductor substrate by alternatively providing to that surface, reducing gases and tungsten-containing gases. Each cycle of the method provides for one or more monolayers of the tungsten film. The film is conformal and has improved step coverage, even for a high aspect ratio contact hole.
    Type: Application
    Filed: October 2, 2012
    Publication date: July 4, 2013
    Inventors: Sang-Hyeob Lee, Joshua Collins
  • Patent number: 8476162
    Abstract: Methods for forming layers on a substrate are provided herein. In some embodiments, methods of forming layers on a substrate disposed in a process chamber may include depositing a barrier layer comprising titanium within one or more features in the substrate; and sputtering a material from a target in the presence of a plasma formed from a process gas by applying a DC power to the target, maintaining a pressure of less than about 500 mTorr within the process chamber, and providing up to about 5000 W of a substrate bias RF power to deposit a seed layer comprising the material atop the barrier layer.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: July 2, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Tae Hong Ha, Winsor Lam, Tza-Jing Gung, Joung Joo Lee
  • Patent number: 8461044
    Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: June 11, 2013
    Assignee: Intermolecular, Inc.
    Inventors: David E. Lazovsky, Sandra G. Malhotra, Thomas R. Boussie
  • Patent number: 8440562
    Abstract: A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a conductive wiring in the first dielectric layer; and a copper germanide nitride layer over the conductive wiring.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: May 14, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Shi Liu, Chen-Hua Yu