Abstract: A storage element of a stacked capacitor having a high dielectric film for a semiconductor device and a method of fabricating the same, the storage element having a storage node comprising a bottom polysilicon layer, a barrier metal layer, and a transition metal layer with sidewall spacers formed on the barrier metal layer. The barrier metal layer and sidewall spacers prevent the polysilicon layer from being oxidized. The polysilicon layer is formed to a thickness that determines the height of the storage node. The transition metal layer directly interfacing the high dielectric film is thinly formed to avoid slope etching thereof and thereby prevent electrical bridges or shorts between adjacent storage nodes.

Abstract: Structures and processes are disclosed for reducing electrical contact resistance between two metal layers. Specifically, a resistive aluminum oxide layer forms spontaneously on metal lines including aluminum, within a V-shaped contact via which is opened in an insulating layer through a mask. The mask includes an opening with a width of less than about 0.75 &mgr;m. After removing the mask, the via is treated with an RF etch. The resultant contact has a width at the bottom of less than 0.9 &mgr;m. A titanium layer of 300 Å to 400 Å is deposited into the via, with about 60 Å to 300 Å reaching the via bottom and reacted with the underlying aluminum. The reaction produces a titanium-aluminum complex (TiAlx) with a thickness of about 150 Å to 900 Å. Advantageously, this composite layer provides a low resistivity contact between the aluminum-containing layer and a subsequently deposited metal layer.

Abstract: A new method of metal plug metallization utilizing a sacrificial high polishing rate layer to prevent dishing and metal residues after CMP is described. An oxide layer is provided overlying semiconductor device structures in and on a semiconductor substrate. A sacrificial high polishing rate (HPR) layer is deposited overlying the oxide layer. An opening is etched through the HPR layer and the oxide layer to one of the semiconductor device structures. A barrier layer and a metal layer are deposited over the surface of the HPR layer and within the opening. The metal layer, barrier layer, and HPR layer overlying the oxide layer are polished away by CMP. The polishing rate of the HPR layer is higher than that of the metal layer with the result that after the HPR layer is completely removed, the metal layer remaining within the opening has a convex shape. The oxide layer is over-polished until endpoint detection is received.

Abstract: A process for chemical vapor deposition of blanket tungsten thin films on titanium nitride proceeds by hydrogen reduction of tungsten hexafluoride at temperatures between 200° C. and 500° C. Tungsten film nucleation is preferably facilitated by a hydrogen plasma treatment of the titanium nitride surface of the substrate. The plasma treatment may be carried out in a separate etch chamber and transferred to a tungsten CVD chamber without intervening exposure to air, or, preferably, is carried out with a low energy etch performed with the substrate mounted on a susceptor in the chamber of the tungsten CVD reactor at which the tungsten film is to be applied.

Abstract: A method for forming a refractory metal layer that features two-stage nucleation prior to bulk deposition of the same. The method includes placing a substrate in a deposition zone, flowing, into the deposition zone during a first deposition stage, a silicon source, such as a silane gas, and a tungsten source, such as tungsten-hexafluoride gas, so as to obtain a predetermined ratio of the two gases therein. During a second deposition stage, subsequent to the first deposition stage, the ratio of the two gases is varied. Specifically, in the first deposition stage there is a greater quantity of silane gas than tungsten-hexafluoride gas. In the second deposition stage there may be a greater quantity of tungsten-hexafluoride than silane.

Abstract: Method and arrangements are provided for removing plasma etch damage to pre-silicidize the surfaces by a wet silicon etch. Following the formation of lightly doped drain (LDD) spacers in conjunction with a refractory metal silicide process, the damage created by the plasma etching to form these sidewall spacers is removed. The silicide that is formed on the pre-silicidized surfaces are substantially free of the etch damage and/or elemental contaminants and exhibits improved quality.

Abstract: The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure comprising a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.

Abstract: A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is deposited by chemical vapor deposition, or by physical vapor deposition in a layer less than about 800 angstroms.

Abstract: A method of filling contact holes in a dielectric layer on an integrated circuit wafer. The method reduces processing steps and results in a reliable metal plug filling the contact hole. In one embodiment the contact hole is filled using blanket deposition of titanium silicide using chemical vapor deposition followed by etchback. In a second embodiment the contact hole is filled with titanium silicide using selective chemical vapor deposition of titanium silicide. In a third embodiment an adhesion layer of titanium silicide is formed on the sidewalls and bottoms of the contact holes. A conductor metal of titanium silicide, aluminum, tungsten, or copper is used to fill the contact hole using selective chemical vapor deposition.

Abstract: A structure and a method for providing structural stability at an interface between two poorly adhering layers in a semiconductor device involve providing anchoring channels in one of the poorly adhering layers through which the other poorly adhering layer can be anchored to a third layer. Specifically, the structure and method are applicable to a three-layer stack having a top layer of amorphous silicon, a middle layer of titanium nitride, and a bottom layer of oxide. In order to reduce susceptibility to delamination between the amorphous silicon layer and the titanium nitride layer, the anchoring channels are created in the titanium nitride layer to allow the amorphous silicon to attach to the oxide layer. Because the amorphous silicon layer and the oxide layer exhibit good adhesion between each other, delamination between the amorphous silicon layer and the titanium nitride layer is minimized.

Abstract: The present invention provides an effective barrier layer for improved via fill in high aspect ratio sub-micron apertures at low temperature, particularly at the contact level on a substrate. In one aspect of the invention, a feature is filled by first depositing a barrier layer onto a substrate having high aspect ratio contacts or vias formed thereon. The barrier layer is preferably comprised of Ta, TaNx, W, WNx, or combinations thereof. A CVD conformal metal layer is then deposited over the barrier layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal layer is deposited onto the previously formed CVD conformal metal layer at a temperature below that of the melting point temperature of the metal to allow flow of the CVD conformal layer and the PVD metal layer into the vias.

Abstract: A solder bumping method and structure for producing fine-pitch solder bump and which eliminate conventional process compatibility requirements for under bump metallurgy (UBM) and solder bump formation. The method generally entails forming an input/output pad on the surface of a semiconductor device, and then forming a metal layer on the input/output pad that will serve as the UBM of the solder bump. A plating seed layer is then formed on the UBM and on the surrounding surface of the device, after which a mask is formed on the plating seed layer and a via is formed in the mask to expose a portion of the plating seed layer overlying the UBM, and preferably portions of the plating seed layer not overlying the UBM. A solder material is then deposited on the portion of the plating seed layer exposed within the via.

Abstract: A semiconductor wafer comprises a substrate, a first conductive layer and a dielectric layer covering the first conductive layer. A thin-film layer is formed over the dielectric layer. The thin-film layer comprises a hole that penetrates down to the surface of the dielectric layer and the hole is located above the first conductive layer. A first barrier layer is formed on the surface of the semiconductor wafer to cover the thin-film layer. Next, a spacer is formed on the internal walls of the hole. Thereafter, a first dry etching process is performed to form a contact hole. A second barrier layer is then formed on the internal walls of the contact hole. A second conductive layer is formed on the surface of the semiconductor wafer that fills the contact hole. A lithographic process is performed to define a pattern and a location of the storage node in a photo resist layer above the contact hole.

Abstract: A process of forming a thin, protective insulator layer, on the sides of metal interconnect structures, prior to the deposition of a halogen containing, low k dielectric layer, has been developed. The process features the growth of a thin metal nitride, or thin metal oxide layer, on the exposed sides of the metal interconnect structures, via a plasma treatment, performed in either a nitrogen containing, or in a water containing, ambient. The thin layer protects the metal interconnect structure from the corrosive, as well as delamination effects, created by the halogen, or halogen products, contained in overlying low k dielectric layers, such as fluorinated silica glass.

Abstract: A diffusion barrier layer comprising TiNxBy is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can be fabricated by first forming a TiN layer and then incorporating boron into the TiN layer. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a TDMAT process including boron. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a CVD process.

Abstract: A method of fabricating a barrier layer includes a clamped metal layer formed on a substrate. After the formation of the clamped metal layer, a rapid thermal process is performed. A clampless metal nitride layer is then formed on the clamped metal layer.

Abstract: Borderless vias are formed by depositing a hard dielectric mask layer on the upper surface of a lower metal feature and forming sidewall spacers on the side surfaces of the metal feature and mask layer. A dielectric interlayer is deposited and a misaligned through-hole formed therein by etching. The dielectric material of the sidewall spacer and dielectric material of the dielectric interlayer are different. The etchant employed to form the through-hole exhibits a high selectivity with respect to the sidewall spacer material. The dielectric mask layer enables the formation of a sidewall spacer extending above the metal feature such that, after etching to form the misaligned through-hole, the sidewall spacer covers the side surface of the metal feature.

Abstract: A method of fabricating a plug etches back the first plug material layer to form a dished surface on the first plug material layer and then performs a second coverage step. A second plug material layer is formed to fill the dished surface and a hole. Thus, the slurry cannot fill the hole during chemical mechanical polishing nor can slurry react with the plug material or the first metallic layer. The reliability of the plug according to the present invention is increased. The thickness of the second plug material layer is thinner than the plug material layer of the conventional method. The thickness is decreased by about 60% when compared with the conventional method, which decreases fabrication costs.

Abstract: An interconnect (60) is formed overlying a substrate (10). In one embodiment, an adhesion/barrier layer (81), a copper-alloy seed layer (42), and a copper film (43) are deposited overlying the substrate (10), and the substrate (10) is annealed. In an alternate embodiment, a copper film is deposited over the substrate, and the copper film is annealed. In yet another embodiment, an adhesion/barrier layer (81), a seed layer (82), a conductive film (83), and a copper-alloy capping film (84) are deposited over the substrate (10) to form an interconnect (92). The deposition and annealing steps can be performed on a common processing platform.

Abstract: The present invention provides a method for forming a discontinuous conductive layer in the fabrication of integrated circuits. The method includes providing a substrate assembly having a surface including at least one metal-containing adhesion region separated by at least one surface region of the substrate assembly. A conductive metal layer is formed on the surface of the substrate assembly. The substrate assembly including the conductive metal layer thereon in then annealed. Any nonadhered conductive metal is removed from the at least one exposed surface region to form a discontinuous conductive metal layer on at least one metal-containing adhesion region, for example, by simply rising the substrate assembly in water. The conductive metal layer can be platinum or ruthenium.

Abstract: A semiconductor device and a method for making a semiconductor device having a pillar-shaped capacitor storage node compatible with a high dielectric film, wherein the pillar-shaped capacitor storage node includes a thick conductive metal layer that is easily etched and a thin conductive layer completely coating the thick conductive metal layer. The thin conductive layer protects the thick conductive metal layer during subsequent high dielectric deposition and annealing and various oxidation process.

Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.

Abstract: Methods of fabricating ohmic contacts and adhesion layers therefore are provided. In one aspect, a method of fabricating an ohmic contact in an opening of an insulating layer is provided. Tetra-dimethyl-amino-titanium vapor is decomposed in the presence of the opening to deposit TiCN in the opening at a rate of about 9.4 to 10.6 Å/second and a thickness of less than about 105 Å. The deposited TiCN is exposed to a plasma ambient containing nitrogen and hydrogen to remove carbon and oxygen from the deposited TiCN. A conducting material is deposited on the TiCN. Controlled TiCN thickness, and subsequent plasma treatment dissociate most of the carbon and oxygen incorporated into the TiCN layer during deposition. The potential for undesirably high contact resistance due to oxygen and carbon-based insulating structures within the adhesion layer is reduced.

Abstract: The present invention relates to a method of soldering a semiconductor chip to a substrate, such as to a capsule in an RF-power transistor, for instance. The semiconductor chip is provided with an adhesion layer consisting of a first material composition. A solderable layer consisting of a second material composition is disposed on this adhesion layer. An antioxidation layer consisting of a third material composition is disposed on said solderable layer. The antioxidation layer is coated with a layer of gold-tin solder. The chip is placed on a solderable capsule surface, via said gold-tin solder. The capsule and chip are exposed to an inert environment to which a reducing gas is delivered and the capsule and chip are subjected to a pressure substantially beneath atmospheric pressure whilst the gold-tin solder is heated to a temperature above its melting point.

Abstract: The present invention provides an effective barrier layer for improved via fill in high aspect ratio sub-micron apertures at low temperature, particularly at the contact level on a substrate. In one aspect of the invention, a feature is filled by first depositing a barrier layer onto a substrate having high aspect ratio contacts or vias formed thereon. The barrier layer is preferably comprised of Ta, TaNx, W, WNx, or combinations thereof. A CVD conformal metal layer is then deposited over the barrier layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal layer is deposited onto the previously formed CVD conformal metal layer at a temperature below that of the melting point temperature of the metal to allow flow of the CVD conformal layer and the PVD metal layer into the vias.

Abstract: A process of polishing two dissimilar conductive materials deposited on semiconductor device substrate optimizes the polishing of each of the conductive material independently, while utilizing the same polishing equipment for manufacturing efficiency. A tungsten layer (258) and a titanium layer (256) of a semiconductor device substrate (250) are polished using one polisher (10) but two different slurry formulations. The two slurries can be dispensed sequentially onto the same polishing platen (132) from two different urce containers (111 and 112), wherein the first slurry is dispensed until e tungsten is removed and then the slurry dispense is switched to second slurry for removal of the titanium. In a preferred embodiment, the first slurry composition is a ferric nitrate slurry while the second slurry composition is an oxalic acid slurry.

Abstract: A method for using a Cu(hfac) precursor with a substituted phenylethylene ligand to form an adhesive seed layer on an IC surface has been provided. The substituted phenylethylene ligand includes bonds to molecules selected from the group consisting of C1 to C6 alkyl, C1 to C6 haloalkyl, phenyl, H and C1 to C6 alkoxyl. One variation, the &agr;-methylstyrene ligand precursor has proved to be especially adhesive. Copper deposited with this precursor has low resistivity and high adhesive characteristics. The seed layer provides a foundation for subsequent Cu layers deposited through either CVD, PVD, or electroplating. The adhesive seed layer permits the subsequent Cu layer to be deposited through an economical high deposition rate process.

Abstract: A method for forming a Cu-thin film includes the steps of coating a dispersion containing Cu-containing ultrafine particles individually dispersed therein on a semiconductor substrate having recessed portions, such as wiring grooves, via holes or contact holes, which have an aspect ratio ranging from 1 to 30; firing the coated semiconductor substrate in an atmosphere which can decompose organic substances present in the dispersion, but never oxidizes Cu to form a Cu-thin film on the substrate; then removing the Cu-thin film on the substrate except for that present in the recessed portions to thus level the surface of the substrate and to form the Cu-thin film in the recessed portions. The method permits the complete embedding or filling of the recessed portions of LSI substrates having a high aspect ratio with a Cu-thin film and thus permits the formation of a conductive, uniform and fine pattern, and further requires a low processing cost.

Abstract: A new method of tungsten plug metallization using a silicide glue layer is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer is provided covering the semiconductor device structures wherein a contact opening is made through the insulating layer to one of the semiconductor device structures. A silicide layer is deposited conformally over the surface of the insulating layer and within the contact opening as a combined ohmic contact and glue layer. In a first embodiment, a tungsten layer is deposited overlying the silicide layer. The tungsten layer not within the contact opening is removed to complete the formation of the tungsten plug metallization. In a second embodiment, the silicide layer not within the contact opening is selectively removed and a tungsten layer is selectively deposited overlying the silicide layer within the contact opening to complete formation of the tungsten plug metallization in the fabrication of an integrated circuit.

Abstract: The present invention relates to an interconnect structure wherein the upper surface of the first interconnect level is a tungsten layer, portions of the first interconnect level are insulated from one another by an insulator of the SOG type, portions of a second interconnect level are connected to portions of the first interconnect level by conductive pads formed in openings of an insulating layer, at least the lower part of which is of the SOG type, the walls and the bottom of the openings are covered with a thin titanium layer, and the openings are filled with a conductive material selected in the group including Al, Cu and aluminum alloys such as silicon, copper, and titanium alloys.

Abstract: An multi-level interconnection uses a glue layer material as a via plug or contact plug. An method of forming the multi-level interconnection includes: forming a first opening and a wider second opening in a dielectric layer, whereas the first opening exposes the conductive layer and the second opening is above the first opening; and filling the first opening with titanium, titanium nitride or tungsten nitride.

Abstract: A dual damascene process for forming interconnects such as contact plugs or vias. A first metal line is formed on a substrate structure. A first metal line is formed on the substrate structure. At least a stud is formed to cover a part of the first metal line. An insulation layer is formed to cover the substrate structure, the first metal line and the stud. A part of the insulation layer is removed to expose the stud. The expose stud is removed to form a contact window to expose the part of the first metal line. A metal layer is formed to fill the contact window.

Abstract: The invention generally provides an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free interconnections in high aspect ratio, sub-half micron applications. The invention provides a multi-step PVD process in which the plasma power is varied for each of the steps to obtain favorable fill characteristics as well as good reflectivity, morphology and throughput. The initial plasma powers are relatively low to ensure good, void-free filling of the aperture and, then, the plasma powers are increased to obtain the desired reflectivity and morphology characteristics. The invention provides an aperture filling process comprising physical vapor depositing a metal over the substrate and varying the plasma power during the physical vapor deposition. Preferably, the plasma power is varied from a first discrete low plasma power to a second discrete high plasma power.

Abstract: The invention consists in a method of filling recesses in a surface layer of a workpiece with conductive material including the steps of: forming a barrier layer on the surface; depositing a layer of conductive material on to the barrier layer; and forcing, flowing or drifting the conductive material into the recesses characterized in that the barrier layer includes Oxygen or is oxidized and oxidized material in the surface of the layer is nitrided prior to the deposition of the conductive material.

Abstract: The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member with an ammonia plasma followed by depositing the diffusion barrier layer on the treated surface. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, treating the exposed surface of the Cu/Cu alloy interconnect with an ammonia plasma, and depositing a silicon nitride diffusion barrier layer directly on the plasma treated surface.

Abstract: A method for fabricating a dual damascene structure. A cap layer and a dielectric layer are formed in sequence over a substrate having a first conductive layer. A trench and a via hole are formed in the dielectric layer. The via hole is aligned under the trench. A barrier spacer is formed on sidewalls of the trench and the via hole. The cap layer exposed by the via hole is removed. A conformal adhesion layer is formed over the substrate. A second conductive layer is formed over the substrate and fills the trench and the via hole. A portion of the second conductive layer and the adhesion layer are removed to expose the dielectric layer.

Abstract: A method for forming a metal plug is provided. The method is used to form a metal plug without a hole on a glue/barrier layer within a trench when the glue/barrier layer has been formed for a while. A substrate with a trench therein and a glue/barrier layer formed conformal to the profile of the substrate is provided. A post-treatment is performed on the glue/barrier layer to prevent moisture absorption and to make the glue/barrier become dense. The post-treatment comprises a plasma treatment or a deep UV plus laser treatment. After performing the post-treatment step, a metal layer is formed on the glue/barrier layer at least to fill in the trench. The metal layer other than that filling the trench is removed to form a metal plug.

Abstract: A fabricating method of a capacitor includes two gates and a commonly used source/drain region formed on a substrate. Then, a process of sell align contact has been applied to make a pitted self align contact window (PSACW) to partly expose the commonly used source/drain region. Then an glue/barrier layer and a lower electrode of the capacitor are formed over the PSACW. Then a dielectric thin film with a material having high dielectric constant is formed over the lower electrode. Then, an upper electrode is formed over the dielectric thin film to complete a capacitor, which has a structure of metal insulator metal with a shape like the PSACW.

Abstract: A method is provided for forming barrier layers in channel or via openings of semiconductors by using in-situ nitriding of barrier metals (Ta, Ti, or W) after they have been deposited in channel and via openings which will allow better control of the barrier metal/barrier material (Ta/TaN, Ti/TiN, or W/WN) composition, eliminate particle problems, and avoiding target poisoning.

Abstract: The invention concerns a method of forming a layer of metal on a substrate and fill the via with high throughput. A layer of metal can be formed on a substrate using sequentially a cold deposition step, a slow hot deposition step and a rapid hot deposition step. The cold deposition step need only be performed for a time sufficient to deposit a seed layer of metal over the entire surface on which the metal layer is to be formed. In the slow hot deposition step, further metal is deposited at a low power allowing for surface diffusion of the deposited metal, which is then followed by a rapid hot deposition of metal under bulk diffusion conditions.

Abstract: The present invention pertains to a carrier layer and a contact enabled by the carrier layer which enables the fabrication of aluminum (including aluminum alloys and other conductive materials having a similar melting point) electrical contacts in multilayer integrated circuit vias, through holes, or trenches having an aspect ratio greater than one. In fact, the structure has been shown to enable such contact fabrication in vias, through holes, and trenches having aspect ratios as high as at least 5:1, and should be capable of filing apertures having aspect ratios up to about 12:1. The carrier layer, in addition to permitting the formation of a conductive contact at high aspect ratio, provides a diffusion barrier which prevents the aluminum from migrating into surrounding substrate material which operates in conjunction with the electrical contact.

Abstract: A method of fabricating an interconnect wherein there is initially provided a first layer of electrically conductive interconnect (3). A via (7) is formed which is defined by walls extending to the first layer of interconnect. A layer of titanium (9) is formed between the electrically conductive interconnect and the first layer of electrically conductive metal (11). A first layer of electrically conductive metal is formed on the walls of the via having a predetermined etch rate relative to a specific etch species and a second layer of electrically conductive metal (13) is formed on the first layer of electrically conductive metal having an etch rate relative to the specific etch species greater than the first layer and which preferably extends into the via.

Abstract: The present invention provides a method for forming barrier layers in a channel or via opening by using a plasma etching technique to etch back the barrier layer which reduces the electrical resistance of the barrier layer, maintains its barrier effectiveness and enhances the subsequent filling of the channel or via opening by conductive materials.

Abstract: A method for reducing the stress on a titanium nitride layer formed by collimator sputtering. On a semiconductor substrate, an insulated oxide layer is formed. A trench is formed in the insulated oxide layer. On the trench, a first titanium nitride layer is formed conformally by using physical or chemical vapor deposition as a buffer layer. A second titanium nitride layer is formed by collimator sputtering on the first titanium layer. The orientation of lattice arrangement of the second titanium nitride layers is changed from <100>-orientation to <111>-orientation, and therefore, the stress is reduced.

Abstract: A method for planarizing the interface of polysilicon and silicide in a polycide structure is presented in this invention. It is by regulating the process temperature when depositing polysilicon to meanwhile improve its planarization. At first, a doped polysilicon layer is deposited on a semiconductor substrate in the integrated circuits, then immediately after the deposition of an undoped polysilicon, the process temperature is reduced and the treatment of purging is followed with, finally, a metal silicide is formed on the undoped polysilcion.

Abstract: There is provided a method of fabricating a semiconductor including the steps, in this order, of (a) forming an interlayer insulating film on a semiconductor substrate, (b) forming a first TiN film on the interlayer insulating film by sputtering, (c) forming a hole throughout the interlayer insulating film to thereby cause the semiconductor substrate to appear, (d) forming a second TiN film over the first TiN film by chemical vapor deposition to thereby fill the hole with the second TiN film, and (e) removing the first and second TiN films except TiN filling the hole therewith. When a Ti or TiN film having a thickness sufficient to fill a contact hole or a through-hole therewith is to be formed by CVD even at low temperature, the this method prevents the Ti or TiN film from being cracked or peeled off.

Abstract: A method of minimizing intragranular oxidation of TiON and providing a low resistivity film that provides for highly textured metal overlayers. The method provides an in situ diffusion barrier for subsequent high temperature metal deposition or processes. An in situ process eliminates the need for a fortification anneal immediately following the barrier deposition, thus reducing the number of metal processing steps and providing for a more economical process or for subsequent high temperature metal deposition. The surface properties of the TiON allow for improved texture in those metal overlayers as well as low diffusion barrier resistivity.

Abstract: A method for forming metal interconnection of semiconductor device is disclosed. In the present invention, an aluminum layer in the 10 to 100 .ANG. range is deposited on the bottom of the contact before or after the deposition of a titanium layer for barrier metal, which forms TiAl.sub.3 by the reaction of titanium and aluminum. According to the invention, stable contact resistance and low leakage current can be obtained in the application of ultra shallow junction.

Abstract: A TiN.sub.x layer is formed by disposing a substrate (18) in a chamber (12). A first reactant gas (40) comprising Ti, a second reactant gas (42) and a third reactant gas (44) comprising N are introduced into the chamber (12). By controlling the ratio of the first, second and third reactant gasses (40, 42, 44), TiN.sub.x is deposited onto a surface (28) of the substrate (18), where x is between zero and one.

Abstract: A process for fabricating contact plugs for semiconductor IC devices. An insulating layer is formed over the surface of an IC substrate. The insulating layer is then patterned for forming contact vias revealing the surface of an electrically conductive region of the IC circuitry that requires electrical connections by the contact plugs. A glue (adhesive) layer is then formed over the sidewall surface inside the contact vias. The glue (adhesive) layer is densified by either a rapid thermal annealing or a plasma treatment in order to prevent the formation of voids when the plugs are formed. The internal space of the contact vias are then filled with an electrically conductive material to form the contact plugs.