Abstract: The invention included to methods of forming CoSi2, methods of forming field effect transistors, and methods of forming conductive contacts. In one implementation, a method of forming CoSi2 includes forming a substantially amorphous layer comprising MSix over a silicon-containing substrate, where “M” comprises at least some metal other than cobalt. A layer comprising cobalt is deposited over the substantially amorphous MSix-comprising layer. The substrate is annealed effective to diffuse cobalt of the cobalt-comprising layer through the substantially amorphous MSix-comprising layer and combine with silicon of the silicon-containing substrate to form CoSi2 beneath the substantially amorphous MSix-comprising layer. Other aspects and implementations are contemplated.

Abstract: Provided is a method of depositing a noble metal layer using an oxidation-reduction reaction. The method includes flowing a noble metal source gas, an oxidizing gas, and a reducing gas into a reaction chamber; and generating plasma in the reaction chamber to form a noble metal layer or a noble metal oxide layer on a bottom structure.

Abstract: A method of integrated processing of a patterned substrate for copper metallization. The method includes providing the patterned substrate containing a via and a trench in a vacuum processing tool, and performing an integrated process on the patterned substrate in the vacuum processing tool by depositing a first metal-containing layer over the patterned substrate, removing by sputter etching the first metal-containing layer from the bottom of the via and at least partially removing the first metal-containing layer from the bottom of the trench, depositing a conformal Ru layer onto the sputter etched first metal-containing layer, depositing a non-conformal Cu layer on the conformal Ru layer, and plating Cu over the patterned substrate. According to one embodiment of the invention, the method can further include depositing a second metal-containing layer onto the sputter etched first metal-containing layer prior to depositing the conformal Ru layer.

Abstract: Provided is a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, without limitation, includes forming a first semiconductor layer over a substrate, and forming a second semiconductor layer over the first semiconductor layer, wherein an amorphous nitrided silicon adhesion layer is located between and adheres the first and second semiconductor layers.

Abstract: A sputter-etching method employed to achieve a thinned down noble metal liner layer deposited on the surface or field of an intermediate back end of the line (BEOL) interconnect structure. The noble metal liner layer is substantially thinned down to a point where the effect of the noble metal has no significant effect in the chemical-mechanical polishing (CMP) process. The noble metal liner layer may be completely removed by sputter etching to facilitate effective planarization by chemical-mechanical polishing to take place.

Abstract: A method for fabricating a conductive layer is provided. First, a substrate is provided and a patterned adhesion layer is formed on the substrate. Next, a chemical plating process is performed to form a first metal layer on the patterned adhesion layer by placing the substrate in an electroplating solution and the electroplating solution is shocked. Thereafter, a second metal layer is formed on the first metal layer by performing a plating process.

Abstract: Embodiments of the invention provide processes for vapor depositing tungsten-containing materials, such as metallic tungsten and tungsten nitride. In one embodiment, a method for forming a tungsten-containing material is provided which includes positioning a substrate within a processing chamber containing a lid plate, heating the lid plate to a temperature within a range from about 120° C. to about 180° C., exposing the substrate to a reducing gas during a pre-nucleation soak process, and depositing a first tungsten nucleation layer on the substrate during a first atomic layer deposition process within the processing chamber. The method further provides depositing a tungsten nitride layer on the first tungsten nucleation layer during a vapor deposition process, depositing a second tungsten nucleation layer on the tungsten nitride layer during a second atomic layer deposition process within the processing chamber, and exposing the substrate to another reducing gas during a post-nucleation soak process.

Abstract: A copper interconnection structure which is electroplated onto a silicon layer or semiconductor substrate. The structure includes an ultra-thin copper seed alloy incorporating selectively minor amounts of a dopant material to facilitate a continuous deposition thereof onto the silicon layer or semiconductor substrate. The copper seed alloy may contain dopant material selected from the group of materials consisting of Ru, Ir, Pt, Pd and alloys thereof. Furthermore, there is provided a method for producing the structure.

Abstract: A technique capable of improving reliability of a semiconductor apparatus is provided. A semiconductor device having a metal electrode on at least one principal surface and a die pad (a metal member) electrically connected to the metal electrode via conductive resin composed of base resin (an organic binder) mixed with a Ag particle (metal powder) including precious metal are provided, and a configuration is made so that a porous nano-particle coat film (a precious metal layer) having an Ag (precious metal) nano particle fired on a metal surface is formed on at least one of mutually opposed surfaces of the metal electrode and the die pad.

Abstract: Embodiments include an interconnect or trace of electrically conductive material with a contact surface, and a dielectric layer overlying the contact surface with a via formed on the dielectric layer and to the contact surface. The via sidewalls and perimeter are layered with a manganese oxide (MnO2) layer which is layered over with a conductive polymer material. An interconnect material is formed in the via and in a trench above the perimeter of the via such that the interconnect material is on the conductive polymer material and contacts the contact surface. An additional dielectric layer may be formed over the interconnect material and an additional via may be formed therethrough so that an additional structure having a MnO2 layer, conductive polymer material, and interconnect material can be formed in the additional via and to the interconnect material.

Abstract: A CMOS gate stack that increases the inversion capacitance compared to a conventional CMOS gate stack has been described. Using a poly-SiGe gate, instead of the conventional poly-Si gate near the gate dielectric layer, increases the amount of implanted dopant that can be activated. This increase overcomes the polysilicon depletion problem that limits the inversion capacitance in the conventional CMOS gate stack. To integrate the poly-SiGe layer into the gate stack, a thin ?-Si layer is deposited between the gate dielectric layer and the poly-SiGe layer. To ensure proper salicide formation, a poly-Si layer is capped over the poly-SiGe layer. In order to obtain a fined-grained poly-Si over poly-SiGe, a second ?-Si layer is deposited between the poly-Si layer and the poly-SiGe layer.

Abstract: A phase change memory material may be deposited over an electrode in a pore through an insulator. The adherence of the memory material to the insulator may be improved by using a glue layer. At the same time, a breakdown layer may be formed in the pore between the memory material and electrode.

Abstract: A semiconductor device having a semiconductor substrate, at least one of a protruding electrode and wiring formed on one surface of the semiconductor substrate, and a first resin film formed on this surface. The first resin film has elasticity low enough to reduce stress induced by a difference in thermal expansion coefficient between the semiconductor substrate and the first resin film. A second resin film, having higher elasticity or higher strength than the first resin film, may be formed on the other surface of the semiconductor substrate.

Abstract: A method is provided for forming wafer level package that incorporates dual compliant layers and a metal cap layer on top of I/O pads. The wafer level package includes a plurality of metal cap layers formed on top of a plurality of I/O pads to function as stress buffering and avoiding sharp corners in metal traces formed on top of the metal cap layers. A first compliant layer and a second compliant layer are formed under the metal trace to provide the necessary standoff and to accommodate differences in coefficients of thermal expansion of the various materials on an IC die. The wafer level package is particularly suitable for copper devices or in devices wherein copper lines are used.

Abstract: Disclosed are a metal interconnection structure of a semiconductor device and a method for manufacturing the same. The structure includes an upper interlayer dielectric layer pattern including fluorine (F), an upper metal interconnection in the upper interlayer dielectric layer pattern and connecting with a lower metal interconnection formed in a lower interlayer dielectric layer pattern. The lower interlayer dielectric layer pattern can include a barrier pattern provided below the upper interlayer dielectric layer pattern to inhibit diffusion of F, an adhesion layer pattern below the barrier layer pattern, and a silicon-oxy-carbide (SiOC) layer pattern below the adhesion layer pattern. In order to inhibit F from penetrating into a neighboring interlayer dielectric layer, the barrier layer can include boron (B), which can combine with F, thereby inhibiting diffusion of the F. Accordingly, the increase of the dielectric constant of an SiOC layer due to diffusion of F is inhibited.

Abstract: An interlayer insulation layer is formed on a semiconductor substrate to cover a lower wiring layer that is also formed on the semiconductor substrate. A contact hole to expose a surface of the lower wiring layer is formed by etching the interlayer insulation film. A wetting layer is formed on an inner wall of the contact hole. An anti-deposition layer is formed around an entrance of the contact hole to prevent an aluminum layer from being deposited around the entrance of the contact hole. The contact hole is filled with the aluminum layer.

Abstract: Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming barrier metals on first electrodes provided on a chip of the semiconductor device, implementing a predetermined test on the semiconductor device by applying a signal to the semiconductor device via at least one of the barrier metals, and forming second protruded electrodes on the barrier metals. The predetermined tests are implemented before forming second protruded electrodes on the barrier metals.

Abstract: The invention is a chemically grown oxide layer which prevents dopant diffusion between semiconductor layers. The chemically grown oxide layer may be so thin that it does not form a barrier to electrical conduction, and thus may be formed within active devices such as diodes or bipolar transistors. Such a chemically grown oxide film is advantageously used to prevent dopant diffusion in a vertically oriented polysilicon diode formed in a monolithic three dimensional memory array.

Abstract: A method for fabricating an electronic component, includes forming a seed film above a base body, cooling said seed film, and putting the cooled seed film into a plating solution to perform electro-plating with said seed film being as a cathode.

Abstract: A method for forming an Al interconnect is disclosed. A disclosed method comprises: depositing a Ti layer on a substrate having predetermined devices; depositing a TiN layer on the entire surface of the Ti layer by performing a CVD process; performing a plasma treatment for the TiN layer; depositing an Al layer on the TiN layer; and forming an ARC on the entire surface of the Al layer.

Abstract: After a first adhesive layer having high adhesion to a supporting base is locally formed, a second adhesive layer having low adhesion to the supporting base is formed all over the supporting base so as to cover the first adhesive layer. When a wiring structure is separated, a predetermined portion of the wiring structure where the first adhesive layer is formed is cut to thereby separate the integrated wiring structure and second adhesive layer from the first adhesive layer.

Abstract: A method for forming a via in an integrated circuit packaging substrate includes embedding an interfacial adhesion layer at a base of a via, and heating the materials at the base of the via. Embedding the interfacial adhesion layer further includes placing a conductive material over the interfacial adhesion layer. An interfacial layer material is deposited within at the base of opening and a conductive material is placed over the interfacial material. The interfacial layer material is a material that will diffuse into the conductive material at the temperature produced by heating the materials at the base of the via opening. Heating the materials at the base of the via opening includes directing energy from a laser at the base of the opening. An integrated circuit packaging substrate includes a first layer of conductive material, and a second layer of conductive material.

Abstract: The present application discloses process comprising providing a wafer, the wafer comprising an inter-layer dielectric (ILD) having a feature therein, an under-layer deposited on the ILD, and a barrier layer deposited on the under-layer, and a conductive layer deposited in the feature, placing the wafer in an electrolyte, such that at least the barrier layer is immersed in the electrolyte, and applying an electrical potential between the electrode and the wafer.

Abstract: Electronic devices are constructed by a method that includes forming a first conductive layer in an opening in a multilayer dielectric structure supported by a substrate, forming a core conductive layer on the first conductive layer, subjecting the core conductive layer to a H2 plasma treatment, and depositing a capping adhesion/barrier layer on the core conductive layer after the H2 plasma treatment. The multilayer dielectric structure provides an insulating layer for around the core conducting layer and at least one sacrificial layer for processing. The H2 plasma treatment removes unwanted oxide from the surface region of the core conducting layer such that the interface between the core conducting layer and the capping adhesion/barrier is substantially free of oxides. In an embodiment, the core conducting layer is copper with a titanium nitride or zirconium capping adhesion/barrier layer.

Abstract: A process for making semiconductor structures uses a decoupled plasma source to produce a highly selective plasma etchant to form a structure with a thin adhesive layer and overlaying conductive layer. The preferred plasma is formed from chlorine and oxygen feed gases. The highly conductive semiconductor structure has a thickness less than about 3000 ?, preferably less than about 2600 ?, and incorporates an adhesive layer that is preferably less than about 100 ? thick. Despite the reduced profile and topography of the structure, it is more conductive than prior structures, and provides a robust device.

Abstract: A metal structure for a contact pad of a wafer or substrate (101), which have copper interconnecting traces (102) surrounded by a barrier metal layer (103). The wafer or substrate is protected by an insulating overcoat (104). In the structure, the barrier metal layer is selectively exposed by a window (110) in the insulating overcoat. A layer of copper (105), adherent to the barrier metal, conformally covers the exposed barrier metal. Preferably, the copper layer is deposited by sputtering using a shadow mask. A layer of nickel (106) is adherent to the copper layer and a layer of noble metal (106) is adherent to the nickel layer. The noble metal may be palladium, or gold, or a palladium layer with an outermost gold layer. Preferably, the nickel and noble metal layers are deposited by electroless plating.

Abstract: An apparatus incorporating small-feature size and large-feature-size components. The apparatus comprise a strap including a substrate with an integrated circuit contained therein. The integrated circuit coupling to a first conductor disposed on the substrate. The first conductor is made of a thermosetting or a thermoplastic material including conductive fillers. A large-scale component having a second conductor is electrically coupled to the first conductor to electrically couple the large-scale component to the integrated circuit. The large-scale component includes a second substrate.

Abstract: A method of forming a conductive structure is disclosed. The method includes forming an interconnect in a substrate, and forming a layer of iridium on the interconnect. The layer of iridium has a thickness of less than six hundred angstroms. The method further includes annealing the layer of iridium, forming a dielectric layer on the layer of iridium, and forming a conductive layer on the dielectric layer.

Abstract: A composite film comprised of three layers is formed by ALD on a substrate with a substrate interface surface. A first layer is coupled to the substrate interface surface. The first layer provides adhesion to the substrate interface surface and initiation of layer by layer ALD growth. A second layer is positioned between the first and third layers and provides a conducting diffusion barrier between the substrate and subsequent overlaying film. A third layer has a surface that is configured to provide adhesion and a texture template in preparation for a subsequent overlaying film. The composite engineered barrier structures are applied to interconnect, capacitor and transistor applications.

Abstract: An apparatus comprising an insulating substrate (101) having first and second surfaces (101a, 101b) and a plurality of metal-filled vias (102) extending from the first to the second surface. The first and second surfaces have contact pads (103, 104), each one comprising a connector stack to at least one of the vias. The stack comprises a seed metal layer (110, copper) in contact with the via metal capable of providing an adhesive and conductive layer for electroplating on its surface, a first electroplated support layer (111a, copper) secured to the seed metal layer, a second electroplated support layer (111b, nickel), and at least one reflow metal bonding layer (112, palladium, gold) on the second support layer. The electrolytic plating process produces support layers substantially pure (at least 99.0%), free of unwanted additives such as phosphorus or boron, and exhibiting closely controlled grain sizes. Reflow metal connectors (220, 230) provide attachment to chip contact pads and external parts.

Abstract: A direct imprinting process for Step and Flash Imprint Lithography includes providing (40) a substrate (12); forming (44) an etch barrier layer (14) on the substrate; patterning (46) the etch barrier layer with a template (16) while curing with ultraviolet light through the template, resulting in a patterned etch barrier layer and a residual layer (20) on the substrate; and performing (48) an etch to substantially remove the residual layer. Optionally, a patterning layer (52) may be formed on the substrate (12) prior to forming the etch barrier layer (14). Additionally, an adhesive layer (13) may be applied (42) between the substrate (12) and the etch barrier layer (14).

Abstract: A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on the high-k gate dielectric layer, a second metal layer is formed on the first metal layer. At least part of the second metal layer is removed from above the dielectric layer using a polishing step, and additional material is removed from above the dielectric layer using an etch step.

Abstract: The present invention provides, in one embodiment, method of forming a barrier layer 300 over a semiconductor substrate 110. The method comprises forming an opening 120 in an insulating layer 130 located over a substrate thereby uncovering an underlying copper layer 140. The method further comprises exposing the opening and the underlying copper layer to a plasma-free reducing atmosphere 200 in the presence of a thermal anneal. The also comprises depositing a barrier layer in the exposed opening and on the exposed underlying copper layer. Such methods and resulting conductive structures thereof may be advantageously used in methods to manufacture integrated circuits comprising copper interconnects.

Abstract: A method of fabricating an integrated circuit can include forming a barrier layer along lateral side walls and a bottom of a via aperture, forming a seed layer proximate and conformal to the barrier layer, and ion implanting elements into the seed layer. The via aperture is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer.

Abstract: An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion of the surface of the first layer. A binding layer is formed on the dielectric layer and on the exposed portion of the surface of the first layer and a second layer of conductive material is formed on the conductive binding layer. The binding layer can be an oxide and the second layer a conductive material that is diffusible into an oxide. The electrode structure can be annealed to cause conductive material from the second layer to be chemisorbed into the binding layer to improve adhesion between the first and second layers. A programmable cell can be formed by forming a doped glass layer in the electrode structure.

Abstract: A method and system to form a refractory metal layer on a substrate features nucleating a substrate using sequential deposition techniques in which the substrate is serially exposed to first and second reactive gases followed by forming a layer, employing vapor deposition, to subject the nucleation layer to a bulk deposition of a compound contained in one of the first and second reactive gases.

Abstract: A copper filled semiconductor feature and method of forming the same having improved bulk properties the method including providing a semiconductor process wafer having a process surface including an opening for forming a semiconductor feature; depositing at least one metal dopant containing layer over the opening to form a thermally diffusive relationship to a subsequently deposited copper layer; depositing said copper layer to substantially fill the opening; and, thermally treating the semiconductor process wafer for a time period sufficient to distribute at least a portion of the metal dopants to collect along at least a portion of the periphery of said copper layer including a portion of said copper layer grain boundaries.

Abstract: A method for conductive line of semiconductor device is disclosed. A cobalt silicide layer is formed on an impurity junction region exposed through a contact hole. The cobalt silicide layer stabilizes a contact resistance so that the contact resistance of the impurity junction region does not vary in subsequent thermal processes.

Abstract: A deposition method includes, at a first temperature, contacting a substrate with a surface activation agent and adsorbing a first layer over the substrate. At a second temperature greater than the first temperature, the first layer may be contacted with a first precursor, chemisorbing a second layer at least one monolayer thick over the substrate. The first layer may enhance a chemisorption rate of the first precursor compared to the substrate without the surface activation agent adsorbed thereon. One deposition apparatus includes a deposition chamber with a precursor gas dispenser in a contacting zone and a cooling gas dispenser in a cooling zone. A substrate chuck moves by linear translational motion from the contacting zone to the cooling zone. The substrate chuck includes a substrate lift that positions a deposition substrate at an elevation above a heated surface of the substrate chuck when dispensing a cooling gas or surface activation agent.

Abstract: A multilayer copper structure has been provided for improving the adhesion of copper to a diffusion barrier material, such as TiN, in an integrated circuit substrate. The multilayer copper structure comprises a thin high-resistive copper layer to provide improved adhesion to the underlying diffusion barrier layer, and a low-resistive copper layer to carry the electrical current with minimum electrical resistance. The invention also provides a method to form the multilayer copper structure.

Abstract: An electrical interconnection for a highly integrated semiconductor device includes a first insulation layer having at least a first recessed portion on a substrate. The first recessed portion is filled with metal to form a first metal pattern. A diffusion barrier layer including aluminum oxide of high light transmittance is provided on the first insulation layer and the first metal pattern for preventing metal from diffusing. An insulating interlayer including a second recessed portion for exposing an upper surface of the first metal pattern is provided on the diffusion barrier layer. The second recessed portion is filled with metal to form a second metal pattern. The electrical interconnection may be used with an image sensor. The metal may be copper. High light transmittance of the diffusion barrier layer ensures external light reaches the photodetector. The aluminum oxide of the diffusion barrier layer reduces parasitic capacitance of the electrical interconnections.

Abstract: Methods and compositions are disclosed for modifying a semiconductor interconnect layer to reduce migration problems while minimizing resistance increases induced by the modifications. One method features creating trenches in the interconnect layer and filling these trenches with compositions that are less susceptible to migration problems. The trenches may be filled using traditional vapor deposition methods, or electroplating, or alternately by using electroless plating methods. Ion implantation may also be used as another method in modifying the interconnect layer. The methods and compositions for modifying interconnect layers may also be limited to the via/interconnect interface for improved performance. A thin seed layer may also be placed on the semiconductor substrate prior to applying the interconnect layer. This seed layer may also incorporate similar dopant and alloying materials in the otherwise pure metal.

Abstract: An integrated method comprises providing a low dielectric material, applying a first treatment altering a first property of the low dielectric material, and applying a second treatment altering a second property of the treated low dielectric material and producing a lower dielectric material with better mechanical stability.

Abstract: Apparatus and method for treating a surface of a substrate for electrolytic or electroless plating of metals in integrated circuit manufacturing. In one embodiment the method includes forming a barrier layer on a substrate. A metal-seed layer is then formed on the barrier layer. The method continues by performing in situ surface treatment of the metal-seed layer to form a passivation layer on the metal-seed layer. In another embodiment of a method of this invention, a substrate is provided into an electroplating tool chamber. The substrate has a barrier layer formed thereon, a metal seed layer formed on the barrier layer and a passivation layer formed over the metal seed layer. The method continues by annealing the substrate in forming gas to reduce the passivation layer. A conductive material is deposited on the substrate using an electrolytic plating or electroless plating process.

Abstract: The present invention describes the use of polybenzoxazoles (PBOs) for adhesively bonding articles or materials, especially components used in the semiconductor industry, such as chips and wafers, a process for adhesively bonding materials, especially chips and wafers, chip and/or wafer stacks produced by the process, and adhesive compositions which comprise the polybenzoxazoles of the formula (I).

Abstract: Resin cloths, powders, specular bodies and other objects resistant to conventional plating can be plated with metals by a simple method. According to the metal plating method of the present invention, electroless plating is performed after the surface of a object to be plated is treated with a pretreatment agent obtained by reacting or mixing in advance a noble metal compound (catalyst) with a silane-coupling agent having functional groups capable of capturing metals. According to this method, metal plating can be securely applied to powders, resin cloths, semiconductor wafers, and other specular bodies. Moreover, the problem of the insufficient coverage of the seed layer on the inside walls of vias and trenches during the formation of fine wiring can be addressed by applying this method to semiconductor wafers. The silane-coupling agent may be a compound containing azole groups, preferably an imidazole.

Abstract: A physical vapor deposition process for maintaining the wafer below a critical temperature. The rate at which material particles are sputtered from the target and thus deposited on the wafer is controllable in response to power supplied to the target. Maintaining a desired deposition rate maintains the wafer temperature below the critical temperature.

Abstract: A depression is formed from a first surface of a semiconductor substrate. An insulating layer is provided on the bottom surface and an inner wall surface of the depression. A conductive portion is provided inside the insulating layer. A second surface of the semiconductor substrate is etched by a first etchant having characteristics such that the etching amount with respect to the semiconductor substrate is greater than the etching amount with respect to the insulating layer, and the conductive portion is caused to project while covered by the insulating layer. At least a portion of the insulating layer formed on the bottom surface of the depression is etched with a second etchant having characteristics such that at least the insulating layer is etched without forming a residue on the conductive portion, to expose the conductive portion.

Abstract: An integrated circuit chip 501 has a plurality of contact pads (FIG. 5B) to be connected by reflow attachment 510 to outside parts. The chip comprises a deposited layer 505 of nickel/titanium alloy on each of the pads; the alloy has a composition and crystalline structure operable in reversible phase transitions under thermomechanical stress, whereby mechanical strain is absorbed by the alloy layer. Preferably, the alloy has between 55.0 and 56.0 weight % nickel, between 44.0 and 45.0 weight % titanium, and a thickness in the range from 0.3 to 6.0 ?m, recrystallized after deposition in a temperature range from 450 to 600° C. for a time period between 4 and 6 min. A layer 506 of solderable metal is on the alloy, operable as diffusion barrier after reflow attachment.