Abstract: It is an object of the present invention to provide a power semiconductor device, which is capable of being operable regardless of thermal stress generation, reducing a heat generation from wire, securing the reliability of bonding portion when the device is used for dealing with a large amount current and/or under a high temperature atmosphere, a method of manufacturing the device and a bonding wire. In a power semiconductor device in which a metal electrode (die electrode 3) on a power semiconductor die 2 and another metal electrode (connection electrode 4) are connected by metal wire 5 using wedge bonding connection, the metal wire is Ag or Ag alloy wire of which diameter is greater than 50 ?m and not greater than 2 mm and the die 3 has thereon one or more metal and/or alloy layers, each of the layer(s) being 50 ? or more in thickness and a metal for the layer is selected from Ni, Cr, Cu, Pd, V, Ti, Pt, Zn, Ag, Au, W and Al.

Abstract: The invention provides a method of forming a film stack on a substrate, comprising performing a silicon containing gas soak process to form a silicon containing layer over the substrate, reacting with the silicon containing layer to form a tungsten silicide layer on the substrate, depositing a tungsten nitride layer on the substrate, subjecting the substrate to a nitridation treatment using active nitrogen species from a remote plasma, and depositing a conductive bulk layer directly on the tungsten nitride layer.

Abstract: A contact to a semiconductor including sequential layers of Cr, Ti, and Al is provided, which can result in a contact with one or more advantages over Ti/Al-based and Cr/Al-based contacts. For example, the contact can: reduce a contact resistance; provide an improved surface morphology; provide a better contact linearity; and/or require a lower annealing temperature, as compared to the prior art Ti/Al-based contacts.

Abstract: Disclosed are apparatus and method embodiments for achieving etch and/or deposition selectivity in vias and trenches of a semiconductor wafer. That is, deposition coverage in the bottom of each via of a semiconductor wafer differs from the coverage in the bottom of each trench of such wafer. The selectivity may be configured so as to result in punch through in each via without damaging the dielectric material at the bottom of each trench or the like. In this configuration, the coverage amount deposited in each trench is greater than the coverage amount deposited in each via.

Abstract: One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed.

Abstract: Methods of forming titanium-containing layers on substrates are disclosed. In the disclosed methods, the vapor of a precursor compound having the formula Ti(Me5Cp)(OR)3, wherein R is selected from methyl, ethyl, or isopropyl is provided. The vapor is reacted with the substrate according to an atomic layer deposition process to form a titanium-containing complex on the surface of the substrate.

Abstract: One illustrative method disclosed herein includes forming a seed layer above a structure, forming a nucleation layer on the seed layer, forming a plurality of spaced-apart, vertically oriented alloy structures that are comprised of materials from the seed layer and the nucleation layer, forming a sacrificial material layer above the nucleation layer and around the alloy structures, performing an etching process to remove the alloy structures and portions of the seed layer so as to thereby define a plurality of openings, forming an initial masking structure in each of the openings, performing an etching process to remove the sacrificial material layer and the nucleation layer so as to thereby expose the structure and define a masking layer comprised of the initial masking structures, and performing at least one process operation on the structure through the masking layer.

Abstract: Electrodes, which contain molybdenum dioxide (MoO2) can be used in electronic components, such as memory or logic devices. The molybdenum-dioxide containing electrodes can also have little or no molybdenum element, together with a portion of molybdenum oxide, e.g., MoOx with x between 2 and 3. The molybdenum oxide can be present as molybdenum trioxide MoO3, or in Magneli phases, such as Mo4O11, MO8O23, or Mo9O26. The molybdenum-dioxide containing electrodes can be formed by annealing a multilayer including a layer of molybdenum and a layer of molybdenum oxide. The oxygen content of the multilayer can be configured to completely, or substantially completely, react with molybdenum to form molybdenum dioxide, together with leaving a small excess amount of molybdenum oxide MoOx with x>2.

Abstract: A wafer-level package device and techniques are described that include utilizing a dry-etch process for mitigating metal seed layer undercut. In an implementation, a process for fabricating the wafer-level package device that employs the techniques of the present disclosure includes processing a substrate, depositing a metal seed layer on the substrate, depositing and patterning a resist layer, depositing a redistribution layer structure, removing the photoresist layer, and dry-etching the metal seed layer. In implementations, the wafer-level package device that employs example techniques in accordance with the present disclosure includes a substrate, a metal seed layer disposed on the substrate, and a redistribution layer structure formed on the metal seed layer. The metal seed layer is dry-etched so that undercut is mitigated.

Abstract: Self-aligned pitch split techniques for metal wiring involving a hybrid (subtractive patterning/damascene) metallization approach are provided. In one aspect, a method for forming a metal wiring layer on a wafer includes the following steps. A copper layer is formed on the wafer. A patterned hardmask is formed on the copper layer. The copper layer is subtractively patterned using the patterned hardmask to form a plurality of first copper lines. Spacers are formed on opposite sides of the first copper lines. A planarizing dielectric material is deposited onto the wafer, filling spaces between the first copper lines. One or more trenches are etched in the planarizing dielectric material. The trenches are filled with copper to form a plurality of second copper lines that are self-aligned with the first copper lines. An electronic device is also provided.

Abstract: A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes conductive lines having sidewalls angled between about 45° to about 90° relative to a plane in which bottom surfaces of the conductive lines lie. A dielectric layer is formed over the conductive lines, where forming the dielectric layer after the conductive lines are formed mitigates damage to the dielectric layer, such as by not subjecting the dielectric layer to etching. The angled sidewalls of the conductive lines cause the dielectric layer to pinch off before an area between adjacent conductive lines is filled, thus establishing an air gap between adjacent conductive lines, where the air gap has a lower dielectric constant than the dielectric material. At least one of the substantially undamaged dielectric layer or the air gap serves to reduce parasitic capacitance within the semiconductor arrangement, which improves performance.

Abstract: An electronic fuse structure including etching a dual damascene feature in a dielectric layer, the dual damascene feature including a first via opening, a second via opening, and a trench opening, forming a seed layer within the dual damascene feature, the seed layer including a conductive material, and heating the dielectric layer and the seed layer causing the seed layer to reflow and fill the first via opening, the second via opening, and partially filling the trench opening to form a fuse line, a first via, and a second via. The structure further including forming an insulating layer on top of the fuse line, and forming a fill material on top of the insulating layer and substantially filling the trench opening.

Abstract: A system for forming self-aligned contacts includes electroplating a first metal contact onto a Group III-V semiconductor substrate, the first metal contact having a greater height than width and having a straight sidewall profile, etching back the semiconductor substrate down to a base layer to expose an emitter semiconductor layer under the first metal contact, conformally depositing a dielectric layer on a vertical side of the first metal contact, a vertical side of the emitter semiconductor layer and on the base layer, anisotropically etching the dielectric layer off of the semiconductor substrate to form a dielectric sidewall spacer on the vertical side of the first metal contact and providing a second metal contact immediately adjacent the dielectric sidewall spacer.

Abstract: A method for processing a substrate includes providing a substrate including a metal layer, a dielectric layer arranged on the metal layer, and at least one of a via and a trench formed in the dielectric layer; depositing a metal using chemical vapor deposition (CVD) during a first deposition period, wherein the first deposition period is longer than a first nucleation period that is required to deposit the metal on the metal layer; stopping the first deposition period prior to a second nucleation delay period, wherein the second nucleation period is required to deposit the metal on the dielectric layer; performing the depositing and the stopping N times, where N is an integer greater than or equal to one; and after the performing, depositing the metal using CVD during a second deposition period that is longer than the second nucleation delay period.

Abstract: In one embodiment method, a first Ti based layer is deposited on the substrate. An intermediate Al based layer is deposited on the first layer, a second NiV based layer is deposited on the intermediate layer, and a third Ag based layer is deposited on the second layer. The layer stack is tempered in such a way that at least one inter-metallic phase is formed between at least two metals of the group containing Ti, Al, Ni and V.

Abstract: Fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines and depositing a protective cap on at least some of the one or more conductive lines. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer pitches, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer line widths, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers.

Abstract: A method of manufacturing a semiconductor device capable of minimally preventing the property deterioration caused by the oxidation of a metal film, and a substrate processing apparatus are provided.

Abstract: Embodiments of the present invention relate to approaches for forming RMG FinFET semiconductor devices using a low-resistivity metal (e.g., W) as an alternate gap fill metal. Specifically, the semiconductor will typically comprise a set (e.g., one or more) of dielectric stacks formed over a substrate to create one or more trenches/channels (e.g., short/narrow and/or long/wide trenches/channels). A work function layer (e.g., TiN) will be provided over the substrate (e.g., in and around the trenches). A low-resistivity metal gate layer (e.g., W) may then be deposited (e.g., via chemical vapor deposition) and polished (e.g., via chemical-mechanical polishing). Thereafter, the gate metal layer and the work function layer may be etched after the polishing to provide a trench having the etched gate metal layer over the etched work function layer along a bottom surface thereof.

Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

Abstract: A nonvolatile semiconductor memory apparatus according to an embodiment includes: a semiconductor layer; a first insulating film formed on the semiconductor layer, the first insulating film being a single-layer film containing silicon oxide or silicon oxynitride; a charge trapping film formed on the first insulating film; a second insulating film formed on the charge trapping film; and a control gate electrode formed on the second insulating film. A metal oxide exists in an interface between the first insulating film and the charge trapping film, the metal oxide comprises material which is selected from the group of Al2O3, HfO2, ZrO2, TiO2, and MgO, the material is stoichiometric composition, and the charge trapping film includes material different from the material of the metal oxide.

Abstract: The present invention includes embodiments of a processing method, and resulting structure, for building a chip having a TSV pillar which can be used as an interconnecting structure. The process includes the deposition of a dual diffusion barrier between the TSV and the substrate the TSV is embedded within. The TSV is then exposed from the back side of the substrate so that at least a portion of the TSV protrudes from the substrate and can be used as a contact for connecting the chip to another surface. The resulting TSV is rigid, highly conductive, can be placed in a tightly pitched grid of contacts, and reduces effects of CTE mismatch.

Abstract: Provided are test vehicles for evaluating various semiconductor materials. These materials may be used for various integrated circuit components, such as embedded resistors of resistive random access memory cells. Also provided are methods of fabricating and operating these test vehicles. A test vehicle may include two stacks protruding through an insulating body. Bottom ends of these stacks may include n-doped poly-silicon and may be interconnected by a connector. Each stack may include a titanium nitride layer provided over the poly-silicon end, followed by a titanium layer over the titanium nitride layer and a noble metal layer over the titanium layer. The noble metal layer extends to the top surface of the insulating body and forms a contact surface. The titanium layer may be formed in-situ with the noble metal layer to minimize oxidation of the titanium layer, which is used as an adhesion and oxygen getter.

Abstract: Disclosed herein are through silicon vias (TSVs) and contacts formed on a semiconductor material, methods of manufacturing, and design structures. The method includes forming a contact hole in a dielectric material formed on a substrate. The method further includes forming a via in the substrate and through the dielectric material. The method further includes lining the contact hole and the dielectric material with a metal liner using a deposition technique that will avoid formation of the liner in the viaformed in the substrate. The method further includes filling the contact hole and the via with a metal such that the metal is formed on the liner in the contact hole and directly on the substrate in the via.

Abstract: A system and a method for protecting vias is disclosed. An embodiment comprises forming an opening in a substrate. A barrier layer disposed in the opening including along the sidewalls of the opening. The barrier layer may include a metal component and an alloying material. A conductive material is formed on the barrier layer and fills the opening. The conductive material to form a via (e.g., TSV).

Abstract: A method for forming a film includes the steps of: placing an object to be processed into a processing container; and generating M(BH4)4 gas by feeding H2 gas as carrier gas into a raw material container in which solid M(BH4)4 (where M is Zr or Hf) is accommodated to introduce a mixture gas of H2 gas and M(BH4)4 gas having a volume ratio of flow rates (H2/M(BH4)4) of 2 or more into the processing container, and deposit a MBx film (where M is Zr or Hf and x is 1.8 to 2.5) on the object using a thermal CVD.

Abstract: A method of forming a semiconductor device is disclosed. The method including providing a substrate with at least one insulating layer disposed thereon, the at least one insulating layer including a trench; forming at least one liner layer on the at least one insulating layer; forming a nucleation layer on the at least one liner layer; forming a first metal film on a surface of the nucleation layer; etching the first metal film; and depositing a second metal film on the etched surface of the first metal film, the second metal film substantially forming an overburden above the trench.

Abstract: A method for processing a wafer with a wafer bevel that surrounds a central region is provided. The wafer is placed in a bevel plasma processing chamber. A protective layer is deposited on the wafer bevel without depositing the protective layer over the central region. The wafer is removed from the bevel plasma processing chamber. The wafer is further processed.

Abstract: Disclosed herein are various methods of forming a metal cap layer on copper-based conductive structures on integrated circuit devices, and integrated circuit devices having such a structure. In one example, the method includes the steps of forming a conductive feature comprised of copper in a layer of insulating material, performing a metal removal process to remove a portion of the conductive feature and thereby define a recess above a residual portion of the copper feature, and performing a selective deposition process to form a cap layer comprised of cobalt, manganese, CoWP or NiWP within the recess.

Abstract: Disclosed is a method of forming wiring. The method includes the steps of: depositing a metal thin film (12) of copper (Cu) on a glass substrate (11) serving as a base; forming an insulating film or a metal insulating film (131) containing no Cu on the metal thin film (12); patterning a photoresist (14) by photolithography on the insulating film (131); etching a liner film (13) by isotropic dry etching using the photoresist (14) as an etching mask; and after the etching of the liner film (13), removing the photoresist (14), and then removing part of the metal thin film (12) by isotropic wet etching using the liner film (13) as an etching mask, thereby forming metal wiring (12a).

Abstract: Embodiments of the invention generally provide methods for depositing metal-containing materials and compositions thereof. The methods include deposition processes that form metal, metal carbide, metal silicide, metal nitride, and metal carbide derivatives by a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD.

Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

Abstract: To provide a semiconductor device having improved reliability by improving a coupling property between a semiconductor chip and a bonding wire. A redistribution layer is comprised of a Cu film, an Ni film, and a Pd film which have been formed successively from the side of a semiconductor substrate. The Pd film on the uppermost surface is used as an electrode pad and a bonding wire made of Cu is coupled to the upper surface of the Pd film. The thickness of the Pd film is made smaller than that of the Ni film and the thickness of the Ni film is made smaller than that of the Cu film. The Cu film, the Ni film, and the Pd film have the same pattern shape in a plan view.

Abstract: A manufacturing method of a semiconductor device including an electrode having low contact resistivity to a nitride semiconductor is provided. The manufacturing method includes a carbon containing layer forming step of forming a carbon containing layer containing carbon on a nitride semiconductor layer, and a titanium containing layer forming step of forming a titanium containing layer containing titanium on the carbon containing layer. A complete solid solution Ti (C, N) layer of TiN and TiC is formed between the titanium containing layer and the nitride semiconductor layer. As a result, the titanium containing layer comes to be in ohmic contact with the nitride semiconductor layer throughout the border therebetween.

Abstract: A wafer level semiconductor device and manufacturing method including providing a semiconductor device wafer substrate having a backside, applying to the backside a conductive metallization layer, and applying to the backside over the conductive metallization layer a protective metal layer of titanium, titanium alloys, nickel, nickel alloys, chromium, chromium alloys, cobalt or cobalt alloys, tungsten or tungsten alloys and palladium or palladium alloys.

Abstract: A method for preventing formation of metal silicide material on a wafer bevel is provided, where the wafer bevel surrounds a central region of the wafer. The wafer is placed in bevel plasma processing chamber. A protective layer is deposited on the wafer bevel. The wafer is removed from the bevel plasma processing chamber. A metal layer is deposited over at least part of the central region of the wafer, wherein part of the metal layer is deposited over the protective layer. Semiconductor devices are formed while preventing metal silicide formation on the wafer bevel.

Abstract: A multi-layer TiN film with reduced tensile stress and discontinuous grain structure, and a method of fabricating the TiN film are disclosed. The TiN layers are formed by PVD or IMP in a nitrogen plasma. Tensile stress in a center layer of the film is reduced by increasing N2 gas flow to the nitrogen plasma, resulting in a Ti:N stoichiometry between 1:2.1 to 1:2.3. TiN films thicker than 40 nanometers without cracks are attained by the disclosed process.

Abstract: A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.

Abstract: Atomic layer deposition methods as described herein can be advantageously used to form a metal-containing layer on a substrate. For example, certain methods as described herein can form a strontium titanate layer that has low carbon content (e.g., low strontium carbonate content), which can result in layer with a high dielectric constant.

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle.

Abstract: Disclosed is a solution composition for forming a thin film transistor including a zinc-containing compound, an indium-containing compound, and a compound including at least one metal or metalloid selected from the group consisting of hafnium (Hf), magnesium (Mg), tantalum (Ta), cerium (Ce), lanthanum (La), silicon (Si), germanium (Ge), vanadium (V), niobium (Nb), and yttrium (Y). A method of forming a thin film by using the solution composition, and a method of manufacturing thin film transistor including the thin film are also disclosed.

Abstract: In semiconductor devices, integrity of a titanium nitride material may be increased by exposing the material to an oxygen plasma after forming a thin silicon nitride-based material. The oxygen plasma may result in an additional passivation of any minute surface portions which may not be appropriately covered by the silicon nitride-based material. Consequently, efficient cleaning recipes, such as cleaning processes based on SPM, may be performed after the additional passivation without undue material loss of the titanium nitride material. In this manner, sophisticated high-k metal gate stacks may be formed with a very thin protective liner material on the basis of efficient cleaning processes without unduly contributing to a pronounced yield loss in an early manufacturing stage.

Abstract: A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The SC2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate.

Abstract: Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an ILD to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD; and filling the recesses with an insulating material to leave unrecessed edges of the first conductive spacers as vias to subsequent wiring features.

Abstract: A semiconductor device and a manufacturing method thereof are disclosed. The method comprises: providing a substrate with a first dielectric layer and a gate, wherein the gate is embedded in the first dielectric layer and an upper portion of the gate is an exposed first metal; and covering only the exposed first metal with a conductive material that is harder to be oxidized than the first metal by a selective deposition. An advantage of the present invention is that the metal of the upper surface of the gate is prevented from being oxidized by covering the metal gate with the conductive material that is relatively harder to be oxidized, thereby facilitating the formation of an effective electrical connection to the gate.

Abstract: The present invention provides a transfer substrate for transferring a metal wiring material to a transfer-receiving object, the transfer substrate comprising a substrate, at least one metal wiring material formed on the substrate and an underlying metal film formed between the substrate and the metal wiring material, wherein the metal wiring material is a molded article prepared by sintering, e.g., gold powder having a purity of 99.9% by weight or more and an average particle size of 0.01 ?m to 1.0 ?m and the underlying metal film is composed of a metal such as gold or an alloy. The transfer substrate is capable of transferring a metal wiring material to the transfer-receiving object even at a temperature for heating the transfer-receiving object of 80 to 300° C.

Abstract: Metallic layers can be selectively deposited on surfaces of a substrate relative to a second surface of the substrate. In preferred embodiments, the metallic layers are selectively deposited on copper instead of insulating or dielectric materials. In preferred embodiments, a first precursor forms a layer or adsorbed species on the first surface and is subsequently reacted or converted to form a metallic layer. Preferably the deposition temperature is selected such that a selectivity of above about 90% is achieved.

Abstract: In MRAM, a write wiring clad in a ferromagnetic film has been used to reduce a write current or avoid disturbances. Besides, a CuAl wiring obtained by adding a trace of Al to a Cu wiring has been used widely to secure reliability of a high reliability product. There is a high possibility of MRAM being mounted in high reliability products so that reliability is important. Clad wiring however increases the resistance of the CuAl wiring, which is originally high, so that using both may fail to satisfy the specification of the wiring resistance. In the semiconductor device of the invention having plural copper-embedded wiring layers, copper wiring films of plural copper-embedded clad wirings configuring a memory cell matrix region of MRAM are made of relatively pure copper, while a CuAl wiring film is used as copper wiring films of copper-embedded non-clad wirings below these wiring layers.

Abstract: A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.

Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

Abstract: Native oxides and associated residue are removed from surfaces of a substrate by sequentially performing two plasma cleaning processes on the substrate in a single processing chamber. The first plasma cleaning process removes native oxide formed on a substrate surface by generating a cleaning plasma from a mixture of ammonia (NH3) and nitrogen trifluoride (NF3) gases, condensing products of the cleaning plasma on the native oxide to form a thin film that contains ammonium hexafluorosilicate ((NH4)2SiF6), and subliming the thin film off of the substrate surface. The second plasma cleaning process removes remaining residues of the thin film by generating a second cleaning plasma from nitrogen trifluoride gas. Products of the second cleaning plasma react with a few angstroms of the bare silicon present on the surface, forming silicon tetrafluoride (SiF4) and lifting off residues of the thin film.