Abstract: Bottom-up fill dielectric materials for semiconductor structure fabrication, and methods of fabricating bottom-up fill dielectric materials for semiconductor structure fabrication, are described. In an example, a method of fabricating a dielectric material for semiconductor structure fabrication includes forming a trench in a material layer above a substrate. A blocking layer is formed partially into the trench along upper portions of sidewalls of the trench. A dielectric layer is formed filling a bottom portion of the trench with a dielectric material up to the blocking layer. The blocking layer is removed. The forming the blocking layer, the forming the dielectric layer, and the removing the blocking layer are repeated until the trench is completely filled with the dielectric material.

Abstract: An electrochemical plating (ECP) system is provided. The ECP system includes an ECP cell comprising a plating solution for an ECP process, a sensor configured to in situ measure an interface resistance between a plated metal and an electrolyte in the plating solution as the ECP process continues, a plating solution supply system in fluid communication with the ECP cell and configured to supply the plating solution to the ECP cell, and a control system operably coupled to the ECP cell, the sensor and the plating solution supply system. The control system is configured to compare the interface resistance with a threshold resistance and to adjust a composition of the plating solution in response to the interface resistance being below the threshold resistance.

Abstract: Methods, systems, and apparatus for coating the internal surface of nano-scale cavities on a substrate are contemplated. A first fluid of high wettability is applied to the nano-scale cavity, filling the cavity. A second fluid carrying a conductor or a catalyst is applied over the opening of the nano-scale cavity. The second fluid has a lower vapor pressure than the first fluid. The first fluid is converted to a gas, for example by heating the substrate. The gas exits the nano-scale cavity, creating a negative pressure or vacuum in the nano-scale cavity. The negative pressure draws the second fluid into the nano-scale cavity. The conductor is deposited on the interior surface of the nano-scale cavity, preferably less than 10 nm thick.

Abstract: Methods for depositing one or more iridium materials on a surface of a substrate are provided. A method for forming the iridium material (e.g., metallic iridium and/or iridium silicide) on the substrate can include sequentially exposing the substrate to an iridium precursor and a reducing agent during an atomic layer deposition (ALD) process within a process chamber and depositing the iridium material on the substrate. In some examples, the reducing agent can be or include hydrogen gas (H2), a hydrogen plasma, atomic hydrogen, hydrazine or derivatives thereof, or any combination thereof and the deposited iridium material is metallic iridium. In other examples, the reducing agent contains one or more silicon precursors and the iridium material is an iridium silicide.

Abstract: A surface treatment method of an object, including the following steps immersion of the object in a solution containing an acid or a mixture of acids, and having a pH between 0 and 6, so as to impregnate the surface of the object, removal of the object from the acid solution, and heating of the object to a temperature between 50° C. and the melting temperature of the object, until the required gloss and roughness surface properties are obtained, the method is particularly but not exclusively applicable to objects derived from additive manufacturing techniques.

Abstract: A wafer is positioned on a wafer support apparatus beneath an electrode such that a plasma generation region exists between the wafer and the electrode. Radiofrequency signals of a first signal frequency are supplied to the plasma generation region to generate a plasma within the plasma generation region. Formation of a plasma instability is detected within the plasma based on supply of the radiofrequency signals of the first signal frequency. After detecting formation of the plasma instability, radiofrequency signals of a second signal frequency are supplied to the plasma generation region in lieu of the radiofrequency signals of the first signal frequency to generate the plasma. The second signal frequency is greater than the first signal frequency and is set to cause a reduction in ion energy within the plasma and a corresponding reduction in secondary electron emission from the wafer caused by ion interaction with the wafer.

Abstract: A process for creating a contact on a Ge-containing contact region of a semiconductor structure, said process comprising the steps of: providing said semiconductor structure comprising: (i) a Ge-containing contact region, (ii) optionally, a SiO2 layer coating said Ge-containing contact region, (iii) a Si3N4 layer coating said SiO2 layer if present or said Ge-containing contact region; etching selectively the Si3N4 layer by means of an inductively coupled plasma, thereby exposing the underlying SiO2 layer if present or the Ge-containing contact region; etching selectively the SiO2 layer if present, thereby exposing the SiGe:B contact region; and creating said contact on said Ge-containing contact region.

Abstract: A method for integrated circuit fabrication can include removing silicon oxide by a pre-clean process. The pre-clean process can include depositing a halogen-containing material on the surface of a substrate in a first reaction chamber, and transferring the substrate having the halogen-containing material to a second reaction chamber. Silicon oxide material can be removed from a surface of the substrate by sublimating the halogen-containing material in the second reaction chamber. A target material, such as a conductive material, may subsequently be deposited on the substrate surface in the second reaction chamber.

Abstract: The method of manufacturing a semiconductor device in accordance with the present invention provides a metal-containing film capable of adjusting a work function. The including: (a) alternately supplying a first source containing a first metal element and a halogen element and a second source containing a second metal element different from the first metal element and at least one selected from the group consisting of a ligand of a methyl group, a ligand of an ethyl group and a ligand of a cyclopenta-based group onto a substrate in a process chamber to form a composite metal-containing film on the substrate; and (b) alternately supplying a third source containing a third metal element and a fourth source containing nitrogen onto the substrate in the process chamber to form a metal nitride film on the composite metal-containing film.

Abstract: A metal-containing film capable of adjusting a work function is formed. A first source containing a first metal element and a halogen element and a second source containing a second metal element different from the first metal element and an amino group are alternately supplied onto a substrate having a high-k dielectric film to form a composite metal nitride film on the high-k dielectric film.

Abstract: Methods are described herein for selectively etching titanium nitride relative to dielectric films, which may include, for example, alternative metals and metal oxides lacking in titanium and/or silicon-containing films (e.g. silicon oxide, silicon carbon nitride and low-K dielectric films). The methods include a remote plasma etch formed from a chlorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the titanium nitride. The plasma effluents react with exposed surfaces and selectively remove titanium nitride while very slowly removing the other exposed materials. The substrate processing region may also contain a plasma to facilitate breaking through any titanium oxide layer present on the titanium nitride. The plasma in the substrate processing region may be gently biased relative to the substrate to enhance removal rate of the titanium oxide layer.

Abstract: A combinatorial processing chamber is provided. The combinatorial processing chamber is configured to isolate a radial portion of a rotatable substrate support, which in turn is configured to support a substrate. The chamber includes a plurality of clusters process heads in one embodiment. An insert having a base plate disposed between the substrate support and the process heads defines a confinement region for a deposition process in one embodiment. The base plate has an opening to enable access of the deposition material to the substrate. Through rotation of the substrate and movement of the opening, multiple regions of the substrate are accessible for performing combinatorial processing on a single substrate.

Abstract: A semiconductor device includes a first interconnect, a porous dielectric layer formed over the first interconnect, a second interconnect buried in the porous dielectric layer and electrically connected to the first interconnect, and a carbon-containing metal film that is disposed between the porous dielectric layer and the second interconnect and isolates these layers.

Abstract: A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive bump of the signal redistribution layer is electrically coupled to a conductive contact of a package substrate. An external access point of the package substrate is electrically coupled to the conductive contact, such that signals of the flip chip semiconductor die are accessible for measurement at the external access point.

Abstract: A method of manufacturing a semiconductor device comprises forming a contact hole within an interlayer insulating film of a substrate and forming a contact plug while the substrate is heated. In forming the contact plug, the substrate is held on a stage within the chamber of a sputtering apparatus through a chuck, and an ESC voltage applied to the chuck is increased stepwise in a plurality of steps. First target power is applied to a target within the chamber to form a first Al film in the contact hole. Next, second target power higher than the first target power is applied to the target within the chamber to form a second Al film on the first Al film.

Abstract: The present invention relates to a method for forming a raised conductive image on a non-conductive or dielectric surface, the method comprising placing a metal coordination complex on a surface of the substrate, exposing the surface to electromagnetic radiation, reducing the exposed complex, removing unexposed complex leaving an elemental metal image, removing unexposed metal complex and then plating the resulting elemental metal image with a highly conductive material.

Abstract: A process for forming a carbon nanotube field effect transistor (CNTFET) device includes site-specific nanoparticle deposition on a CNTFET that has one or more carbon nanotubes, a source electrode, a drain electrode, and a sacrificial electrode on a substrate with an interposed dielectric layer. The process includes control of PMMA removal and electrodeposition in order to select nanoparticle size and deposition location down to singular nanoparticle deposition. The CNTFET device resulting in ultra-sensitivity for various bio-sensing applications, including detection of glucose at hypoglycemic levels.

Abstract: A process is provided for contacting a nanostructured surface. In that process, a substrate is provided having a nanostructured material on a surface, the substrate being conductive and the nanostructured material being coated with an insulating material. A portion of the nanostructured material is at least partially removed. A conductor is deposited on the substrate in such a way that it is in electrical contact with the substrate through the area where the nanostructured material has been at least partially removed.

Abstract: A new method of electrophoretic nanotube deposition is proposed wherein individual nanotubes are placed on metal electrodes which have their length significantly exceeding their width, while the nanotube length is chosen to be close to that of the metal electrode. Due to electrostatic attraction of individual nanotube to the elongated electrode, every nanotube approaching the electrode is deposited along the electrode, since such an orientation is energetically favorable. This method offers opportunity to produce oriented arrays of individual nanotubes, which opens up a new technique for fabrication and mass production of nanotube-based devices and circuits. Several such devices are considered. These are MESFET- and MOSFET-like transistors and CMOS-like voltage inverter.

Abstract: Methods are described herein for selectively etching titanium nitride relative to dielectric films, which may include, for example, alternative metals and metal oxides lacking in titanium and/or silicon-containing films (e.g. silicon oxide, silicon carbon nitride and low-K dielectric films). The methods include a remote plasma etch formed from a chlorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the titanium nitride. The plasma effluents react with exposed surfaces and selectively remove titanium nitride while very slowly removing the other exposed materials. The substrate processing region may also contain a plasma to facilitate breaking through any titanium oxide layer present on the titanium nitride. The plasma in the substrate processing region may be gently biased relative to the substrate to enhance removal rate of the titanium oxide layer.

Abstract: A method for forming a semiconductor interconnect structure includes forming a dielectric layer on a substrate and patterning the dielectric layer to form an opening therein. A metal layer fills the opening and covers the dielectric layer. The metal layer is planarized so that it is co-planar with a top of the dielectric layer. A treating process is performed on the metal layer to convert a top surface thereof into a metal oxide layer. A copper-containing layer is then formed over the metal oxide layer and the dielectric layer. The copper-containing layer is etched to form interconnect features, wherein the etching stops at the metal oxide layer and does not etch into the underlying metal layer. A radiation exposure process is thereafter performed on the metal oxide layer to convert it into a non-oxidized metal layer.

Abstract: High aspect ratio trenches may be filled with metal that grows more from the bottom than the top of the trench. As a result, the tendency to form seams or to close off the trench at the top during filling may be reduced in some embodiments. Material that encourages the growth of metal may be formed in the trench at the bottom, while leaving the region of the trench near the top free of such material to encourage growth upwardly from the bottom.

Abstract: A method for modifying the chemistry or microstructure of silicon-based technology via an annealing process is provided. The method includes depositing a reactive material layer within a selected proximity to an interconnect, igniting the reactive material layer, and annealing the interconnect via heat transferred from the ignited reactive material layer. The method can also be implemented in connection with a silicide/silicon interface as well as a zone of silicon-based technology.

Abstract: A method of fabricating a rare earth silicide gate electrode on III-N material grown on a silicon substrate includes growing a single crystal stress compensating template on a silicon substrate. The template is substantially crystal lattice matched to the surface of the silicon substrate. A single crystal GaN structure is grown on the surface of the template and substantially crystal lattice matched to the template. An active layer of single crystal III-N material is grown on the GaN structure and substantially crystal lattice matched to the GaN structure. A single crystal monoclinic rare earth oxide dielectric layer is grown on the active layer of III-N material and a single crystal rare earth silicide gate electrode is grown on the dielectric layer, the silicide. Relative portions of the gadolinium metal and the silicon are adjusted during deposition so they react to form rare earth silicide during deposition.

Abstract: A universal modular connector includes a base and a transforming module. The base has a first opening thereon, and the base further has an optical component therein. The transforming module has a circuit board, a plurality of connection terminals, a first signal transforming integrated circuit (IC), and at least one fiber optic connector therein. The transforming module receives external electronic signal through the connection terminals, and transforms the received electronic signal into optical signal via the first signal transforming IC. The transforming module is connected with the base through the first opening, and the optical component of the base receives the transformed optical signal sent by the fiber optic connector of the transforming module. Therefore, the universal modular connector transmits the optical signal externally to an electronic device via the optical component.

Abstract: A new method of electrophoretic nanotube deposition is proposed wherein individual nanotubes are placed on metal electrodes which have their length significantly exceeding their width, while the nanotube length is chosen to be close to that of the metal electrode. Due to electrostatic attraction of individual nanotube to the elongated electrode, every nanotube approaching the electrode is deposited along the electrode, since such an orientation is energetically favorable. This method offers opportunity to produce oriented arrays of individual nanotubes, which opens up a new technique for fabrication and mass production of nanotube-based devices and circuits. Several such devices are considered. These are MESFET- and MOSFET-like transistors and CMOS-like voltage inverter.

Abstract: The present invention relates to a method for producing a modified surface of a substrate that stimulates the growth of epitaxial layers of group-III nitride semiconductors with substantially improved structural perfection and surface flatness. The modification is conducted outside or inside a growth reactor by exposing the substrate to a gas-product of the reaction between hydrogen chloride (HCl) and aluminum metal (Al). As a single-step or an essential part of the multi-step pretreatment procedure, the modification gains in coherent coordination between the substrate and group-III nitride epitaxial structure to be deposited. Along with epilayer, total epitaxial structure may include buffer inter-layer to accomplish precise substrate-epilayer coordination.

Abstract: The present invention relates to the field of selective metallization, and in particular to preparing a polymer article for selective metallization by submerging the article in a first liquid, and while submerged irradiate the article by a laser beam the area of the article on which the metal is to be deposited. An activation step, prior to the selective metallization, comprises submerging the article in an activation liquid for depositing seed particles in the selected area. The irradiation of the selected area is proportionate so as to cause a temporary melting of the polymer in the surface of the selected area of the polymer article. The invention is advantageous in that the preparation may be performed with a relatively high scan rate across the polymer article, and in that a quite limited use of toxic chemicals.

Abstract: In one disclosed embodiment, the present method for depositing a conductive capping layer on metal lines comprises forming metal lines on a dielectric layer, applying a voltage to the metal lines, and depositing the conductive capping layer on the metal lines. The applied voltage increases the selectivity of the deposition process used, thereby preventing the conductive capping layer from causing a short between the metal lines. The conductive capping layer may be deposited through electroplating, electrolessly, by atomic layer deposition (ALD), or by chemical vapor deposition (CVD), for example. In one embodiment, the present method is utilized to fabricate a semiconductor wafer. In one embodiment, the metal lines comprise copper lines, while the conductive capping layer may comprise tantalum or cobalt. The present method enables deposition of a capping layer having high electromigration resistance.

Abstract: Embodiments of the present invention generally provide methods and apparatus for material removal using lasers in the fabrication of solar cells. In one embodiment, an apparatus is provided that removes portions of a dielectric layer deposited on a solar cell substrate according to a desired pattern. In certain embodiments, methods for removing a portion of a material via a laser without damaging the underlying substrate are provided. In one embodiment, the intensity profile of the beam is adjusted so that the difference between the maximum and minimum intensity within a spot formed on a substrate surface is reduced to an optimum range. In one example, the substrate is positioned such that the peak intensity at the center versus the periphery of the substrate is lowered. In one embodiment, the pulse energy is improved to provide thermal stress and physical lift-off of a desired portion of a dielectric layer.

Abstract: Electronic devices are provided with housing components that have improved aesthetics. One or more holes may be formed through an extruded portion of the housing.

Abstract: According to an embodiment of the present disclosure, a method of pre-migrating metal ions is disclosed. A metal in a semiconductor configuration is exposed to water and oxygen to yield metal ions. The metal couples a conductor to another material. The metal and the conductor are exposed to an electrical field in such a manner that one or both of the metal and the conductor becomes an anode to a corresponding cathode. The metal ions are then allowed to migrate from the anode to the cathode to form a migrated metal. Finally, a migration inhibitor is applied on top of the migrated metal to prevent further migration.

Abstract: A double seal ring for an integrated circuit includes a first seal ring with a first opening. The first seal ring surrounds the integrated circuit. A second seal ring with a second opening surrounds the first seal ring. Two connectors connect the first opening of the first seal ring and the second opening of the second seal ring. The first seal ring, the second seal ring, and the two connectors form a closed loop.

Abstract: A composite wafer semiconductor device includes a first wafer and a second wafer. The first wafer has a first side and a second side, and the second side is substantially opposite the first side. The composite wafer semiconductor device also includes an isolation set is formed on the first side of the first wafer and a free space is etched in the isolation set. The second wafer is bonded to the isolation set. A floating structure, such as an inertia sensing device, is formed in the second wafer over the free space. In an embodiment, a surface mount pad is formed on the second side of the first wafer. Then, the floating structure is electrically coupled to the surface mount pad using a through silicon via (TSV) conductor.

Abstract: Disclosed herein are a variety of microfluidic devices and solid, typically electrically conductive devices that can be formed using such devices as molds. In certain embodiments, the devices that are formed comprise conductive pathways formed by solidifying a liquid metal present in one or more microfluidic channels (such devices hereinafter referred to as “microsolidic” devices). In certain such devices, in which electrical connections can be formed and/or reformed between regions in a microfluidic structure; in some cases, the devices/circuits formed may be flexible and/or involve flexible electrical components. In certain embodiments, the solid metal wires/conductive pathways formed in microfluidic channel(s) may remain contained within the microfluidic structure. In certain such embodiments, the conductive pathways formed may be located in proximity to other microfluidic channel(s) of the structure that carry flowing fluid, such that the conductive pathway can create energy (e.g.

Abstract: The present invention provides a semiconductor light-emitting element comprising an electrode part excellent in ohmic contact and capable of emitting light from the whole surface. An electrode layer placed on the light-extraction side comprises a metal part and plural openings. The metal part is so continuous that any pair of point-positions in the part is continuously connected without breaks, and the metal part in 95% or more of the whole area continues linearly without breaks by the openings in a straight distance of not more than ? of the wavelength of light emitted from an active layer. The average opening diameter is of 10 nm to ? of the wavelength of emitted light. The electrode layer has a thickness of 10 nm to 200 nm, and is in good ohmic contact with a semiconductor layer.

Abstract: A process is provided for contacting a nanostructured surface. In that process, a substrate is provided having a nanostructured material on a surface, the substrate being conductive and the nanostructured material being coated with an insulating material. A portion of the nanostructured material is at least partially removed. A conductor is deposited on the substrate in such a way that it is in electrical contact with the substrate through the area where the nanostructured material has been at least partially removed.

Abstract: A method for manufacturing a semiconductor device for detecting a physical amount distribution, the semiconductor device comprising unit components arrayed in a predetermined order, the unit components each including a unit signal generation portion for detecting an electromagnetic wave and outputting the corresponding unit signal. A diffraction grating is provided on the incident light side of a spectral image sensor, the diffraction grating including scatterers, slits, and scatterers disposed in that order. An electromagnetic wave is scattered by the scatterers to produce diffracted waves, and by using the fact that interference patterns between the diffracted waves change with wavelengths, signals are detected for respective wavelengths by photoelectric conversion elements in each photodiode group.

Abstract: The present invention provides an antenna with low resistance and a semiconductor device having an antenna whose communication distance is improved. A fluid containing conductive particles is applied over an object. After curing the fluid containing the conductive particles, the fluid is irradiated with a laser to form an antenna. As a method for applying the fluid containing the conductive particles, screen printing, spin coating, dipping, or a droplet discharging method is used. Further, a solid laser having a wavelength of 1 nm or more and 380 nm or less is used as the laser.

Abstract: The present inventors have found that a wafer process of VLSI (Very Large Scale Integration) has the following problem, that is, generation of foreign matters due to moisture from a wafer as a result of degassing when a barrier metal film or a first-level metal interconnect layer is formed by sputtering as a preliminary step for the formation of a tungsten plug in a pre-metal step. To overcome the problem, the present invention provides a manufacturing method of a semiconductor integrated circuit device including, in a plasma process, in-situ monitoring of moisture in a processing chamber by receiving an electromagnetic wave generated from plasma.

Abstract: An integrated component having a substrate, the substrate having a cavity which surrounds a mechanical structure. The cavity is filled by a fluid of a specific composition under a specific pressure, and the mechanical properties of the mechanical structure are influenced by the fluid.

Abstract: A substrate micro-processing method and a semiconductor device manufacturing method in which a stained part does not remain in a finished product even if a residual ion-injected part stays in the finished product. The substrate micro-processing method is one that carries out processing of a substrate by dividing the substrate depthwise, and comprises a proton injection step S11 in which protons are injected from one principal surface side of the substrate and an irradiation step S12 in which the substrate is irradiated with light having the wavelength nearly equal to the absorption wavelength of the defect level formed within the substrate due to the proton injection in order to divide the substrate.

Abstract: Material is deposited in a desired pattern by spontaneous deposition of precursor gas at regions of a surface that are prepared using a beam to provide conditions to support the initiation of the spontaneous reaction. One the reaction is initiated, it continues in the absence of the beam at the regions of the surface at which the reaction was initiated.

Abstract: A chemically amplified positive resist composition comprising (A) a substantially alkali insoluble polymer having an acidic functional group protected with an acid labile group, (B) an acid generator, and (C) a perfluoroalkyl ethylene oxide adduct or a nonionic fluorinated organosiloxane compound is coated, exposed to UV radiation having a wavelength of at least 150 nm, and developed. The composition has advantages of uniformity and minimized edge crown upon coating, and no scum formation after development.

Abstract: In a chemically amplified positive resist composition comprising a base resin and an acid generator in a solvent, the base resin contains both an alkali-insoluble or substantially alkali-insoluble polymer having an acid labile group-protected acidic functional group having a Mw of 1,000-500,000 and an alkyl vinyl ether polymer having a Mw of 10,000-500,000. The composition forms on a substrate a resist film of 5-100 ?m thick which can be briefly developed to form a pattern at a high sensitivity and a high degree of removal or dissolution to bottom.

Abstract: A microelectronic method for the fabrication of a transistor gate using a precursor material that is suitable for being broken down into at least one metallic material after having been exposed to an electron beam. The invention applies in particular to the fabrication of multi-channel transistors, of the FinFET, suspended-channel, ITS or GAA type.

Abstract: As a semiconductor device, specifically, a pixel portion included in a semiconductor device is made to have higher precision and higher aperture ratio, it is required to form a smaller wiring in width. In the case of forming a wiring by using an ink-jet method, a dot spreads on a wiring formation surface, and it is difficult to narrow width of a wiring. In the present invention, a photocatalytic substance typified by TiO2 is formed on a wiring formation surface, and a wiring is formed by utilizing photocatalytic activity of the photocatalytic substance. According to the present invention, a narrower wiring, that is, a smaller wiring in width than a diameter of a dot formed by an ink-jet method can be formed.

Abstract: A semiconductor wafer in which a carbon thin film is formed on a surface of a silicon substrate implanted with impurities is irradiated with flash light emitted from flash lamps. Absorbing the flash light causes the temperature of the carbon thin film to increase. The surface temperature of the silicon substrate implanted with impurities is therefore increased to be higher than that in a case where no thin film is formed, and the sheet resistance value can be thereby decreased. When the semiconductor wafer with the carbon thin film formed thereon is irradiated with flash light in high concentration oxygen atmosphere, since the carbon of the thin film is oxidized to be vaporized, removal of the thin film is performed concurrently with flash heating.

Abstract: Provided herein are improved methods of laser scribing photovoltaic structures to form monolithically integrated photovoltaic modules. The methods involve forming P1, P2 or P3 scribes by an ablative scribing mechanism having low melting, and in certain embodiments, substantially no melting. In certain embodiments, the methods involve generating an ablation shockwave at an interface of the film to be removed and the underlying layer. The film is then removed by mechanical shock. According to various embodiments, the ablation shockwave is generated by using a laser beam having a wavelength providing an optical penetration depth on the order of the film thickness and a minimum threshold intensity. In one embodiment, material including an absorber layer is scribed using an infrared laser source and a picosecond pulse width.

Abstract: A structure, tool and method for forming in-situ metallic/dielectric caps for interconnects. The method includes forming wire embedded in a dielectric layer on a semiconductor substrate, the wire comprising a copper core and an electrically conductive liner on sidewalls and a bottom of the copper core, a top surface of the wire coplanar with a top surface of the dielectric layer; forming a metal cap on an entire top surface of the copper core; without exposing the substrate to oxygen, forming a dielectric cap over the metal cap, any exposed portions of the liner, and the dielectric layer; and wherein the dielectric cap is an oxygen diffusion barrier and contains no oxygen atoms.