Abstract: A wiring pattern formation method in which a wiring pattern is formed by arranging, in a region which is demarcated by a partition wall, liquid material which includes an electrically conductive material, including: arranging a resin material around the periphery of a region upon which the wiring pattern is to be formed; imparting liquid affinity to a demarcated region which has been demarcated by the resin material; narrowing down the demarcated region by flowing out the resin material towards and into the demarcated region; and forming the partition wall by curing the resin material.

Abstract: A processing method for selectively reducing or removing the region to be exposed with energy ray in a film formed on a substrate, comprising relatively scanning a first exposure light whose shape on the substrate is smaller than the whole first region to be exposed against the whole first region to be exposed to selectively remove or reduce the first region to be exposed, and exposing a whole second region to be exposed inside the whole first region to be exposed with a second exposure light to selectively expose the whole second region to be exposed.

Abstract: A method and apparatus including an interconnect structure having a surface, a plurality of nanotubes disposed adjacent to the surface, and a metallic layer disposed adjacent to the surface and substantially including the nanotubes. An assembly may include a first embodiment of an apparatus as described, and may further include a second such embodiment at least one of physically and electrically coupled to the first embodiment.

Abstract: A method of processing a substrate comprising depositing a layer comprising amorphous carbon on the substrate and then exposing the substrate to electromagnetic radiation have one or more wavelengths between about 600 nm and about 1000 nm under conditions sufficient to heat the layer to a temperature of at least about 300° C. is provided. Optionally, the layer further comprises a dopant selected from the group consisting of nitrogen, boron, phosphorus, fluorine, and combinations thereof. In one aspect, the layer comprising amorphous carbon is an anti-reflective coating and an absorber layer that absorbs the electromagnetic radiation and anneals a top surface layer of the substrate. In one aspect, the substrate is exposed to the electromagnetic radiation in a laser annealing process.

Abstract: A coplanar mounting member for a MEM sensor includes a first surface coplanar with a connection pad on the surface of a MEM sensor board containing the MEM sensor control circuit; a second surface inclined to the surface of the board for mounting a MEM sensor and an electrical conductor array for interconnecting the MEM sensor with the connection pad on the board.

Abstract: The present invention relates to a deposition method of a low dielectric constant insulating film, which comprises the steps of generating a first deposition gas containing at least one silicon source selecting from the group consisting of silicon containing organic compound having siloxane bond and silicon containing organic compound having CH3 group, and an oxidizing agent consisting of oxygen containing organic compound having alkoxyl group (OR: O is oxygen and R is CH3 or C2H5), and applying electric power to the first deposition gas to generate plasma and then causing reaction to form a low dielectric constant insulating film on a substrate.

Abstract: A technique for more efficiently forming conductive elements, such as conductive layers and electrodes, using chemical vapor deposition. A conductive precursor gas, such as a platinum precursor gas, having organic compounds to improve step coverage is introduced into a chemical vapor deposition chamber. A reactant is also introduced into the chamber that reacts with residue organic compounds on the conductive element so as to remove the organic compounds from the nucleating sites to thereby permit more efficient subsequent chemical vapor deposition of conductive elements.

Abstract: A method of forming a thin film pattern by placing a functional liquid on a substrate, includes a bank formation step of forming banks in accordance with the thin film pattern on the substrate, a residue processing step of removing residue between the banks, and a material placement step of placing the functional liquid between the banks removed the residue.

Abstract: Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing process to form a copper wiring within a damascene pattern. At this time, the chemical mechanical polishing process is overly performed so that the top surface of the copper wiring is concaved and is lower than the surface of the interlayer insulating film of the low dielectric constant neighboring it. Furthermore, an annealing process is performed so that the top surface of the copper wiring is changed from the concaved shape to a convex shape while stabilizing the copper wiring. A copper anti-diffusion insulating film is then formed on the entire structure including the top surface of the copper wiring having the convex shape.

Abstract: A first precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. A second precursor gas different in composition from the first precursor gas is flowed to the first monolayer within the chamber under surface microwave plasma conditions within the chamber effective to react with the first monolayer and form a second monolayer on the substrate which is different in composition from the first monolayer. The second monolayer includes components of the first monolayer and the second precursor. In one implementation, the first and second precursor flowings are successively repeated effective to form a mass of material on the substrate of the second monolayer composition. Additional and other implementations are contemplated.

Abstract: An electrodeposition film forming method includes forming an electrodeposited film of an electrodeposition coating material having good thermal fluidity by a first electrodeposition; forming an electrodeposition film in a very small through-hole provided on a conductive or semiconductive substrate; removing electrodeposited film at an opening portion of the through-hole under a wet-coated condition; and hardening the electrodeposition film to obtain a flat portion other than the opening portion. Then, a second electrodeposition film of an electrodeposition coating material having good thermal fluidity is formed around the opening portion and is hardened to coat uncoated portions of the opening portion remaining after the first deposition. Accordingly, a flat inner surface of the through-hole is obtained, any exposed portions of an underlayer at the opening of the through-hole are covered and the opening of the through-hole is maintained.

Abstract: A physical vapor deposition process for maintaining the wafer below a critical temperature. The rate at which material particles are sputtered from the target and thus deposited on the wafer is controllable in response to power supplied to the target. Maintaining a desired deposition rate maintains the wafer temperature below the critical temperature.

Abstract: The present invention provides a method for the patterned metallization of a surface of a substrate, comprising the steps of preheating the substrate to a temperature which is below a deposition temperature of a predetermined metal dissolved in a fluid provided above the surface, and performing patterned deposition of the predetermined metal in predetermined regions on the surface of the substrate by locally increasing the temperature to above the deposition temperature.

Abstract: In copper plating using a damascene method, in order to prevent cost rise, dishing, erosion and the like due to the protrusion of plating on the dense wiring area to increase the time for CMP polishing, the copper plating is performed so that the current step of the copper plating has only one step for flowing current in the direction opposite to the direction of growing the plating as shown in FIG. 1. In this time, this opposite direction current step is performed under the condition of a current-time product within a range between 1.0 and 120 mA×sec/cm2.

Abstract: A method for manipulating a nanoscale object deposited on a substrate. The surface of the substrate is passive. A target position is formed on the passive surface by the action of the tip of a scanning probe microscope. The nanoscale object is picked from its initial position by the tip of the scanning probe microscope, then placed and released at the target position.

Abstract: Method for making three-dimensional structures. A template is provided having at least two conductive regions separated by a non-conductive region. The template is disposed in an electrolyte in an electrodeposition cell and a voltage is established between one of the conductive regions and an electrode in the cell. Material is deposited on the one of the conductive regions connected to the voltage and subsequently bridges to the other conductive region with material deposition continuing on both of the at least two regions. The non conductive region may be a gap and the gap dimension is selected to regulate height differences between the at least two conductive regions.

Abstract: In a first aspect, a method is provided that includes (1) forming a first barrier layer over the sidewalls and bottom of a via using atomic layer deposition within an atomic layer deposition (ALD) chamber; (2) removing at least a portion of the first barrier layer from the bottom of the via by sputter etching; and (3) depositing a second barrier layer on the sidewalls and bottom of the via within the ALD chamber. Numerous other embodiments are provided, as are systems, methods and computer program products in accordance with these and other aspects.

Abstract: A printed wiring board design aiding system comprises a first unit which acquires design layout information regarding a printed wiring board targeted for design, a second unit which acquires setting parameter information for the printed wiring board, which is targeted for design, and a third unit which estimates a value of the thickness of each of insulation layers of the printed wiring board in a post-manufacture state in accordance with the information acquired by the first unit and the information acquired by the second unit, and for outputting an estimated value.

Abstract: After a barrier film is formed on a pad electrode, Ni particles having a diameter of 2 ?m or less are selectively deposited on the barrier film, thereby forming a Ni fine particle film. Then, a bump electrode made of a solder ball is provided on the pad electrode through the Ni fine particle film. Thereafter, the bump electrode is melted by a heat treatment to join the Ni fine particle film to the bump electrode. Thus, a bump electrode structure is finished.

Abstract: The present invention relates to a resist resin having an acid-decomposable group, which gives rise to decomposition of the acid-decomposable group to show an increased solubility to an aqueous alkali solution by the action of an acid, wherein the resist resin has, in the main chain, an alicyclic lactone structure represented by the following general formula (1). According to the present invention, a positive-type chemically amplified resist can be obtained which has high transparency to a far-ultraviolet light having a wavelength of about 220 nm or less, excellent etching resistance, and excellent adhesion to substrate; and a fine pattern required in production of semiconductor device can be formed. (wherein Z is an alicyclic hydrocarbon group having a lactone structure).

Abstract: In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from being adsorbed onto the surface of the first conductive layer. In one embodiment, a second conductive layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates an oxide formed between the two layers as a result of subsequent thermal treatments. In another embodiment, a dielectric layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates the ability of the first conductive layer to incorporate oxygen from the dielectric.

Abstract: The electromigration resistance of nitride capped Cu lines is significantly improved by controlling the nitride deposition conditions to reduce the compressive stress of the deposited nitride layer, thereby reducing diffusion along the Cu-nitride interface. Embodiments include depositing a silicon nitride capping layer on inlaid Cu using dual frequency powers, holding the high frequency power constant and controlling the compressive stress of the deposited silicon nitride capping layer by varying the low frequency power to the susceptor, thereby enabling reduction of the compressive stress below about 2×107 Pascals. Embodiments also include sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a soft plasma containing NH3 diluted with N2, and then depositing the silicon nitride capping layer by plasma enhanced chemical vapor deposition, while varying the low frequency power between about 100 to about 300 watts.

Abstract: Methods are provided for fabricating semiconductor structures and semiconductor device structures utilizing epitaxial Hf3Si2 layers. A process in accordance with one embodiment of the invention begins by disposing a silicon substrate in a processing chamber. The pressure within the processing chamber and a temperature of the silicon substrate in the range of approximately 250° C. to approximately 700° C. is established. A layer of Hf3Si2 then is grown overlying the silicon substrate at a rate in the range of about one (1) to about five (5) monolayers per minute.

Abstract: Disclosed is a method for forming a metal contact of a semiconductor device. The method includes the steps of preparing a substrate formed with a tungsten bit line, forming an insulating interlayer on an entire surface of the substrate, forming a contact hole expositing the tungsten bit line, depositing a first tungsten layer on the insulating interlayer through an IMP process, depositing a second tungsten layer on the first tungsten layer through a CMP process, and performing an etch back process with respect to the second tungsten layer. After depositing the first tungsten layer through the IMP process, the second tungsten layer is deposited trough the CVD process without forming the barrier metal. Thus, contact filling failure is prevented when CVD tungsten is deposited, thereby preventing metal contact failure while improving reliability and a yield rate of the semiconductor devices.

Abstract: The adhesion properties of a metal interconnect structure are enhanced by selectively depositing a barrier layer component having good adhesion to an underlying metal on the bottom surface of a via. Then, a further barrier layer having superior adhesion characteristics for the dielectric is formed on the dielectric sidewalls of the via, so that excellent adhesion to the dielectric and the underlying metal is achieved. The selectivity of the deposition may be accomplished by exploiting the capabilities of modem IPVD tools.

Abstract: The present invention provides a method for creating microscopic high resistivity structures on a target by directing a focused ion beam toward an impact point on the target and directing a precursor gas toward the impact point, the ion beam causing the precursor gas to decompose and thereby deposit a structure exhibiting high resistivity onto the target. The precursor gas preferably contains a first compound that would form a conductive layer and a second compound that would form an insulating layer if each of the first and second compounds were applied alone in the presence of the ion beam.

Abstract: Conductive material is deposited by ionized physical vapor deposition on an insulator, possibly to contact a conductive layer exposed by an opening in the insulator. At the beginning of the deposition, the wafer bias is low (possibly zero), to prevent the insulator re-sputtering by the ionized conductive material as this material is being deposited. The contact resistance is improved (reduced) as a result.

Abstract: A method for forming a metal thin film is suitable for suppressing the deterioration of a throughput according to enlarging a purge time to prevent the metal precursor from mixing with a reaction gas in a reactor during the deposition of an atomic layer. The method includes the steps of flowing a reaction gas into a reactor loaded therein a substrate, flowing a metal precursor in a pulse form into the reactor, activating the reaction gas by exiting a plasma in a pulse form to change with a pulse of the metal precursor in the reactor, alternately and depositing a metal thin film in a unit of an atomic layer by reacting the activated reaction gas with the metal precursor.

Abstract: A method for capping over a copper layer. A copper layer is deposited overlying a substrate. The copper surface is treated with hydrogen-containing plasma to remove copper oxides formed thereon, thereby suppressing copper hillock formation. The treated copper surface is treated again with nitrogen-containing plasma to improve adhesion of the copper surface. A capping layer is formed on the copper layer.

Abstract: The present invention relates to a method of fabricating polysilicon film by Nickel and Copper induced lateral crystallization for the TFT-LCD, comprising the step of: a) a thin (˜4 nm) Copper and Nickel being evaporated onto the substrate; b) a amorphous-silicon film (˜50 nm) being evaporated onto thereof obtained according to a); c) applying annealing at less than 600° C. to thereof obtained according to b) for fast fabricating poly-silicon film. It is approximately 10 times faster than that of Ni induced polysilicon. The present invention is to provide a low-temperature (<600° C.) fast growth rate process to convert the hydrogenated amorphous silicon (a-Si:H) films to polysilicon film for substantially time-saving process and industrial applicability.

Abstract: In a first aspect, a method is provided that includes (1) forming a first barrier layer over the sidewalls and bottom of a via using atomic layer deposition within an atomic layer deposition (ALD) chamber; (2) removing at least a portion of the first barrier layer from the bottom of the via by sputter etching; and (3) depositing a second barrier layer on the sidewalls and bottom of the via within the ALD chamber. Numerous other embodiments are provided, as are systems, methods and computer program products in accordance with these and other aspects.

Abstract: The invention includes methods of forming regions of differing composition over a substrate. A first material having a pattern of at least one substantially amorphous region and at least one substantially crystalline region is provided over the substrate. The at least one substantially amorphous region of the first material replaced with a second material, while the at least one substantially crystaline region is not replaced. The invention also includes a circuit construction comprising an electrically conductive material extending within openings in a substantially crystalline electrically insulative material, and in which the electrically conductive material corresponds to quantum dots.

Abstract: Herein disclosed are a variety of techniques relating to the wiring and logic corrections on a chip by making use of the focused ion beam (which is shortly referred to as “FIB”) or the laser selection metal CVD. The time periods for the wiring corrections and for debugging and developing an electronic system are shortened by making use of the processing characteristics of the FIB. Illustratively, a hole is bored in an insulating film above a portion of a wiring which is to be connected to another wiring by means of a focused ion beam. The inside of the hole and a predetermined region on the insulating film are irradiated with either a laser beam or an ion beam in a metal compound gas to deposit metal in the hole and on said region and a connecting wiring is formed by means of optically pumped CVD.

Abstract: A process for electroplating metallic features of different density on a surface of a substrate comprises providing an electroplating bath having an anode, immersing the substrate into the electroplating bath, spaced from the anode, the substrate comprising a cathode. Positioned in the electroplating bath between the substrate and the anode, and adjacent to and separated from the substrate surface is a second cathode that includes a wire mesh screening portion having openings of different sizes conforming to the metallic features to be electroplated. The second cathode screening portion has openings of larger size adjacent areas of higher density of features to be electroplated and openings of smaller size adjacent areas of lower density of features to be electroplated.

Abstract: A method of manufacturing a semiconductor device including the steps of: (a) preparing a semiconductor substrate formed with an insulating layer having a wiring recess; and (b) forming a conductive layer by chemical vapor deposition on a surface of the semiconductor substrate including an inner surface of the wiring recess, while lamp light is applied to the semiconductor substrate, the conductive layer being substantially made of copper. With this method, Cu wiring having a high adhesion force is formed by chemical vapor deposition.

Abstract: An electroplating system is described which provides for the formation of a conductive layer on a workpiece. The current used to electroplate the workpiece is controlled by a controller. The rotation of the workpiece within a solution containing conductive material is controlled by a rotation controller. The current level and/or rotation of the workpiece is controlled in such a way that the non-uniform growth of large grains within the conductive film is minimized.

Abstract: A method is provided for processing a substrate including treating a surface of a dielectric layer comprising silicon and carbon by exposing the dielectric layer comprising silicon and carbon to a plasma of an inert gas, and depositing a photoresist on the dielectric layer comprising silicon and carbon. The dielectric layer may comprise a first dielectric layer comprising silicon, carbon, and nitrogen, and a second layer of nitrogen-free silicon and carbon containing material in situ on the first dielectric layer, and a third dielectric layer comprising silicon, oxygen, and carbon on the second dielectric layer.

Abstract: A method for determining relevant deposition parameters in i-PVD processes, includes, first calculating the reaction rates for desired reagents of the gas plasma and of a metal and/or metal compound to be deposited, then simulating the edge coverage of a predetermined structure with the deposited metal based upon the calculated reaction rates with systematic variation of the relevant deposition parameters, and compiling variant tables therefrom. By comparing an experimental verification of the simulated edge coverage by imaging the edge coverage of the metal layer deposited over the determined structure, e.g., using a TEM cross-section, with the simulated deposition parameters for the edge coverages that have been recorded in the variant table, it is possible to read the deposition parameters that are of relevance to the process from the variant table.

Abstract: The present invention relates to a resist resin having an acid-decomposable group, which gives rise to decomposition of the acid-decomposable group to show an increased solubility to an aqueous alkali solution by the action of an acid, wherein the resist resin has, in the main chain, an alicyclic lactone structure represented by the following general formula (1). According to the present invention, a positive-type chemically amplified resist can be obtained which has high transparency to a far-ultraviolet light having a wavelength of about 220 nm or less, excellent etching resistance, and excellent adhesion to substrate; and a fine pattern required in production of semiconductor device can be formed.

Abstract: The present invention is a surface-mounted device of light-emitting diodes (SMD LED) whose component typically has a plane on the surface. Through the calculation of Snell's Law, most of light fails to be emitted directly from the component because of the difference in the refractive index of the epoxy resin and the atmosphere (the refractive index of the light in the atmosphere is 1, the refractive index of the epoxy resin is around 1.5). It takes several times of refraction and a waste of brightness to allow the light that fails to be emitted directly a chance to be emitted, while leaving some light that might never be emitted. Therefore, the brightness reduces. The surface-mounted devices of light-emitting diodes with small lens for the present invention attach several small lens or diffraction lens on the plane surface of the SMD LED. The lens that enlarges the critical angle increases the direct light-emitting opportunity from the light-emitting chip, which in turn increases the brightness of LED.

Abstract: An antireflection coating has two-layer structure including lower and upper silicon nitride films (p-SiN films) formed by plasma CVD. For the lower p-SiN film, the real part of its complex index of refraction is set in the range not less than 1.9 nor more than 2.5, the imaginary part is set in the range of not less than 0.9 nor more than 1.7, and the film thickness is set in the range of not less than 20 nm nor more than 60 nm. For the upper p-SiN film, the real part of its complex index of refraction is set in the range not less than 1.7 nor more than 2.4, the imaginary part is set in the range of not less than 0.15 nor more than 0.75, and the film thickness is set in the range of not less than 10 nm nor more than 40 nm.

Abstract: An apparatus and method for scribing a semiconductor wafer coated with a substantially opaque material using vision recognition is disclosed. The apparatus includes a stage configured to hold a wafer, an imaging unit configured to generate an image of the wafer, and a computer configured to identify the coordinates of the scribe lines on the wafer from the image. During operation, the wafer is imaged using the imaging unit. The computer then identifies the coordinates of the scribe lines on the wafer from the image. Thereafter the coordinates are provided to a dicing machine which performs the dicing of the wafer. Accuracy is therefore improved since the dicing machine relies on the coordinates of the scribe lines as opposed to attempting to recognize the scribe lines through the opaque material. According to various embodiments of the invention, the imaging unit may use infrared, X-ray or ultrasound waves to generate the image of the wafer.

Abstract: A method of depositing a thin film on a substrate in a semiconductor device using Atomic Layer Deposition (ALD) process parameters exposes the substrate to at least one adherent material in a quantity sufficient for the material to adsorb onto the substrate and thereby form an initiation layer. The initiation layer presents at least one first reactive moiety which is then chemically reacted with at least one first reaction material using atomic layer deposition conditions to form a second reactive moiety. The second reactive moiety is then chemically reacted with at least one second reaction material under process conditions sufficient to form a reaction layer over the initiation layer. The process may be repeated to form successive reaction layers over the initiation layer. The adherent material constituting the initiation layer is preferably one which is not substantially degraded by the atomic layer deposition parameters.

Abstract: Conductive material is deposited by ionized physical vapor deposition on an insulator, possibly to contact a conductive layer exposed by an opening in the insulator. At the beginning of the deposition, the wafer bias is low (possibly zero), to prevent the insulator re-sputtering by the ionized conductive material as this material is being deposited. The contact resistance is improved (reduced) as a result.

Abstract: Disclosed is a copper film selective formation method capable of reducing the material cost by selectively depositing copper in a necessary region of an undercoat film made of an arbitrary material such as a metal or an insulating material. This copper film selective formation method includes the steps of forming a thin film of a silane coupling agent or a surfactant on an undercoat film on a substrate, making a prospective copper film region of the thin film hydrophilic, and selectively forming a copper film in the hydrophilic prospective copper film region of the undercoat film by CVD of copper.

Abstract: Conductive material is deposited by ionized physical vapor deposition on an insulator, possibly to contact a conductive layer exposed by an opening in the insulator. At the beginning of the deposition, the wafer bias is low (possibly zero), to prevent the insulator re-sputtering by the ionized conductive material as this material is being deposited. The contact resistance is improved (reduced) as a result.

Abstract: In a fabrication method of a microstructure array, such as a mold for forming a microlens array, a first insulating mask layer is formed on a conductive portion of s substrate, an array of openings for the microstructure array and at least an opening for an alignment marker are formed in the first insulating mask layer during a common process to expose the conductive portion of the substrate at the openings, and first plated or electrodeposited layers are grown in the openings and on the first insulating mask layer using the conductive portion of the substrate as a cathode. The opening for the alignment marker is surrounded by the array of openings for the microstructure array, and a pattern of the opening for the alignment marker is determined such that a current density distribution at the time of electroplating or electrodeposition can be oppressed.

Abstract: Silicon carbide layers are often used as hardmask layers in semiconductor processing. The photoresist used to pattern the silicon carbide layers during the hardmask patterning process can become poisoned by the silicon carbide layer and remain attached to the silicon carbide surface. According to the method of the instant invention a trimethylsilane and oxygen treatment of the silicon carbide growth chamber prior to layer growth will reduce the photoresist poisoning.

Abstract: For fabricating an interconnect structure formed within an interconnect opening surrounded by dielectric material, a layer of diffusion barrier material is formed on at least one wall of the interconnect opening. An activation layer comprised of palladium is formed on the layer of diffusion barrier material when the interconnect opening is immersed in an activation bath comprised of tin ions and palladium ions. The tin ions have a tin ion concentration in the activation bath that is greater than a palladium ion concentration in the activation bath. A layer of seed material is deposited on the activation layer in an electroless deposition process, and the interconnect opening is filled with a conductive fill material grown from the layer of seed material. A layer of silicon rich material may be formed on the layer of diffusion barrier material before deposition of the activation layer such that the activation layer is formed on the layer of silicon rich material.

Abstract: The present invention relates to a method and apparatus for forming interconnects on a substrate such as a semiconductor wafer by filling a conductive material such as copper (Cu) in fine recesses formed in a surface of the substrate. A method for forming interconnects comprises providing a substrate and a target composed of a conductive material in confrontation with each other in a chamber, introducing a sputtering gas into the chamber while a high voltage is applied between the substrate and the target to cause the sputtering gas to collide with the target, and depositing particles of the conductive material emitted from the target on the surface of the substrate to form a thin film, while sputter-etching the thin film by reflection sputtering gas molecules reflected from the target and having high energy.