Abstract: The present invention generally provides a method and apparatus for forming a doped layer on a substrate to improve uniformity of subsequent deposition thereover. Preferably, the layer is deposited by a sputtering process, such as physical vapor deposition (PVD) or Ionized Metal Plasma (IMP) PVD, using a doped target of conductive material. Preferably, the conductive material, such as copper, is alloyed with a dopant, such as phosphorus, boron, indium, tin, beryllium, or combinations thereof, to improve deposition uniformity of the doped layer over the substrate surface and to reduce oxidation of the conductive material. It is believed that the addition of a dopant, such as phosphorus, stabilizes the conductive material surface, such as a copper surface, and lessens the surface diffusivity of the conductive material.

Abstract: The invention relates to a process for filling a multiplicity of recesses (3) formed in an exposed surface of a workpiece (1), wherein the mouths of the recesses (3) are closed by the deposition of a layer (10) and the layer is subjected to elevated temperature and pressure to force material from the layer down into the recesses. In the particular embodiments described, the elevated temperature is achieved by supplying very short thermal pulses, for example, from a light source such as a laser or a halogen light and preferably this thermal pulse is applied after the elevated pressure has been achieved.

Abstract: In accordance with the objectives of the invention a new method is provided to create aluminum pads that overlay an electrical contact point. A layer of passivation is deposited over the surface that contains one or more electrical contact points, the layer of passivation is patterned thereby creating openings in the layer of passivation that overlay and align with one or more of the contact points. Under the first embodiment of the invention, a layer of AlCu is deposited over the patterned layer of passivation thereby including the openings that have been created in the layer of passivation. The deposited layer of AlCu is patterned and etched thereby creating the required AlCu bond pad. In addition to creating the required AlCu bond pad, the etch of the layer of AlCu also creates a pattern of dummy AlCu pads that are not in contact with any underlying points of electrical contact but that are located on the surface of the layer of passivation.

Abstract: An article of manufacture and method of forming nanoparticle sized material components. A semiconductor oxide substrate includes nanoparticles of semiconductor oxide. A modifier is deposited onto the nanoparticles, and a source of metal ions are deposited in association with the semiconductor and the modifier, the modifier enabling electronic hole scavenging and chelation of the metal ions. The metal ions and modifier are illuminated to cause reduction of the metal ions to metal onto the semiconductor nanoparticles.

Abstract: Silicon oxynitride layers are deposited by plasma enhanced chemical vapor deposition with significantly reduced defects, such as nodules, employing a ramp down step at the end of the deposition cycle. Embodiments include depositing a SION ARC at a first power, discontinuing the flow of SiH4 and ramping down to a second power while continuing the flow of N2O and N2, and ramping down to a third power while continuing the flow of N20 and N2 before pumping down. The resulting relatively defect free silicon oxynitride layers can be advantageously employed as an ARC, particularly when patterning contact holes in manufacturing flash memory devices.

Abstract: The adhesion of a barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member, after CMP, in a reaction chamber with a plasma containing ammonia and nitrogen for a brief period of time to reduce the surface oxide and then introducing silane into the reaction chamber to deposit the barrier layer, e.g., silicon nitride, under high density plasma conditions in the presence of nitrogen. The presence of nitrogen during plasma oxide layer reduction and plasma barrier layer deposition significantly improves adhesion of the barrier layer to the Cu or Cu alloy surface.

Abstract: A method is provided for forming conductive layers in semiconductor device channels and vias by using forward current and periodic pulse reverses for filling inward from the sidewalls of the channels and vias. The pulse reversals and inward filling reduce recrystallization rate to improve electromigration resistance and reduce the stress in the conductive layers to eliminate voids.

Abstract: A method of depositing a thin film on a substrate in a semiconductor device using Atomic Layer Deposition (ALD) process parameters exposes the substrate to at least one adherent material in a quantity sufficient for the material to adsorb onto the substrate and thereby form an initiation layer. The initiation layer presents at least one first reactive moiety which is then chemically reacted with at least one first reaction material using atomic layer deposition conditions to form a second reactive moiety. The second reactive moiety is then chemically reacted with at least one second reaction material under process conditions sufficient to form a reaction layer over the initiation layer. The process may be repeated to form successive reaction layers over the initiation layer. The adherent material constituting the initiation layer is preferably one which is not substantially degraded by the atomic layer deposition parameters.

Abstract: In the formation of a halftone type phase shift mask, a reactive gas introduction inlet and an inert gas introduction inlet are provided so as to introduce the respective gases separately and by using a reactive low throw sputtering method a molybdenum silicide based phase shifter film is formed. Thereby, it becomes possible to provide a halftone type phase shift mask, which is applicable to an ArF laser or to a KrF laser, by using molybdenum silicide based materials.

Abstract: The present invention relates to a method and apparatus for forming interconnects on a substrate such as a semiconductor wafer by filling a conductive material such as copper (Cu) in fine recesses formed in a surface of the substrate. A method for forming interconnects comprises providing a substrate and a target composed of a conductive material in confrontation with each other in a chamber, introducing a sputtering gas into the chamber while a high voltage is applied between the substrate and the target to cause the sputtering gas to collide with the target, and depositing particles of the conductive material emitted from the target on the surface of the substrate to form a thin film, while sputter-etching the thin film by reflection sputtering gas molecules reflected from the target and having high energy.

Abstract: A method for providing a low carbon and/or low oxygen containing conductive material includes providing a substrate assembly having a surface and providing a stream of a precursor containing conductive material to a region proximate the surface of the substrate assembly where the conductive material is to be deposited. A stream of reaction gas is also provided to the region proximate the surface of the substrate assembly where the conductive material is to be deposited. The reaction gas is one of an oxygen or hydrogen containing gas. A focused beam is scanned over the surface of the substrate assembly in the presence of the stream of precursor containing conductive material and the stream of the reaction gas to deposit the conductive material on the surface. The stream of the precursor containing conductive material may include a stream of a precursor containing one of platinum, palladium, rhodium, ruthenium, chromium, silver, and iridium; preferably platinum.

Abstract: The present invention is directed to a method of forming process layers comprised of silicon oxynitride. In one embodiment, the method comprises positioning a wafer in a process chamber, introducing silane and nitrous oxide into the chamber at a flow rate ratio ranging from approximately 2.6-3.8 silane to nitrous oxide, and generating a plasma in the chamber using a high frequency to low frequency power setting ratio ranging from approximately 1.2-1.8.

Abstract: A process for preparing a semiconductor device includes a step of surface-modifying a desired portion of the surface of a substrate carried out in an atmosphere containing oxygen or nitrogen atoms. The process also includes a step of depositing selectively a metal on an electron-donative surface provided corresponding to the desired portion.

Abstract: An apparatus and method for performing material deposition on semiconductor devices. The apparatus provides an enclosure for defining a chamber. The chamber includes a metallic portion such as a conductor coil powered by a voltage generator. A gas, having a suspension of particles for treating the semiconductor devices, is introduced into the chamber and the powered conductor coil converts the gas to inductively coupled plasma and vaporizes the particles. The particles can then be deposited on the semiconductor devices.

Abstract: A method for electroplating a copper layer (118) over a wafer (20) powers a cathode of an electroplating system (10) in a manner that obtains improved copper interconnects. A control system (34) powers the cathode of the system (10) with a mix of two or more of: (i) positive low-powered DC cycles (201 or 254); (ii) positive high-powered DC cycles (256 or 310); (iii) low-powered, pulsed, positive-power cycles (306 or 530); (iv) high-powered, pulsed, positive-powered cycles (212, 252, 302, or 352); and/or (v) negative pulsed cycles (214, 304, 510, 528, or 532). The collection of these cycles functions to electroplate copper or a like metal (118) onto the wafer (20). During electroplating, insitu process control and/or endpointing (506, 512, or 520) is performed to further improve the resulting copper interconnect.

Abstract: A method for plating a second metal directly to a first metal without utilizing a mask. A semiconductor substrate is provided including at least one metal feature and at least one insulating layer covering the metal feature and the substrate. At least one recess is formed in the at least one insulating layer thereby exposing at least a portion of the metal feature. At least one conductive barrier layer is formed over the insulating layer and the exposed portion of the metal feature. A plating seed layer of a first metal is formed over the at least one barrier layer. A photoresist layer is deposited over the plating seed layer. Portions of the photoresist layer and portions of the plating seed layer outside of the at least one recess are removed. Photoresist remaining in the at least one recess is removed. A second metal is electroplated to the plating seed layer in the recess, using the barrier layer to conduct electrical current.

Abstract: A method and apparatus for depositing a titanium containing layer on a semiconductor substrate employing high density plasma processing techniques. The titanium source includes a TiCl4 gas which is flowed into a process chamber along with an inert gas source, such as argon and a flow of hydrogen gas. A plasma is present in the process chamber where the semiconductor substrate is situated. The apparatus includes a dome-shaped cover which forms part of the process chamber. The cover includes aperture centrally disposed therein and is adapted to produce a flow of TiCl4 gas that is directed substantially transverse to the semiconductor substrate, with a portion of the flow of hydrogen gas and the inert gas source positioned between the cover and the flow of TiCl4 gas.

Abstract: It is intended to provide a method of forming a gate overlap lightly doped impurity region (GOLD). After a gate insulating film is formed by a material mainly made of silicon oxide and a gate electrode is formed with, for instance, silicon, lightly doped impurity regions are formed. A coating mainly made of silicon is formed on the entire surface including the surface of the gate electrode. Side walls mainly made of silicon are formed on the side faces of the gate electrode by anisotropically or semi-anisotropically etching the thus-formed coating in an atmosphere of ClF3, for instance. In this etching step, since a selective etching ratio of the side walls to the gate insulating film is sufficiently large, etching of the gate insulating film is negligible. A source and a drain are then formed by doping an impurity at a high concentration using the gate electrode and the side walls as a mask.

Abstract: There is provided a means for selectively coating a coating liquid on a desired coating position when the coating liquid for forming an EL layer is coated. When the coating liquid is coated, a mask is provided between a coating liquid chamber and a substrate, and a voltage is applied to the mask, so that the coating liquid can be selectively coated on the desired coating position.

Abstract: A semiconductor fabrication apparatus and methods for processing materials on a semiconductor wafer are disclosed. The fabrication apparatus is a processing chamber comprising: an ultraviolet radiation source and an infrared radiation source, the radiation sources symmetrically arranged such that radiation is substantially uniform throughout the chamber and the radiation sources being capable of being used as a film deposition radiation source or a film annealing radiation source or both; an ultraviolet radiation sensor and an infrared radiation sensor to provide a feedback loop to the ultraviolet radiation source and to the infrared radiation source, respectively, so that a desired level of ultraviolet radiation and infrared radiation is maintained inside the chamber.

Abstract: In one aspect, a deposition method comprises the following steps: a) forming a layer on a semiconductive substrate, the layer comprising predominately an inorganic material, the layer also comprising incorporated carbon; b) generating a plasma adjacent the layer from a component gas, the component gas consisting essentially of N2; and c) utilizing the plasma to remove the carbon from the layer.

Abstract: The invention relates to a process and a device for metallization of semiconductor structures, with which areas of the surface can be connected to be electrically conductive using strip conductors in one or a plurality of planes, and contacts between the strip conductors of different planes. The process for producing metallic coatings on semiconductor structures by depositing from a vapor phase under vacuum, in trenches produced for the strip conductors and holes for strip conductor connection in the substrate material such as SiO2 or other inorganic and organic materials is characterized in that a known per se pulsed vacuum-arc evaporator is used, a barrier layer being deposited on the surface of the trenches and holes of the substrates using the plasma of the evaporator and/or the trenches and holes being filled with low-impedance strip conductor material from a further plasma of said type of evaporator.

Abstract: An article of manufacture and method of forming nanoparticle sized material components. A semiconductor oxide substrate includes nanoparticles of semiconductor oxide. A modifier is deposited onto the nanoparticles, and a source of metal ions are deposited in association with the semiconductor and the modifier, the modifier enabling electronic hole scavenging and chelation of the metal ions. The metal ions and modifier are illuminated to cause reduction of the metal ions to metal onto the semiconductor nanoparticles.

Abstract: In a method of forming a microelectronic structure of a Pt/BSTO/Pt capacitor stack for use in a DRAM device, the improvement comprising substantially eliminating or preventing oxygen out-diffusion from the BSTO material layer, comprising: a) preparing a bottom Pt electrode formation; b) subjecting the bottom Pt electrode formation to an oxygen plasma treatment to form an oxygen enriched Pt layer on the bottom Pt electrode; c) depositing a BSTO layer on said oxygen enriched Pt layer; d) depositing an upper Pt electrode layer on the BSTO layer; e) subjecting the upper Pt electrode layer to an oxygen plasma treatment to form an oxygen incorporated Pt layer; and f) depositing a Pt layer on the oxygen incorporated Pt layer upper Pt elect.

Abstract: A semiconductor device manufacturing method capable of proceeding semiconductor device manufacturing processes according to predetermined schedules or while correcting them without testpieces is provided. The method includes the steps of collecting actually observed data during at least one of plural steps, obtaining prediction data in at least one of plural steps by using an ab initio molecular dynamics process simulator or a molecular dynamics simulator, comparing and verifying the prediction data and the actually observed data sequentially at real time, and correcting and processing the plural manufacturing process factors sequentially at real time if a difference in significance is recognized between set values for the plural manufacturing process factors and the plural manufacturing process factors estimated from the actually observed data according to comparison and verification.

Abstract: In a titanium film forming method of this invention, before a titanium film is formed, the temperature in a reaction chamber for forming the titanium film is set to a temperature or more at which hydrogen chloride is produced by chlorine and hydrogen. A hydrogenated gas is then fed into the reaction chamber for a predetermined period of time. With this process, before the titanium film is formed, chlorine gas and titanium chloride gas left in the reaction chamber for forming the titanium film are reduced.

Abstract: The present invention provides three embodiments to deposit layers over a substrate using ultrasound energy to vibrate the substrate during (1) PVD or CVD deposition, (2) anneal or (3) plating deposition. The first embodiment deposits a first layer over a substrate using ultrasonic energy to vibrate the substrate. The ultrasound allows the layer to deposit more conformal over opening sidewalls and decreases overhangs and voids. The second embodiment involves using ultrasonic vibrations during annealing or RTA. The ultrasound smooches out barrier/seed/conductive layers in contact holes. The third embodiment is a method of plating a metal layer such as Cu over a substrate while vibrating the substrate with ultrasonic waves. The substrate is vibrated with ultrasound waves in vertical or horizontal direction. The ultrasonic vibration allow the metal to plate in small contact holes with improved step coverage.

Abstract: Semiconductor fabrication methods for processing materials on a semiconductor wafer are disclosed. An exemplary method the semiconductor fabrication apparatus comprises processing a material on a semiconductor assembly during semiconductor fabrication, by the steps of: precleaning a semiconductor assembly in ultraviolet radiation, the step of precleaning performed prior to the step of forming; forming a film in ultraviolet radiation and infrared radiation; annealing the film ultraviolet light radiation and infrared radiation.

Abstract: An external inductive coil is used in a plasma process system having a dielectric shield which separates the coil from the plasma. The shield includes channels provided along the inner side of the shield facing the plasma region. The channels inhibit the formation of a continuous metal film over the inner surface of the shield during sputtering and deposition. The sidewalls defining the channels permit RF transmission after the surfaces directly facing the plasma are coated with metal.

Abstract: A method for treating exposed surfaces of a low k carbon doped silicon oxide dielectric material in order to protect the low k carbon doped silicon oxide dielectric material from damage during removal of photoresist mask materials is described. The process comprises (a) first treating the exposed surfaces of a low k carbon doped silicon oxide dielectric material with a plasma capable of forming a densified layer on and adjacent the exposed surfaces of low k carbon doped silicon oxide dielectric material and (b) then treating the semiconductor wafer with a mild oxidizing agent capable of removing photoresist materials from the semiconductor wafer. These steps will prevent the degradation of the exposed surfaces of a low k carbon doped silicon oxide dielectric material during removal of an etch mask after formation of vias or contact openings in the low k carbon doped silicon oxide dielectric material.

Abstract: The present invention provides a method of fabricating a semiconductor device, including the steps of (a) forming a gate electrode in device formation regions on a semiconductor substrate having first conductivity, (b) forming diffusion layers in the device formation regions, the diffusion layers having second conductivity, (c) removing naturally oxidized films having been formed on both the diffusion layers and the gate electrode, in vacuum condition, (d) selectively forming cobalt films on both the diffusion layers and the gate electrode by chemical vapor deposition using gas produced by gasifying cobalt organic compound, (e) carrying out thermal annealing to selectively form cobalt disilicide (CoSi.sub.

Abstract: This invention provides a stable process for depositing films which include silicon and nitrogen, such as antireflective coatings of silicon oxynitride. Nitrogen is employed to permit lower flow rates of the process gas containing silicon, thereby reducing the deposition rate and providing better control of film thickness. Additionally, the use of nitrogen stabilizes the process, improving film uniformity, and provides a higher-quality film. The invention is capable of providing more accurate and easier fabrication of structures requiring uniformly thin films containing silicon, nitrogen, and, optionally, oxygen, such as antireflective coatings.

Abstract: Microwave radiation, perhaps with microwave absorbing materials, is utilized to provide heating of partially formed integrated circuits in a variety of circumstances.

Abstract: A method of forming an electrical contact to a substrate includes, a) placing a substrate having a silicon node to which electrical connection is to be made within a chemical vapor deposition reactor; b) injecting a first titanium organometallic precursor to within the reactor having the substrate positioned therein, and maintaining the reactor at a temperature and a pressure which in combination are effective to deposit a first layer comprising titanium nitride onto the substrate over the node to a first thickness, the first layer of titanium nitride having incorporated carbon from the first titanium organometallic precursor, the first layer and silicon node defaming a contact interface therebetween; c) after depositing the first layer, ceasing to inject the first titanium organometallic precursor into the reactor and first injecting a first component gas into the reactor and generating a first plasma from the first component gas within the reactor against the first layer, the first component gas and first p

Abstract: The present invention includes a method of improving conductivity between an electrode and a plug in a stacked capacitor where an oxide has formed therebetween. The method includes the steps of bombarding the oxide with ions and mixing the oxide with materials of the electrode and the plug to increase a conductivity between the electrode and the plug. A method of forming a diffusion barrier within an electrode in a stacked capacitor includes the steps of providing a stacked capacitor having a plug coupled to an electrode and bombarding the electrode with ions to form the diffusion barrier within the electrode such that the diffusion barrier is electrically conductive. A stacked capacitor in accordance with the present invention includes an electrode, a plug for electrically accessing a storage node, the plug being coupled to the electrode and a barrier layer disposed within the electrode for preventing diffusion of materials which reduce conductivity between the electrode and the plug.

Abstract: A method of fabricating a semiconductor device includes the step of removing native oxide on the surface of a metal silicide layer formed on a shallow impurity diffusion layer and exposed at the bottom portion of a contact hole by sputter etching under an incident ion condition of a high density and a low energy. In this sputter etching, the side surface of the contact hole is prevented from being sputtered and re-deposited on the bottom portion of the contact hole, whereby the native oxide is effectively removed while the impurity diffusion layer is prevented from being damaged. In addition, a substrate may be heated during sputter etching for preventing ion species such as Ar.sup.+ from being entrapped in the metal silicide layer.

Abstract: A method is disclosed for forming a buried contact within an integrated circuit ("IC"). Initially, a gate oxide layer is deposited onto a surface of a silicon substrate. A first polysilicon layer is deposited onto the gate oxide layer using an ionized cluster beam ("ICB") technique. The first polysilicon layer and the gate oxide layer are patterned and etched at predetermined locations, exposing the underlying silicon substrate surface at these locations. A small amount of undesirable native oxide grows on the exposed substrate surface. This oxide represents an unwanted impedance, which degrades IC device performance. The ICB machine is then used to deposit a second layer of polysilicon on the silicon substrate, including over the oxide layer regions and over the exposed silicon substrate surface at the predetermined locations. This second polysilicon deposition step breaks up and removes the unwanted native oxide from the silicon substrate.

Abstract: A production method for forming contact structures on a planar surface of a substrate.

Abstract: A semiconductor fabrication apparatus and methods for processing materials on a semiconductor wafer are disclosed. The fabrication apparatus is a processing chamber comprising: an ultraviolet radiation source and an infrared radiation source, the radiation sources symmetrically arranged such that radiation is substantially uniform throughout the chamber and the radiation sources being capable of being used as a film deposition radiation source or a film annealing radiation source or both; an ultraviolet radiation sensor and an infrared radiation sensor to provide a feedback loop to the ultraviolet radiation source and to the infrared radiation source, respectively, so that a desired level of ultraviolet radiation and infrared radiation is maintained inside the chamber.

Abstract: An IC wiring connecting method for interconnecting conductive lines of the same wiring plane of an IC chip for correcting the wiring, for interconnecting conductive lines of different wiring lanes of a multilayer IC chip at the same position, or for connecting a conductive line of a lower wiring plane of a multilayer IC chip to a conductive line formed at a separate position on the same multilayer IC chip. The insulating film or films covering conductive lines to be interconnected are processed by an energy beam such as a concentrated ion beam to form holes so as to expose the respective parts of the conductive lines where the conductive lines are to be interconnected, then a metal is deposited over the surfaces of the holes and an area interconnecting the holes by irradiating the surfaces of the holes and the area by an energy beam or a concentrated ion beam in an atmosphere of a gaseous organic metal compound to form a conductive metal film electrically interconnecting the conductive lines.

Abstract: A method of forming an electrical contact to a substrate includes, a) placing a substrate having a silicon node to which electrical connection is to be made within a chemical vapor deposition reactor; b) injecting a first titanium organometallic precursor to within the reactor having the substrate positioned therein, and maintaining the reactor at a temperature and a pressure which in combination are effective to deposit a first layer comprising titanium nitride onto the substrate over the node to a first thickness, the first layer of titanium nitride having incorporated carbon from the first titanium organometallic precursor, the first layer and silicon node defining a contact interface therebetween; c) after depositing the first layer, ceasing to inject the first titanium organometallic precursor into the reactor and first injecting a first component gas into the reactor and generating a first plasma from the first component gas within the reactor against the first layer, the first component gas and first p