Abstract: A nonvolatile memory device, including a lower electrode on a semiconductor substrate, a phase change material pattern on the lower electrode, an adhesion pattern on the phase change material pattern and an upper electrode on the adhesion pattern, wherein the adhesion pattern includes a conductor including nitrogen.

Abstract: The present invention provides an antenna with low resistance and a semiconductor device having an antenna whose communication distance is improved. A fluid containing conductive particles is applied over an object. After curing the fluid containing the conductive particles, the fluid is irradiated with a laser to form an antenna. As a method for applying the fluid containing the conductive particles, screen printing, spin coating, dipping, or a droplet discharging method is used. Further, a solid laser having a wavelength of 1 nm or more and 380 nm or less is used as the laser.

Abstract: The present invention provides a method of manufacturing an organic thin film transistor (TFT), comprising: providing a substrate layer; providing a gate electrode layer; providing a dielectric material layer; providing an organic semiconductor (OSC) material layer; providing a source and drain electrode layer; and wherein one or more of the layers is deposited using a laser induced thermal imaging (LITI) process. Preferably the organic TFT is a bottom gate device and the source and drain electrodes are deposited on an organic semiconductor layer, or over a dielectric material layer using LITI. Further preferably a dopant material may be provided between the OSC material and the source and drain electrode layer, wherein the dopant material may also be deposited using LITI. Also preferably, wherein the dopant may be a charge neutral dopant such as substituted TCNQ or F4TCNQ.

Abstract: Embodiments of the present invention describe a method of forming nickel sulfide layer on a semiconductor device. A nickel sulfide layer is formed on a substrate by alternatingly exposing the substrate to a nickel-containing precursor and a sulfur-containing precursor.

Abstract: A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.

Abstract: An antenna with air-filled trench is integrated with a radio frequency (RF) circuit. The trench locates directly under the metal lines that made up the antenna and is formed by etching from the back side of the semiconductor substrate until all the substrate material in the trench is removed. The air-filled trench greatly reduces the losses due to the semiconductor substrate; therefore the performance of the antenna improves greatly. When the antenna is a large planar spiral inductor, the air-filled trench means the semiconductor substrate inside the spiral inductor is untouched; hence integrated circuit can be built inside the antenna and on that substrate. Therefore the RF integrated circuit has a smaller size. Air-filled trench can also be used to reduce the semiconductor substrate noise coupling between digital circuit block and analog/RF circuit block. This air-filled trench and the air-filled trench under the antenna are formed at the same time.

Abstract: A method of forming a noble metal cap on a conductive material embedded in a dielectric material in an interconnect structure. The method includes the step of contacting (i) a conductive material having a bare upper surface partially embedded in a dielectric material and (ii) vapor of a noble metal containing compound, in the presence of carbon monoxide and a carrier gas. The contacting step is carried out at a temperature, pressure and for a length of time sufficient to produce a noble metal cap disposed directly on the upper surface of the conductive material without substantially extending into upper surface of the dielectric material or leaving a noble metal residue onto the dielectric material.

Abstract: The present invention generally provides an absorber layer using carbon based materials with increased and stabled thermal absorption coefficient and economical methods to produce such an absorber layer. One embodiment of the present invention provides a method for processing a substrate comprising depositing an absorber layer on a top surface of the substrate, wherein the substrate is maintained under a first temperature, annealing the substrate in a thermal processing chamber, wherein the substrate is heated to a second temperature, and the second temperature is higher than the first temperature, and removing the absorber layer from the substrate.

Abstract: Copper seed layers are formed on diffusion barrier layers (e.g., on Ta, and TaNx layers) without significant agglomeration of copper, with the use of an engineered barrier layer/seed layer interface. The engineered interface includes an adhesion layer, in which copper atoms are physically trapped and are prevented from migrating and agglomerating. The adhesion layer can include between about 20-80% atomic of copper. The copper atoms of the adhesion layer are exposed during deposition of a copper seed layer and serve as the nucleation sites for the deposited copper. Thin, continuous, and conformal seed layers can be deposited on top of the adhesion layer. The trapping of copper within the adhesion layer is achieved by intermixing diffusion barrier and seed layer materials using PVD and/or ALD.

Abstract: A plasma processing method performs a desired plasma process on substrates by using a plasma generated in a processing space. A first and a second electrode are disposed in parallel in a processing vessel that is grounded, the substrate is supported on the second electrode to face the first electrode, the processing vessel is vacuum evacuated, a desired processing gas is supplied into the processing space formed between the first electrode, the second electrode and a sidewall of the processing vessel, and a first radio frequency power is supplied to the second electrode. The first electrode is connected to the processing vessel via an insulator or a space, and is electrically coupled to a ground potential via a capacitance varying unit whose electrostatic capacitance is varied based on a process condition of the plasma process performed on the substrate.

Abstract: A film-forming method for forming a metal film on a substrate by a sputtering process includes the steps of depressurizing a processing space, in which deposition of the metal film is caused by the sputtering process, applying a DC bias voltage between the substrate and a target disposed in the processing space so as to face the substrate, and igniting plasma by introducing secondary electrons to the processing space from a secondary electron source.

Abstract: Electrodes formed in a partial surface area of a semiconductor substrate and distal ends of conductive nanotubes bristled on a surface of a growth substrate, are bombarded with rare gas plasma. The distal ends of the conductive nanotubes bombarded with the rare gas plasma are brought into contact with the electrodes bombarded with the rare gas plasma to fix the conductive nanotubes to the electrodes. The growth substrate is separated from the semiconductor substrate in such a manner that the conductive nanotubes fixed to the electrodes remain on the electrodes formed on the semiconductor substrate.

Abstract: An advanced modular plug connector assembly incorporating an insert assembly disposed in the rear portion of the connector housing. In one embodiment, the connector has a plurality of ports in multi-row configuration, and the insert assembly includes a substrate adapted to receive one or more electronic components such as choke coils, transformers, or other signal conditioning elements or magnetics. The substrate also interfaces with the conductors of two modular ports of the connector, and is removable from the housing such that an insert assembly of a different electronics or terminal configuration can be substituted therefor. In this fashion, the connector can be configured to a plurality of different standards (e.g., Gigabit Ethernet and 10/100). In yet another embodiment, the connector assembly comprises a plurality of light sources (e.g., LEDs) received within the housing. Methods for manufacturing the aforementioned embodiments are also disclosed.

Abstract: Chemical etching methods and associated modules for performing the removal of metal from the edge bevel region of a semiconductor wafer are described. The methods and systems apply liquid etchant in a precise manner at the edge bevel region of the wafer, so that the etchant is applied on to the front edge, the side edge and the back edge. The etchant thus does not flow or splatter onto the active circuit region of the wafer. An edge bevel removal embodiment involving that is particularly effective at obviating streaking, narrowing the metal taper and allowing for subsequent chemical mechanical polishing, is disclosed.

Abstract: Disclosed is a technique for embedding metal in a recess provided in the surface of a process object, such as a semiconductor wafer W, only by plasma sputtering. The metal is copper as a typical example. The recess has a microscopic hole or trench having a diameter or width of 100 nm or less as a typical example. A film forming step and a diffusion step are alternately performed a plurality of times. The film forming step deposits a small amount of a metal film in the recess. The diffusion step moves the deposited metal film toward the bottom portion of the recess. In the film forming step, bias power to be applied to a stage for supporting the wafer W is set to a value ensuring that, on the surface of the wafer W, the rate of metal deposition due to the drawing-in of metal particles is substantially equal to the rate of the sputter etching by plasma. In the diffusion step, the wafer W is maintained at a temperature which permits occurrence of surface diffusion of the metal film deposited in the recess.

Abstract: Embodiments of the present invention describe a method of forming nickel sulfide layer on a semiconductor device. A nickel sulfide layer is formed on a substrate by alternatingly exposing the substrate to a nickel-containing precursor and a sulfur-containing precursor.

Abstract: Recessed features on a Damascene substrate are filled with metal using plasma PVD. Recessed features having widths of less than about 300 nm, e.g., between about 30-300 nm can be filled with metals (e.g., copper and aluminum), without forming voids. In one approach, the deposition is performed by exposing the substrate to a high-density plasma characterized by high fractional ionization of metal. Under these conditions, the metal is deposited within the recess, without forming large overhang at the opening of the recess. In some embodiments, the metal is deposited within the recess, while diffusion barrier material is simultaneously etched from the field region. In a second approach, recessed features are filled by performing a plurality of profiling cycles, wherein each cycle includes a net etching and a net depositing operation. Etching and depositing parameters are adjusted such that the recessed features are filled without forming overhangs and voids.

Abstract: The invention relates to a method and device for depositing at least one layer, particularly a semiconductor layer, onto at least one substrate, which is situated inside a process chamber of a reactor while being supported by a substrate holder. The layer is comprised of at least two material components provided in a fixed stoichiometric ratio, which are each introduced into the reactor in the form of a first and a second reaction gas, and a portion of the decomposition products form the layer, whereby the supply of the first reaction gas, which has a low thermal activation energy, determines the growth rate of the layer, and the second reaction gas, which has a high thermal activation energy, is supplied in excess and is preconditioned, in particular, by an independent supply of energy. The first reaction gas flows in a direction toward the substrate holder through a multitude of openings, which are distributed over a surface of a gas inlet element, said surface being located opposite the substrate holder.

Abstract: An iPVD system is programmed to deposit uniform material, such as a metallic material, into high aspect ratio nano-sized features on semiconductor substrates using a process that enhances the feature filling compared to the field deposition, while maximizing the size of the grain features in the deposited material opening at the top of the feature during the process. Sequential deposition and etching are provided by controlling DC and high density power levels and other parameters.

Abstract: A semiconductor capacitor structure comprising sidewalls of conductive hemispherical grained material, a base of metal silicide material, and a metal nitride material overlying the conductive hemispherical grained material and the metal silicide material. The semiconductor capacitor structure is fabricated by forming a base of metal silicide material along the sidewalls of an insulative material having an opening therein, forming sidewalls of conductive hemispherical grained material on the metal silicide material, and forming a metal nitride material overlying the conductive hemispherical grained material and the metal silicide material.

Abstract: A substrate processing method for removing a resist film from a substrate having the resist film formed thereon comprises maintaining the inner region of the chamber at a prescribed temperature by putting a substrate in a chamber, denaturing the resist film by supplying ozone and a water vapor in such a manner that ozone is supplied into the chamber while a water vapor is supplied into the chamber at a prescribed flow rate, the amount of ozone relative to the amount of the water vapor being adjusted such that the dew formation within the chamber is prevented, and processing the substrate with a prescribed liquid material so as to remove the denatured resist film from the substrate.

Abstract: A semiconductor device is manufactured by forming a gate electrode layer over a substrate having a light transmitting property; forming a gate insulating layer over the gate electrode layer; forming a photocatalyst material over the gate insulating layer; immersing the photocatalyst material in a solution containing a plating catalyst material and selectively exposing the photocatalyst material to light transmitted through the substrate in the solution containing the plating catalyst material with the use of the gate electrode layer as a mask to adsorb or deposit the plating catalyst material onto the light-exposed photocatalyst material; immersing the plating catalyst material in a plating solution containing a metal material to form a source electrode layer and a drain electrode layer on the surface of the photocatalyst material adsorbing or depositing the plating catalyst material; and forming a semiconductor layer over the source electrode layer and the drain electrode layer.

Abstract: The present invention is a method of manufacturing miniaturized organic laminate substrate PCB, semiconductors, semiconductor wafers and semiconductor devices that have a 50% reduction in physical dimensions with respect to prior art existing organic laminate substrate PCB, semiconductors, semiconductor wafers and semiconductor devices. The base planar substrate has a vapor deposited 0.02 mil thick copper cladding thereon its first planar surface that has been affixed atop a hydrophillic layer, and an adhesive layer on its second planar surface. The copper cladding has sufficient peel strength and a low enough etch factor so as to allow 10 micron (or smaller) electrical trace pathways to be formed thereon when the steps of a specifically designed manufacturing methodology are followed.

Abstract: A method for forming a metal line of a semiconductor device includes forming an interlayer insulation film over a semiconductor substrate, forming a trench for exposing at least a portion of the semiconductor substrate by using a selective etching process, and forming a diffusion barrier layer over the interlayer film and the inner walls of the trench, by using a plasma enhanced atomic layer deposition process in which a high frequency power generator is set to have a frequency of 13.56 MHz. The plasma enhanced atomic layer deposition process is performed with a base pressure in a chamber maintained at 1×10?8 to 3×10?7 torr.

Abstract: A method of forming a via hole reaching a bonding pad in a wafer having an insulating film constituting a plurality of devices on the front surface of a substrate and bonding pads on each of the devices by applying a pulse laser beam to the rear surface of the substrate, the method comprising the steps of: forming a non-through hole reaching the insulating film formed on the substrate by applying a pulse laser beam to the rear surface of the substrate; forming an insulating film on the inner wall of the hole which is formed in the substrate by the first step; and forming a via hole reaching a bonding pad by applying a pulse laser beam to the hole having the insulating film which is formed on the inner wall by the insulating film forming step.

Abstract: Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.

Abstract: A semiconductor device comprises metal lines in a specific metallization layer which have a different thickness and thus a different resistivity in different device regions. In this way, in high density areas of the device, metal lines of reduced thickness may be provided in order to comply with process requirements for achieving a minimum pitch between neighboring metal lines, while in other areas having less critical constraints with respect to minimum pitch, a reduced resistivity may be obtained at reduced lateral dimensions compared to conventional strategies. For this purpose, the dielectric material of the metallization layer may be appropriately patterned prior to forming respective trenches or the etch behavior of the dielectric material may be selectively adjusted in order to obtain differently deep trenches.

Abstract: The object of the present invention is a method and compositions for direct copper plating and filling to form interconnects in the fabrication of semiconductor devices. According to the invention, this method comprises: providing an electrolytic copper bath containing, in solution in a solvent, a source of copper ions with a concentration of between 45 and 200 mM, preferably of between 45 and 100 mM and at least one copper complexing agent which is an aliphatic polyamine having 2 to 4 amine functions with a concentration of between 30 and 200 mM, preferably of between 60 and 200 mM; the copper/complexing agent(s) molar ratio being of between 0.2 and 2, preferably between 0.3 and 1.5; bringing said copper diffusion barrier layer of said substrate into contact with said electrolytic copper bath, applying an electrical bias to the substrate for a duration adjusted according to the thickness of copper to be electroplated, removing the substrate from said electrolytic copper bath.

Abstract: A microelectronic method for the fabrication of a transistor gate using a precursor material that is suitable for being broken down into at least one metallic material after having been exposed to an electron beam. The invention applies in particular to the fabrication of multi-channel transistors, of the FinFET, suspended-channel, ITS or GAA type.

Abstract: A method of forming an EL-Cu enhanced noble metal layer begins with providing a semiconductor substrate in a reaction chamber, wherein the semiconductor substrate includes a trench etched into a dielectric layer. Next, an organometallic precursor containing a noble metal and a reactive gas are pulsed into the reaction chamber proximate to the semiconductor substrate where they react to form a noble metal layer directly on the dielectric layer within the trench. The substrate is then moved into an electroless plating bath and an electroless plating process deposits a copper seed layer onto the noble metal layer. The substrate is then removed from the plating bath.

Abstract: The invention provides a method of exposing low-k dielectric films to microwave radiation to cure the dielectric films. Microwave curing reduces the cure-time necessary to achieve the desired mechanical properties in the low-k films, thus decreasing the thermal exposure time for the NiSi transistor contacts. A lower thermal budget for interconnect fabrication is necessary to prevent damage to the NiSi transistor contacts and minimize thermal stressing of previously formed interconnect layers. Microwave-cured dielectric films also have higher mechanical strength and strong adhesion to overlying layers deposited during subsequent semiconductor device manufacturing steps.

Abstract: A method of manufacturing a wiring substrate having a wiring layer formation step that includes: a first surface processing step in which surface processing is performed on a film formation area of a substrate; a wiring formation step in which a wiring pattern is formed by placing a first liquid material on the film formation area; a second surface processing step in which surface processing is once again performed on the film formation area; and an insulating film formation step in which an insulating film is formed by placing a second liquid material in gaps in the wiring pattern, wherein an affinity between the second liquid material and the film formation area in the insulating film formation step is greater than an affinity between the first liquid material and the film formation area in the wiring formation step.

Abstract: An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a first porous low-k layer on the substrate, a damascene structure in the first porous low-k layer electrically connecting with the conductive part, a second porous low-k layer over the first porous low-k layer and the damascene structure, and a UV cutting layer at least between the first and the second porous low-k layers, wherein the UV cutting layer is a UV reflection layer or a UV reflection-absorption layer.

Abstract: A pattern formation substrate comprising a substrate having thereon a hydrophobic region exhibiting repellency to liquid drops and a hydrophilic line exhibiting affinity with liquid drops. The hydrophilic line has such a surface treatment that upon landing of a liquid drop thereon, the liquid drop moves in the arrowed direction. Thus, attachment of liquid drops to regions to which liquid drops should not be adhered can be prevented, thereby enabling forming a pattern of desired characteristics.

Abstract: The present invention provides a method for forming a wiring having a minute shape on a large substrate with a small number of steps, and further a wiring substrate formed by the method. Moreover, the present invention provides a semiconductor device in which cost reduction and throughput improvement are possible due to the small number of steps and reduction of materials and which has a semiconductor element with a minute structure, and further a manufacturing method thereof. According to the present invention, a composition including metal particles and organic resin is irradiated with laser light and a part of the metal particles is baked to form a conductive layer typified by a wiring, an electrode or the like over a substrate. Further, a semiconductor device having the baked conductive layer as a wiring or an electrode is formed.

Abstract: Radiant electromagnetic energy beam steering method achieved following antenna conversion from electrical current and voltage characterized signals to radiant wave characterized signals by way of the influence of gaseous plasma of controlled plasma density and electron density on the electromagnetic energy. Reflection and refraction mechanisms are used to impose plasma influence on the steered electromagnetic energy. The employed plasma properties are determined by an electrically energized array of electrodes disposed along the plasma extent. Adaptation of the method to widely differing wavelength parts of the electromagnetic energy spectrum is included. A plurality of prior art patents is identified in supplement of present disclosure of the invention.

Abstract: Techniques for manufacturing a bond pad structure are provide. A method includes providing a substrate. A metal pad and passivation layer are formed over the substrate. The passivation layer includes an opening to expose a portion of the metal pad. A first film is deposited at least over the exposed portion of the metal pad. A second film is deposited over the first film. A photoresist layer is deposited over the substrate, and a trench is formed in the photoresist layer directly over the portion of the metal pad. A first layer is electroplated in the trench over the second film, and a barrier layer is electroplated in trench over the first layer. A termination electrode, comprising tin, is electroplated in the trench over the barrier layer. The photoresist layer is removed. In addition, the method can include etching to remove the second film and first film beyond a predetermined area. The termination electrode is then reflowed.

Abstract: A semiconductor electronic device includes a die of semiconductor material and a support. The die of semiconductor material includes an integrated electronic circuit and a plurality of contact pads associated with the electronic circuit and connected electrically to the support by wire leads. Each contact pad may include a lower layer of aluminum, copper, or alloys thereof, and an upper layer including at least one film of a metal and/or metallic alloy including nickel, palladium, or alloys thereof, and being deposited by an electroless chemical process.

Abstract: A method of fabricating and separating semiconductor structures comprises the steps of: (a) partially forming a semiconductor structure attached to a support structure, the partially formed semiconductor structure comprising a plurality of partially formed devices, where the partially formed devices are attached to one another by at least one connective layer; (b) forming a partial mask layer over at least a part of the partially formed devices; (c) etching the connective layer to separate the devices; and (d) removing the partial mask layer. Advantages of the invention include higher yield than conventional techniques. In addition, less expensive equipment can be used to separate the devices. The result is a greater production of devices per unit of time and per dollar.

Abstract: A gallium nitride-based compound semiconductor light-emitting device which includes an n-type semiconductor layer of a gallium nitride-based compound semiconductor, a light-emitting layer of a gallium nitride-based compound semiconductor and a p-type semiconductor layer of a gallium nitride-based compound semiconductor formed on a substrate in this order, and has a negative electrode and a positive electrode provided on the n-type semiconductor layer and the p-type semiconductor layer, respectively; wherein the negative electrode includes a bonding pad layer and a contact metal layer which is in contact with the n-type semiconductor layer, and the contact metal layer is composed of Cr or a Cr alloy and formed through sputtering.

Abstract: A method of processing a semiconductor workpiece. The method includes flowing a process gas to a semiconductor workpiece through a first plurality of orifices positioned in a gas distribution faceplate. The method also includes removing gas from over the semiconductor workpiece through a chamber exhaust port and a second plurality of orifices positioned in the gas distribution faceplate.

Abstract: According to one aspect of the invention, a method for forming contact formations is provided. A substrate may be placed in an electrolytic solution. The substrate may have an exposed conductive portion and the electrolytic solution may include a plurality of metallic ions and an accelerator. The accelerator may include at least one of bis-(sodium sulfopropyl)-disulfide and 3-mercapto-1-propanesulfonic acid-sodium salt. A voltage may be applied across the electrolytic solution and the conductive portion of the substrate to cause the metallic ions to be changed into metallic particles and deposited on the conductive portion. The electrolytic solution may also include a protonated organic additive. The electrolytic solution may also include an acid and a surfactant. The acid may include at least one of sulfuric acid, methane sulfonic acid, benzene sulfonic acid, and picryl sulfonic acid. The surfactant may include at least one of polyethylene glycol and polypropylene glycol.

Abstract: Systems and methods are disclosed to perform semiconductor processing with a process chamber; a flash lamp adapted to be repetitively triggered; and a controller coupled to the control input of the flash lamp to trigger the flash lamp. The system can deploy a solid state plasma source in parallel with the flash lamp in wafer processing.

Abstract: In a method of forming a thin layer for a semiconductor device through an ALD process and a CVD process in the same chamber, a semiconductor substrate is introduced into a processing chamber, and an interval between a showerhead and the substrate is adjusted to a first gap distance. A first layer is formed on the substrate at a first temperature through an ALD process. The interval between the showerhead and the substrate is additionally adjuted to a second gap distance, and a second layer is formed on the first layer at a second temperature through a CVD process. Accordingly, the thin layer has good current characteristics, and the manufacturing throughput of a semiconductor device is improved.

Abstract: The present voice and data telecommunications connector includes a set of wires each having a first end terminating in a first 50-pin amphenol connector for connecting to a 50-pin amphenol socket of a converged voice and data telecommunications device; a first group of said set of wires each having a second end terminating in a 50-pin amphenol connector for connecting to a 50-pin amphenol trunk socket of a compact integrated communications system device; and a second group of the set of wires each having a second end terminating in a 50-pin amphenol connector for connecting to a 50-pin amphenol station socket of the compact integrated communications system device. Another embodiment provides for a voice and data telecommunications connector that includes a set of wires having a first end terminating in a 50-pin amphenol connector and three 50-pin amphenol connectors for connecting to a modular integrated communications device.

Abstract: A transponder chip module is recessed into the surface of a substrate, end portions of an antenna wire are held in place on terminal areas of the chip module by a patch which may be transparent to allow laser bonding of the wire to the terminal areas. A cover may be disposed over everything. Conductive glue or a solderable material may be used to connect the wire to the terminal areas. A recess for the chip module, and a channel for the antenna wire may be formed by laser ablation. The substrate may be Teslin™, PET/PETE or Polycarbonate. The antenna wire may have a diameter of 60 ?m. A synthetic cushion material may be provided beneath the transponder chip module.

Abstract: A method for producing at least one local coating on a substrate is provided, as well as a combinatory substrate having such a local coating, a mask that is removable in a non-destructive manner being arranged on the substrate in a first step; the mask having at least one perforation, the perforation being at least partially filled with a reactive solution in a second step; and a coating reaction of the reactive solution with the substrate surface being induced in a third step to form the local coating.

Abstract: A method is provided for depositing a patterning material onto an optically transparent substrate by the use of a laser beam. A solid layer of a patterning material is placed adjacent to a receiving surface of the substrate. A laser beam is directed at an incident angle between 0 and 90° relative to the receiving surface. The laser beam is transmitted through the substrate and onto the solid layer to cause patterning material from the solid layer to deposit onto the receiving surface of the substrate.

Abstract: A method for manufacturing an SIP semiconductor device is provided. In this method, a first Organic Solderability Preservative (OSP) is coated over an upper surface of a semiconductor device including a plurality of elements and a first through electrode. An electrochemical plate (ECP) process is then performed on the semiconductor device. A second OSP is then coated over a lower surface of the semiconductor device, the lower surface including a Cu plug that has been formed over the first through electrode through the ECP process. The upper and lower (first and second) OSPs are used to prevent the Cu plug from being easily oxidized when exposed to the air.

Abstract: A method for plating a second metal directly to a first metal without utilizing a mask. A semiconductor substrate is provided including at least one metal feature and at least one insulating layer covering the metal feature and the substrate. At least one recess is formed in the at least one insulating layer thereby exposing at least a portion of the metal feature. At least one conductive barrier layer is formed over the insulating layer and the exposed portion of the metal feature. A plating seed layer of a first metal is formed over the at least one barrier layer. A photoresist layer is deposited over the plating seed layer. Portions of the photoresist layer and portions of the plating seed layer outside of the at least one recess are removed. Photoresist remaining in the at least one recess is removed. A second metal is electroplated to the plating seed layer in the recess, using the barrier layer to conduct electrical current.