Electroless Deposition Of Conductive Layer Patents (Class 438/678)
  • Patent number: 10515921
    Abstract: A semiconductor package has at least one die, a first redistribution layer and a second redistribution layer. The first redistribution layer includes a first dual damascene redistribution pattern having a first via portion and a first routing portion. The second redistribution layer is disposed on the first redistribution layer and over the first die and electrically connected with the first redistribution layer and the first die. The second redistribution layer includes a second dual damascene redistribution pattern having a second via portion and a second routing portion. A location of the second via portion is aligned with a location of first via portion.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Chun-Hui Yu
  • Patent number: 10032658
    Abstract: A manufacturing method of a semiconductor device according to the present invention comprises cleaning a semiconductor substrate. A first chemical liquid for forming a water-repellent protection film and a second chemical liquid coating the first chemical liquid are supplied on a surface of the semiconductor substrate. Alternatively, the semiconductor substrate is immersed in the first chemical liquid coated with the second chemical liquid. The semiconductor substrate is then dried.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: July 24, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinsuke Kimura, Yoshihiro Ogawa
  • Patent number: 9993853
    Abstract: Embodiments of methods and apparatus for removing particles from a surface of a substrate, such as from the backside of the substrate, are provided herein. In some embodiments, an apparatus for removing particles from a surface of a substrate includes: a substrate handler to expose the surface of the substrate; a particle separator to separate particles from the exposed surface of the substrate; a particle transporter to transport the separated particles; and a particle collector to collect the transported particles.
    Type: Grant
    Filed: November 28, 2014
    Date of Patent: June 12, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Sriskantharajah Thirunavukarasu, Jen Sern Lew, Arvind Sundarrajan, Srinivas D. Nemani
  • Patent number: 9875968
    Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: January 23, 2018
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
  • Patent number: 9818627
    Abstract: A manufacturing method of a semiconductor device according to the present invention comprises cleaning a semiconductor substrate. A first chemical liquid for forming a water-repellent protection film and a second chemical liquid coating the first chemical liquid are supplied on a surface of the semiconductor substrate. Alternatively, the semiconductor substrate is immersed in the first chemical liquid coated with the second chemical liquid. The semiconductor substrate is then dried.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: November 14, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinsuke Kimura, Yoshihiro Ogawa
  • Patent number: 9583331
    Abstract: A manufacturing method of a semiconductor device according to the present invention comprises cleaning a semiconductor substrate. A first chemical liquid for forming a water-repellent protection film and a second chemical liquid coating the first chemical liquid are supplied on a surface of the semiconductor substrate. Alternatively, the semiconductor substrate is immersed in the first chemical liquid coated with the second chemical liquid. The semiconductor substrate is then dried.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: February 28, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shinsuke Kimura, Yoshihiro Ogawa
  • Patent number: 9514983
    Abstract: A metal interconnect comprising cobalt and method of forming a metal interconnect comprising cobalt are described. In an embodiment, a metal interconnect comprising cobalt includes a dielectric layer disposed on a substrate, an opening formed in the dielectric layer such that the substrate is exposed. The embodiment further includes a seed layer disposed over the substrate and a fill material comprising cobalt formed within the opening and on a surface of the seed layer.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: December 6, 2016
    Assignee: Intel Corporation
    Inventors: Christopher J. Jezewski, James S. Clarke, Tejaswi K. Indukuri, Florian Gstrein, Daniel J. Zierath
  • Patent number: 9428836
    Abstract: A solution for electroless deposition of cobalt is provided. A reducing agent of Ti3+ ions is provided to the solution. Co2+ ions are provided to the solution.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: August 30, 2016
    Assignee: Lam Research Corporation
    Inventors: Eugenijus Norkus, Ina Stankeviciene, Aldona Jagminiene, Aniruddha Joi, Loreta Tamasauskaite-Tamasiunaite, Yezdi Dordi, Zita Sukackiene
  • Patent number: 9401478
    Abstract: A method for manufacturing a transistor includes: forming a base film for supporting a catalyst for electroless plating; forming a resist layer having an opening portion corresponding to source and drain electrodes onto the base film; causing the base film within the opening portion to support the catalyst for electroless plating and performing a first electroless plating; removing the resist layer; performing a second electroless plating on a surface of an electrode which is formed by the first electroless plating and forming the source and drain electrodes; and forming a semiconductor layer in contact with surfaces of the source and drain electrodes, the surfaces facing each other, wherein an energy level difference between a work function of a material which is used for the second electroless plating and an energy level of a molecular orbital which is used for electron transfer in a material of the semiconductor layer is less than an energy level difference between a work function of a material which is us
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: July 26, 2016
    Assignee: NIKON CORPORATION
    Inventors: Shohei Koizumi, Takashi Sugizaki, Kenji Miyamoto
  • Patent number: 9388504
    Abstract: A plating apparatus includes a processing bath configured to store a processing liquid therein, a transporter configured to immerse a substrate holder, holding a substrate, in the processing liquid, raise the substrate holder out of the processing bath, and transport the substrate holder in a horizontal direction, and a gas flow generator configured to generate a clean gas flow forward of the substrate with respect to a direction in which the substrate holder is transported. The transporter moves the gas flow generator together with the substrate holder in the horizontal direction while transporting the substrate holder in the horizontal direction.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: July 12, 2016
    Assignee: Ebara Corporation
    Inventor: Tomonori Hirao
  • Patent number: 9388497
    Abstract: There is provided a method of electroless gold plating, wherein the method includes a step of forming an underlying alloy layer on a base material and a step of forming a gold plate layer directly on the underlying alloy layer by means of electroless reduction plating using a cyanide-free gold plating bath, wherein the method is characterized in that the underlying alloy layer is formed of an M1-M2-M3 alloy (where M1 is at least one element selected from Ni, Fe, Co, Cu, Zn and Sn, M2 is at least one element selected from Pd, Re, Pt, Rh, Ag and Ru, and M3 is at least one element selected from P and B).
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: July 12, 2016
    Assignee: TOYO KOHAN CO., LTD.
    Inventor: Nobuaki Mukai
  • Patent number: 9269681
    Abstract: Some implementations provide a semiconductor device that includes a substrate coupled to a die through a thermal compression bonding process. The semiconductor device also includes a trace coupled to the substrate. The trace includes a first conductive material having a first oxidation property. The trace also includes a first surface layer including a second conductive material having a second oxidation property. The second oxidation property is less susceptible to oxidation than the first oxidation property. The first and second conductive materials are configured to provide an electrical path between the die and the substrate. The first surface layer has a thickness that is 0.3 microns (?m) or less.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: February 23, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Houssam W. Jomaa, Omar J. Bchir, Milind P. Shah, Manuel Aldrete, Chin-Kwan Kim
  • Patent number: 9257379
    Abstract: A coreless packaging substrate is provided which includes: a circuit buildup structure having at least a dielectric layer, at least a wiring layer and a plurality of conductive elements, a plurality of electrical pads embedded in the lowermost one of the at least a dielectric layer, a plurality of metal bumps formed on the uppermost one of the at least a wiring layer, and a dielectric passivation layer formed on the surface of the uppermost one of the circuit buildup structure and the metal bumps, with the metal bumps exposed from the dielectric passivation layer. The metal bumps each have a metal column portion and a wing portion integrally connected to the metal column portion, such that the bonding force between the metal bumps and a semiconductor chip is enhanced by the entire top surface of the wing portions of the metal bumps being completely exposed.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: February 9, 2016
    Assignee: Unimicron Technology Corporation
    Inventors: Tzyy-Jang Tseng, Chung-W. Ho
  • Patent number: 9232644
    Abstract: There is provided a wiring substrate. The wiring substrate includes: a first wiring layer; a first insulating layer on the first wiring layer; a first coupling agent layer on the first insulating layer; a first copper/tin alloy layer on the first coupling agent layer; a first via hole formed through the first copper/tin alloy layer, the first coupling agent layer, and the first insulating layer to reach the first wiring layer; a metal catalyst provided on only a sidewall of the first via hole; a seed layer provided on the metal catalyst and formed only on the sidewall of the first via hole; and a metal plating layer formed on the first copper/tin alloy layer and the seed layer and filled in the first via hole to contact the first wiring layer.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: January 5, 2016
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Yuichiro Shimizu
  • Patent number: 9202946
    Abstract: The present technology generally relates to methods for metallizing an aluminum paste comprising contacting the aluminum paste with a cleaner, contacting the aluminum paste with an oxidation inhibiting deposit solution to deposit a layer of an oxidation inhibiting composition onto the aluminum paste and contacting the aluminum paste with conductive metal deposit solution to deposit a layer of a conductive metal onto the aluminum paste. Specifically, the present technology includes methods metallizing an aluminum paste comprising contacting the aluminum paste with an acidic cleaner, contacting the aluminum paste with an acid zincate solution to deposit zinc onto the aluminum paste and contacting the aluminum paste with an electroless nickel deposit solution to coat the aluminum paste with a nickel-phosphorus layer.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: December 1, 2015
    Assignee: OMG Electronic Chemicals, Inc.
    Inventors: Richard Bellemare, Denis Morrissey, Anthony Piano
  • Patent number: 9190283
    Abstract: The present invention relates to a kit intended for the deposition of nickel or cobalt in the cavities of a semiconductor substrate intended to form through-silicon vias (TSV) for making interconnections in integrated circuits in three dimensions. The invention also relates to a method of metallization of the insulating surface of such a substrate which comprises contacting the surface with a liquid aqueous solution containing: at least one metal salt of nickel or cobalt; at least one reducing agent; at least one polymer bearing amine functions, and at least one agent stabilizing the metal ions. The step coverage of the layer of nickel or cobalt obtained can be greater than 80%, which facilitates subsequent filling of the vias with copper by electrodeposition.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: November 17, 2015
    Assignee: ALCHIMER
    Inventors: Vincent Mevellec, Dominique Suhr
  • Patent number: 9147739
    Abstract: Disclosed herein are methods for forming polysilicon in a trench. The sacrificial layer having a high etching rate is applied on the surface of polysilicon after polysilicon is formed on the surface of the substrate and in the trench. The sacrificial layer can provide a flat surface. With the sacrificial layer as a sacrificial mask layer, polysilicon can be etched as having a flat surface. The present disclosure avoids using the CMP process, simplifies the manufacturing process, and reduces the production cost. Moreover, the oxide layer formed thereafter can meet the requirement of current applications.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: September 29, 2015
    Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd.
    Inventor: Liang Tong
  • Patent number: 9123727
    Abstract: An airgap interconnect structure with hood layer and methods for forming such an airgap interconnect structure are disclosed. A substrate having a dielectric layer with a plurality of interconnects formed therein is provided. Each interconnect is encapsulated by a barrier layer. A hardmask is formed on the dielectric layer and patterned to expose the dielectric layer between adjacent interconnects where an airgap is desired. The dielectric layer is etched to form a trench, wherein the etching process additionally etches at least a portion of the barrier layer to expose a portion of the side surface of each adjacent copper interconnect. A hood layer is electrolessly plated onto an exposed portion of the top surface and the exposed portion of the side surface to reseal the interconnect. A gap-sealing dielectric layer is formed over the device, sealing the trench to form an airgap.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventor: Kevin Fischer
  • Patent number: 9040346
    Abstract: In one embodiment, a semiconductor package includes a semiconductor chip having a first contact region on a first major surface and a second contact region on an opposite second major surface. The semiconductor chip is configured to regulate flow of a current from the first contact region to the second contact region. An encapsulant is disposed at the semiconductor chip. A first contact plug is disposed within the encapsulant and coupled to the first contact region. A second side conductive layer is disposed under the second major surface and coupled to the second contact region. A through via is disposed within the encapsulant and coupled to the second side conductive layer. The first contact plug and the through via form terminals above the first major surface for contacting the semiconductor package.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ivan Nikitin, Edward Fuergut
  • Publication number: 20150140816
    Abstract: Catalytic metal nanoparticles can be attached on a base. A pre-treatment method for plating includes a catalytic particle-containing film forming process of forming a catalytic particle-containing film on a surface of a substrate by supplying, onto the substrate, a catalytic particle solution which is prepared by dispersing the catalytic metal nanoparticles and a dispersing agent in a solvent containing water; a first heating process of removing moisture contained at least in the catalytic particle-containing film by heating the substrate to a first temperature; and a second heating process of polymerizing the dispersing agent to have a sheet shape by heating the substrate to a second temperature higher than the first temperature after the first heating process and fixing the catalytic metal nanoparticles on a base layer by covering the catalytic metal nanoparticles with the sheet-shaped dispersing agent.
    Type: Application
    Filed: November 20, 2014
    Publication date: May 21, 2015
    Inventors: Takashi Tanaka, Nobutaka Mizutani, Yusuke Saito, Mitsuaki Iwashita
  • Patent number: 9018050
    Abstract: A rolled-up transmission line structure for a radiofrequency integrated circuit (RFIC) comprises a multilayer sheet in a rolled configuration comprising multiple turns about a longitudinal axis, where the multilayer sheet comprises a conductive pattern layer on a strain-relieved layer. The conductive pattern layer comprises a first conductive film and a second conductive film separated from the first conductive film in a rolling direction. In the rolled configuration, the first conductive film surrounds the longitudinal axis, and the second conductive film surrounds the first conductive film. The first conductive film serves as a signal line and the second conductive film serves as a conductive shield for the rolled-up transmission line structure.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: April 28, 2015
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Wen Huang
  • Patent number: 9006097
    Abstract: A method of forming a bump structure includes providing a semiconductor substrate and forming an under-bump-metallurgy (UBM) layer on the semiconductor substrate. The method further includes forming a mask layer on the UBM layer, wherein the mask layer has an opening exposing a portion of the UBM layer. The method further includes forming a copper layer in the opening of the mask layer and removing a portion of the mask layer to form a space between the copper layer and the mask layer. The method further includes performing an electrolytic process to fill the space with a metal layer and removing the mask layer.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsiung Lu, Ming-Da Cheng, Chih-Wei Lin, Jacky Chang, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20150048510
    Abstract: A semiconductor device includes a semiconductor substrate and a metal film formed on the semiconductor substrate. The metal film includes a Ni base and a material having condensation energy higher than that of Ni. In a method of manufacturing a semiconductor device, a semiconductor substrate and a target, which is formed by melting P in Ni, are prepared, and sputtering is performed with the target while a portion of the semiconductor substrate where the metal film is to be formed is heated to a temperature of from 280° C. inclusive to 870° C. inclusive.
    Type: Application
    Filed: April 22, 2013
    Publication date: February 19, 2015
    Inventors: Manabu Tomisaka, Yoshifumi Okabe, Mikimasa Suzuki
  • Patent number: 8956918
    Abstract: A method for manufacturing a chip arrangement in accordance with various embodiments may include: placing a chip on a carrier within an opening of a metal structure disposed over the carrier; fixing the chip to the metal structure; removing the carrier to thereby expose at least one contact of the chip; and forming an electrically conductive connection between the at least one contact of the chip and the metal structure.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: February 17, 2015
    Assignee: Infineon Technologies AG
    Inventor: Petteri Palm
  • Patent number: 8956975
    Abstract: A method for forming magnetic conductors includes forming a metal structure on a substrate. Plating surfaces are prepared on the metal structure for electroless plating by at least one of: masking surfaces of the metal structure to prevent electroless plating on masked surfaces and/or activating a surface of the metal structure. Magnetic material is electrolessly plated directly on the plating surfaces to form a metal and magnetic material structure.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: February 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: William J. Gallagher, Eugene J. O'Sullivan, Naigang Wang
  • Patent number: 8946087
    Abstract: A method for providing metal filled features in a layer is provided. A metal seed layer is deposited on tops and bottoms of the features. Metal seed layer on tops of the features and overhangs is removed without removing metal seed layer on bottoms of features. An electroless deposition of metal is provided to fill the features, wherein the electroless deposition first deposits on the metal seed layer on bottoms of the features.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: February 3, 2015
    Assignee: Lam Research Corporation
    Inventor: Praveen Reddy Nalla
  • Patent number: 8946088
    Abstract: A method of forming a metal layer on an electrically insulating substrate comprises depositing a photocatalyst layer onto the substrate and depositing a mask layer comprising voids on the substrate, such as a layer of latex microparticles with voids between them, to give an open pore structure to the mask. An electroless plating solution is then provided on the photocatalyst layer, and the photocatalyst layer and electroless plating solution are illuminated with actinic radiation whereby deposition of metal from the electroless plating solution to form a metal layer on the photocatalyst layer is initiated whereby the metal deposits in the voids of the mask layer. The mask layer is subsequently removed to leave a porous metal layer on the substrate. The method allows for deposition of porous metal films with controlled thickness and excellent adhesion onto electrically insulating substrates. The method is suitable for providing metal layers with controlled, regular porosity.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: February 3, 2015
    Assignee: Lancaster University Business Enterprises Limited
    Inventors: Colin Boxall, Michael Bromley
  • Patent number: 8911551
    Abstract: An electroless plating apparatus and method designed specifically for plating at least one semiconductor wafer are disclosed. The apparatus comprises a container, a wafer holder, an electrolyte supplying unit, and an ultrasonic-vibration unit. The container is provided with at least an inlet and used for containing electrolyte. The wafer holder is provided within the container. The electrolyte supplying unit is used to supply the electrolyte into the container via the inlet. The ultrasonic-vibration unit consisting of at least one frequency ultrasonic transducer is disposed in the container for producing a uniform flow of electrolyte in the container. Thereby, the wafers can be uniformly plated, especially for wafers with fine via-holes or trench structures.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: December 16, 2014
    Assignee: Win Semiconductor Corp.
    Inventors: Jason Chen, Nakano Liu, Winson Shao, Wen Chu, Chang-Hwang Hua
  • Patent number: 8900998
    Abstract: A plating bath for electroless deposition of gold and gold alloy layers on such silicon-based substrates, includes Na(AuCl4) and/or other gold (III) chloride salts as a gold ion source. The bath is formed as a binary bath solution formed from mixing first and second bath components. The first bath component includes gold salts in concentrations up to 40 g/L, boric acid, in amounts of up to 30 g/L, and a metal hydroxide in amounts up to 20 g/L. The second bath component includes an acid salt, in amounts up to 25 g/L, sodium thiosulfate in amounts up to 30 g/L, and suitable acid, such as boric acid in amounts up to 20 g/L.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: December 2, 2014
    Assignee: University of Windsor
    Inventors: Mordechay Schlesinger, Robert Andrew Petro
  • Patent number: 8895441
    Abstract: One aspect of the present invention includes a method of fabricating an electronic device. According to one embodiment, the method comprises providing a substrate having dielectric oxide surface areas adjacent to electrically conductive surface areas, chemically bonding an anchor compound with the dielectric oxide surface areas so as to form an anchor layer, initiating the growth of a metal using the electrically conductive surface areas and growing the metal so that the anchor layer also bonds with the metal. The anchor compound has at least one functional group capable of forming a chemical bond with the oxide surface and has at least one functional group capable of forming a chemical bond with the metal. Another aspect of the present invention is an electronic device. A third aspect of the present invention is a solution comprising the anchor compound.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: November 25, 2014
    Assignee: Lam Research Corporation
    Inventor: Artur Kolics
  • Patent number: 8889479
    Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: November 18, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Nitin Kumar, Tony P. Chiang, Chi-I Lang, Prashant B. Phatak, Jinhong Tong
  • Patent number: 8883641
    Abstract: The present invention relates to a solution and a method for activating the oxidized surface of a substrate, in particular of a semiconducting substrate, for its subsequent coating by a metal layer deposited by the electroless method. According to the invention, this composition contains: A) an activator consisting of one or more palladium complexes; B) a bifunctional organic binder consisting one or more organosilane complexes; C) a solvent system consisting one or more solvents for solubilizing the said activator and the said binder.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: November 11, 2014
    Assignee: Alchimer
    Inventors: Vincent Mevellec, Dominique Suhr
  • Patent number: 8872297
    Abstract: A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a heavily doped N-type region and a heavily doped P-type region adjacent to one another. An exterior surface of the substrate has a topography that includes a light-transparent region in which light, from a light source, is able to reach a surface of the substrate. An application of light onto the light transparent region is sufficient to cause a voltage potential to form across a junction of the heavily doped regions. The substrate section may further comprise one or more electrical contacts, positioned on the substrate section to conduct current, resulting from the voltage potential created with application of light onto the light transparent region, to a circuit on the semiconductor substrate.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 28, 2014
    Assignee: Tau-Metrix, Inc.
    Inventors: Gary Steinbrueck, James S. Vickers, Mario M. Pelella, Majid Aghababazadeh, Nadar Pakdaman
  • Patent number: 8865518
    Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: October 21, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Nitin Kumar, Tony P. Chiang, Chi-I Lang, Zhi-Wen Wen Sun, Jihong Tong
  • Patent number: 8846529
    Abstract: A method for forming an on-chip magnetic structure includes forming a seed layer over a substrate of a semiconductor chip. The seed layer is patterned to provide a plating location. A cobalt based alloy is electrolessly plated at the plating location to form an inductive structure on the semiconductor chip.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: William J. Gallagher, Eugene J. O'Sullivan, Naigang Wang
  • Patent number: 8846451
    Abstract: Methods for depositing metal in high aspect ratio features formed on a substrate are provided herein. In some embodiments, a method includes applying first RF power at VHF frequency to target comprising metal disposed above substrate to form plasma, applying DC power to target to direct plasma towards target, sputtering metal atoms from target using plasma while maintaining pressure in PVD chamber sufficient to ionize predominant portion of metal atoms, depositing first plurality of metal atoms on bottom surface of opening and on first surface of substrate, applying second RF power to redistribute at least some of first plurality from bottom surface to lower portion of sidewalls of the opening, and depositing second plurality of metal atoms on upper portion of sidewalls by reducing amount of ionized metal atoms in PVD chamber, wherein first and second pluralities form a first layer deposited on substantially all surfaces of opening.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: September 30, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Alan Ritchie, Karl Brown, John Pipitone
  • Patent number: 8841766
    Abstract: Sidewall protection processes are provided for Cu pillar bump technology, in which a protection structure on the sidewalls of the Cu pillar bump is formed of at least one of non-metal material layers, for example a dielectric material layer, a polymer material layer, or combinations thereof.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: September 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Yi-Wen Wu, Chun-Chieh Wang, Chung-Shi Liu
  • Patent number: 8835248
    Abstract: Techniques for fabricating metal lines in semiconductor systems are disclosed. The metal may be tungsten. A hybrid Chemical Vapor Deposition (CVD)/Physical Vapor Deposition (PVD) process may be used. A layer of tungsten may be formed using CVD. This CVD layer may be formed over a barrier layer, such as, but not limited to, TiN or WN. This CVD layer may completely fill some feature such as a trench or via. Then, a layer of tungsten may be formed over the CVD layer using PVD. The layers of tungsten may then be etched to form a wire or line. Techniques for forming metal wires using a hybrid CVD/PVD process may provide for low resistivity with a barrier metal, low surface roughness, and good gap filling.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: September 16, 2014
    Assignee: SanDisk Technologies Inc.
    Inventor: Naoki Takeguchi
  • Patent number: 8828863
    Abstract: A method for providing metal filled features in a layer is provided. A nonconformal metal seed layer is deposited on tops, sidewalls, and bottoms of the features, wherein more seed layer is deposited on tops and bottoms of features than sidewalls. The metal seed layer are etched back on tops, sidewalls, and bottoms of the features, wherein some metal seed layer remains on tops and bottoms of the features. Deposition on the seed layer on tops of the features is suppressed. An electroless “bottom up” deposition of metal is provided to fill the features.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: September 9, 2014
    Assignee: Lam Research Corporation
    Inventors: William T. Lee, Xiaomin Bin
  • Patent number: 8809124
    Abstract: A structure includes a hybrid substrate for supporting a semiconductive device that includes a bumpless build-up layer in which the semiconductive device is embedded and a laminated-core structure. The bumpless build-up layer and the laminated-core structure are rendered an integral apparatus by a reinforcement plating that connects to a plated through hole in the laminated-core structure and to a subsequent bond pad of the bumpless build-up layer structure.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: August 19, 2014
    Assignee: Intel Corporation
    Inventors: Mathew J Manusharow, Mark S Hlad, Ravi K Nalla
  • Patent number: 8772155
    Abstract: High aspect ratio trenches may be filled with metal that grows more from the bottom than the top of the trench. As a result, the tendency to form seams or to close off the trench at the top during filling may be reduced in some embodiments. Material that encourages the growth of metal may be formed in the trench at the bottom, while leaving the region of the trench near the top free of such material to encourage growth upwardly from the bottom.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Shai Haimson, Avi Rozenblat, Dror Horvitz, Maor Rotlain, Rotem Drori
  • Patent number: 8766441
    Abstract: Solder on slot connections in package on package structures. An apparatus includes a substrate having a front side surface and a back side surface; a first passivation layer disposed over at least one of the front side and back side surfaces; at least one via opening formed in the first passivation layer; a conductor layer disposed over the first passivation layer, coupled to the at least one via and forming a conductive trace on the surface of the first passivation layer; a second passivation layer formed over the conductor layer; and at least one slot opening formed in the second passivation layer and exposing a portion of the conductive trace for receiving a solder connector. In additional embodiments the substrate may be a semiconductor wafer. Methods for forming the structures are disclosed.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Sen Chang, Ching-Wen Hsiao, Chen-Shien Chen
  • Patent number: 8748313
    Abstract: A method for making a mask for semiconductor manufacturing. The method includes providing a base layer, forming a conductive layer on the base layer, and forming a photoresist layer on the conductive layer. Additionally, the method includes exposing selectively the photoresist layer to an energy illumination, developing the photoresist layer by removing a first portion of the photoresist layer, and depositing a metal layer by an electroforming process. The electroforming process includes submerging the conductive layer into a chemical bath, and applying a deposition voltage across a negative electrode and a positive electrode. Moreover, the method includes removing a second portion of the photoresist layer, and removing a first portion of the conductive layer.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: June 10, 2014
    Assignees: Semiconductor Manufaturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Hsin Chin Chen
  • Patent number: 8741773
    Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Asa Frye, Andrew Simon
  • Patent number: 8735302
    Abstract: Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: May 27, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Amol Joshi, John Foster, Zhendong Hong, Olov Karlsson, Bei Li, Usha Raghuram
  • Publication number: 20140141609
    Abstract: A plating bath for electroless deposition of gold and gold alloy layers on such silicon-based substrates, includes Na(AuCl4) and/or other gold (III) chloride salts as a gold ion source. The bath is formed as a binary bath solution formed from mixing first and second bath components. The first bath component includes gold salts in concentrations up to 40 g/L, boric acid, in amounts of up to 30 g/L, and a metal hydroxide in amounts up to 20 g/L. The second bath component includes an acid salt, in amounts up to 25 g/L, sodium thiosulfate in amounts up to 30 g/L, and suitable acid, such as boric acid in amounts up to 20 g/L.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 22, 2014
    Applicant: UNIVERSITY OF WINDSOR
    Inventors: Mordechay SCHLESINGER, Robert Andrew PETRO
  • Patent number: 8728939
    Abstract: A single-crystal substrate is placed on a supporting table while maintaining crystalline orientation of the single-crystal substrate. The single-crystal substrate has contacting regions on a periphery of an upper surface of the single-crystal substrate. Linear contacting surfaces of contacting pins are placed in contact with the contacting regions of the single-crystal substrate placed on the supporting table. Longitudinal directions on the contacting surfaces of all the contacting pins are not parallel to intersecting lines of the upper surface of the single-crystal substrate and cleaved surfaces of the single-crystal substrate.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: May 20, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuhiro Maeda, Koichiro Nishizawa
  • Patent number: 8728876
    Abstract: The invention prevents a conductive fuse blown out by laser trimming from reconnecting by a plating electrode in a plating process and prevents a plating solution etc from entering a fuse blowout portion. On a semiconductor substrate of a multilayered wiring structure including a fuse blowout groove formed by blowing out a conductive fuse by laser trimming in a trimming element forming region, a second protection layer is formed so as to cover the trimming element forming region and then a plating electrode is formed on an draw-out pad electrode made of a topmost metal wiring. A third protection layer is then formed so as to cover the semiconductor substrate including the second protection layer and have an opening on the plating electrode.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: May 20, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Eiji Kurose
  • Patent number: 8722539
    Abstract: A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: May 13, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Katie Qun Wang, Mark J. Willey
  • Patent number: 8709948
    Abstract: Apparatus and methods for filling through silicon vias (TSV's) with copper having an intervening tungsten layer between the copper plug and the silicon are disclosed. Methods are useful for Damascene processing, with or without a TSV feature. The tungsten layer serves as a diffusion barrier, a seed layer for copper electrofill and a means of reducing CTE-induced stresses between copper and silicon. Adhesion of the tungsten layer to the silicon and of the copper layer to the tungsten is described.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: April 29, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Michal Danek, Tom Mountsier, Jonathan Reid, Juwen Gao, Aaron Fellis