Abstract: A method for packaging a light emitting element includes a step of providing a carrier formed with an anode electrode and a cathode electrode, a step of providing a light emitting object by utilizing a light emitting diode chip having a positive and negative electrodes, a step of directly contacting the carrier and the light emitting diode chip to establish electrical communication among the anode and cathode electrodes and the positive and negative electrodes, and a step of firmly bonding the carrier and the light emitting diode chip by which to simplify assembling procedure and further to reduce manufacturing cost and enhance production efficiency.

Abstract: The present invention includes: a pre-step of preparing a substrate having on its surface a hydrophilic region that is surrounded by a water-repellent region and provided with a hydrophilic electrode; a first step of applying an electroless plating solution in which a metal compound is dispersed in water to the substrate to dispose an electroless plating solution in the hydrophilic region; a second step of applying an electronic device-dispersed liquid in which an electronic device having a device electrode is dispersed in a first liquid to the substrate to move the electronic device from the first liquid to the electroless plating solution so as to bring the device electrode into contact with the hydrophilic electrode; a third step of coating a surface of the substrate with a second liquid before the water contained in the electroless plating solution volatilizes completely to cause a plating reaction between the hydrophilic electrode and the device electrode and to connect electrically the hydrophilic elect

Abstract: A conformal metallic layer is applied to a selected region of a substrate by forming a pattern of electrically conductive lines on the substrate, placing a bead of a selected metal on the substrate at an edge of the region selected for coating, and passing an electric current through the bead and through conductive lines that extend over the region of the substrate selected for coating with the electric current having a current density sufficient to melt the bead so that metallic material therefrom flows over the conductive lines to form the coating. A pair of electrically conductive connectors is placed in contact with the electrically conductive lines, and an electric power supply is connected to the pair of electrically conductive connectors such that electric current passes through the bead, melts the bead to form a liquid metal, and carries the liquid metal in a continuous stream along the conductive lines, coating the conductive lines conformally in the process.

Abstract: A method forms a micropad to an external contact of a first semiconductor device. A stud of copper is formed over the external contact. The stud extends above a surface of the first semiconductor device. The stud of copper is immersed in a solution of tin. The tin replaces at least 95 percent of the copper of the stud and preferably more than 99 percent. The result is a tin micropad that has less than 5 percent copper by weight. Since the micropad is substantially pure tin, intermetallic bonds will not form during the time while the micropads of the first semiconductor device are not bonded. Smaller micropad dimensions result since intermetallic bonds do not form. When the first semiconductor device is bonded to an overlying second semiconductor device, the bond dimensions do not significantly increase the height of stacked chips.

Abstract: A method of manufacturing a semiconductor device on a semiconductor substrate, includes the steps of forming a first metal film on a front surface of the semiconductor substrate; forming a second metal film on the surface of the first metal film; activating a surface of the second metal film to provide an activated surface; and forming a plated film on the activated surface by a wet plating method in a plating bath that includes a reducing agent that is oxidized during plating and that has a rate of oxidation, wherein the second metal film is a metal film mainly composed of a first substance that enhances the rate of oxidation of the reducing agent in the plating bath. Wet plating is preferably an electroless process.

Abstract: There is provided a bank structure which partitions off a pattern formation region in which a functional liquid is to be disposed and flow. The pattern formation region includes a first pattern formation region, and a second pattern formation region which is continuously connected to the first pattern formation region and which has a larger width than the first pattern formation region. The second pattern formation region is provided with at least one partition bank which partitions off the second pattern formation region to regulate the flow direction of the functional liquid. A partition width substantially orthogonal to the flow direction of the functional liquid which is regulated by the partition bank is less than ±20% of the width of the first pattern formation region.

Abstract: A substrate processing apparatus, including: a reaction container in which a substrate is processed; a seal cap, brought into contact with one end in an opening side of the reaction container via a first sealing member and a second sealing member so as to seal the opening of the reaction container air-tightly; a first gas channel, formed in a region between the first sealing member and the second sealing member in a state where the seal cap is in contact with the reaction container; a second gas channel, provided to the seal cap and through which the first gas channel is in communication with an inside of the reaction container; a first gas supply port that is provided to the reaction container and supplies a first gas to the first gas channel; and a second gas supply port that is provided to the reaction container and supplies a second gas into the reaction container, wherein a front end opening of the first gas supply port opening to the first gas channel, and a base opening of the second gas channel openin

Abstract: One embodiment of the present subject matter includes a system which includes a tank, a conduit is adapted to carry a recirculating supply of fluid from the tank and into the tank, and at least one injector adapted to dispense fluid from the recirculating supply of fluid into a chamber.

Abstract: A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.

Abstract: The present invention relates to a method for manufacturing a backside contact of a semiconductor component, in particular, of a solar cell, comprising a metallic layer on the backside of a substrate in a vacuum treatment chamber, and the use of a vacuum treatment system for performing said method. Through this method and its use, in particular silicon based solar cells, can be provided with a back contact in a simple manner in a continuous process sequence, wherein the process sequence can be provided particularly efficient and economical, since no handling systems for rotating the substrate are required, and in particular silk screening steps can be dispensed with.

Abstract: Structures are provided that include a conducting layer disposed on a layered arrangement of a diffusion barrier layer and a seed layer in an integrated circuit. Apparatus and systems having such structures and methods of forming these structures for apparatus and systems are disclosed.

Abstract: Embodiments of apparatus and methods for forming dual metal interconnects are described herein. Other embodiments may be described and claimed.

Abstract: An electroless plating composition comprising succinic acid, potassium carbonate, a source of cobalt metal ions, a reducing agent, and water is provided. An optional buffering agent may also be included in the composition. The composition may be used to deposit cobalt metal in or on semiconductor substrate surfaces including vias, trenches, and interconnects.

Abstract: The manufacturing method of the present invention includes steps of selectively forming a photocatalyst material or a material including an amino group by discharging a composition including the photocatalyst material or the material including an amino group; immersing the photocatalyst material or the material including an amino group in a solution including a plating catalyst material so as to adsorb or deposit the plating catalyst material onto the photocatalyst material or the material including an amino group; and immersing the plating catalyst material in a plating solution including a metal material so as to form a metal film on a surface of the photocatalyst material or the material including an amino group adsorbing or depositing the plating catalyst material, thereby manufacturing a semiconductor device. The pH of the solution including the plating catalyst material is adjusted in a range of 3 to 6.

Abstract: Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up.

Abstract: A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.

Abstract: Preferred embodiments provide a method for forming at least one catalyst nanoparticle on at least one sidewall of a three-dimensional structure on a main surface of a substrate, the main surface lying in a plane and the sidewall of the three-dimensional structure lying in a plane substantially perpendicular to the plane of the main surface of the substrate. The method comprises obtaining a three-dimensional structure on the main surface, the three-dimensional structure comprising catalyst nanoparticles embedded in a non-catalytic matrix and selectively removing at least part of the non-catalytic matrix at the sidewalls of the three-dimensional structure to thereby expose at least one catalyst nanoparticle.

Abstract: A method of plating a plurality of semiconductor devices includes: applying an electrical power source to an anode terminal and a cathode terminal; placing the plurality of semiconductor devices on a non-conductive platform in a plating solution; moving conductive parts across surfaces of the semiconductor devices to be plated, wherein the conductive parts electrically connect the surfaces of the semiconductor devices to the cathode; and wherein plating particles connected to the anode terminal move to and plate the surfaces of the semiconductor devices.

Abstract: A method for integrating a Ru layer with bulk Cu in semiconductor manufacturing. The method includes depositing a Ru layer onto a substrate in a chemical vapor deposition process, modifying the deposited Ru layer by oxidation, or nitridation, or a combination thereof, depositing an ultra thin Cu layer onto the modified Ru layer, and plating a Cu layer onto the ultra thin Cu layer.

Abstract: A structure has at least one structure component formed of a first material residing on a substrate, such that the structure is out of a plane of the substrate. A first coating of a second material then coats the structure. A second coating of a non-oxidizing material coats the structure at a thickness less than a thickness of the second material.

Abstract: Embodiments of the present invention provide methods of electroprocessing a substrate. One embodiment of the present invention provides a method comprises pressing a substrate against a polishing pad with a force less than about two pounds per square inch, the substrate contacting a first electrode of the polishing pad, applying an electrical bias to the substrate with the first electrode relative to a second electrode of the polishing pad, wherein the second electrode is disposed below the second electrode, and biasing a third electrode disposed in the polishing pad radially outward of the second electrode.

Abstract: A structure and method of fabricating a dual damascene interconnect structure, the structure including a dual damascene wire in a dielectric layer, the dual damascene wires extending a distance into the dielectric layer less than the thickness of the dielectric layer and dual damascene via bars integral with and extending from bottom surfaces of the dual damascene wires to a bottom surface of the dielectric layer.

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Abstract: Solutions comprising: (i) at least one organic semiconductor, (ii) at least one organic solvent A having a boiling point, and (iii) at least one organic solvent B having a boiling point; wherein the at least one organic semiconductor comprises at least one high molecular weight component, wherein the at least one organic solvent A is a good solvent for the at least one organic semiconductor, wherein the at least one organic solvent B is a poor solvent for the at least one organic semiconductor; and wherein the boiling point of the at least one solvent A is greater than the boiling point of the at least one solvent B; and the use of such solutions in processes for forming organic semiconductor layers on substrates and devices formed by such processes.

Abstract: Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a first (lower) electrode, sputter depositing a thin diffusion layer of a conductive material over the chalcogenide material, diffusing metal from the diffusion layer into the chalcogenide material resulting in a metal-comprising resistance variable material, and then plating a conductive material to a desired thickness to form a second (upper) electrode.

Abstract: A semiconductor device has interconnects protected with an alloy film having a minimum thickness necessary for producing the effect of preventing diffusion of oxygen, copper, etc., formed more uniformly over an entire surface of a substrate with less dependency to the interconnect pattern of the substrate. The semiconductor device includes, embedded interconnects, formed by filling an interconnect material into interconnect recesses formed in an electric insulator on a substrate, and an alloy film, containing 1 to 9 atomic % of tungsten or molybdenum and 3 to 12 atomic % of phosphorus or boron, formed by electroless plating on at least part of the embedded interconnects.

Abstract: The present disclosure relates to a display device comprising an insulating substrate; a source electrode and a drain electrode on the insulating substrate and separated by a channel area; an organic semiconductor layer formed in the channel area and on at least a portion of the source electrode and at least a portion of the drain electrode; and a self-assembly monolayer having a first portion disposed between the organic semiconductor layer and the source electrode and a second portion disposed between the organic semiconductor layer and the drain electrode to reduce contact resistance between the electrodes and the organic semiconductor layer. Thus, embodiments of present invention provide a display device including a TFT that is enhanced in its performance.

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Abstract: Embodiments of the current invention describe a method of plating platinum selectively on a copper film using a self-initiated electroless process. In particular, platinum films are plated onto very thin copper films having a thickness of less than 300 angstroms. The electroless plating solution and the resulting structure are also described. This process has applications in the semiconductor processing of logic devices, memory devices, and photovoltaic devices.

Abstract: Embodiments as described herein provide methods for depositing a material on a substrate during electroless deposition processes, as well as compositions of the electroless deposition solutions. In one embodiment, the substrate contains a contact aperture having an exposed silicon contact surface. In another embodiment, the substrate contains a contact aperture having an exposed silicide contact surface. The apertures are filled with a metal contact material by exposing the substrate to an electroless deposition process. The metal contact material may contain a cobalt material, a nickel material, or alloys thereof. Prior to filling the apertures, the substrate may be exposed to a variety of pretreatment processes, such as preclean processes and activations processes. A preclean process may remove organic residues, native oxides, and other contaminants during a wet clean process or a plasma etch process. Embodiments of the process also provide the deposition of additional layers, such as a capping layer.

Abstract: To suppress deterioration in reliability of wiring and to reduce effective dielectric constant of wiring. In a semiconductor device, copper-containing wirings are covered by barrier insulating films, and the barrier insulating films contain a component of an organic silica containing unsaturated hydrocarbon and amorphous carbon. The copper-containing wirings are covered by the barrier insulating films that contain a component that is in an organic silica structure containing unsaturated hydrocarbon and amorphous carbon. Accordingly, inter-wiring capacitance is reduced without deteriorating reliability of the copper-containing wiring, thereby realizing a high-speed LSI with low power consumption.

Abstract: A semiconductor device is manufactured by forming a gate electrode layer over a substrate having a light transmitting property; forming a gate insulating layer over the gate electrode layer; forming a photocatalyst material over the gate insulating layer; immersing the photocatalyst material in a solution containing a plating catalyst material and selectively exposing the photocatalyst material to light transmitted through the substrate in the solution containing the plating catalyst material with the use of the gate electrode layer as a mask to adsorb or deposit the plating catalyst material onto the light-exposed photocatalyst material; immersing the plating catalyst material in a plating solution containing a metal material to form a source electrode layer and a drain electrode layer on the surface of the photocatalyst material adsorbing or depositing the plating catalyst material; and forming a semiconductor layer over the source electrode layer and the drain electrode layer.

Abstract: A method and apparatus for electroprocessing a substrate is provided. In one embodiment, a method for electroprocessing a substrate includes the steps of biasing a first electrode to establish a first electroprocessing zone between the electrode and the substrate, and biasing a second electrode disposed radially outward of substrate with a polarity opposite the bias applied tot he first electrode.

Abstract: A film formation method is provided which includes positioning an object within an electroless deposition apparatus having means for instantaneous temperature control of the object and electrolessly depositing a material upon the object. More specifically, the method includes instantaneously changing the temperature of the object by the means of instantaneous control at one or more predetermined times during the step of electrolessly depositing the material, wherein the predetermined times correspond to different film-growth stages of the material.

Abstract: A metal is deposited onto a surface electrochemically using a deposition solution including a metal salt. In making a composite nanostructure, the solution further includes an enhancer that promotes electrochemical deposition of the metal on the nanostructure. In a method of forming catalyzing nanoparticles, the metal preferentially deposits on a selected location of a surface that is exposed through a mask layer instead of on unexposed surfaces. A composite nanostructure apparatus includes an array of nanowires and the metal deposited on at least some nanowire surfaces. Some of the nanowires are heterogeneous, branched and include different adjacent axial segments with controlled axial lengths. In some deposition solutions, the enhancer one or both of controls oxide formation on the surface and causes metal nanocrystal formation. The deposition solution further includes a solvent that carries the metal salt and the enhancer.

Abstract: A method of forming a wafer level package includes attaching a laser-activated dielectric material to an integrated circuit substrate to form an assembly, the integrated circuit substrate including a plurality of electronic components having terminals on first surfaces thereof. The laser-activated dielectric material is laser activated and ablated with a laser to form laser-ablated artifacts in the laser-activated dielectric material and simultaneously to form an electrically conductive laser-activated layer lining the laser-ablated artifacts. The laser-ablated artifacts are filled using an electroless plating process in which an electrically conductive filler material is selectively plated on the laser-activated layer to form an embedded circuit pattern within the laser-activated dielectric material.

Abstract: Methods of fabricating interconnect structures utilizing barrier material layers formed with an electroless deposition technique utilizing a coupling agent complexed with a catalytic metal and structures formed thereby. The fabrication fundamentally comprises providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, bonding the coupling agent to the dielectric material within the opening, and electrolessly depositing the barrier material layer, wherein the electrolessly deposited barrier material layer material adheres to the catalytic metal of the coupling agent.

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

Abstract: Many electronic entities such as integrated circuits and discrete power devices have contact pads formed from successively deposited layers of nickel and a second metal such as gold. The resulting pad structure is used to make external electrical connection such as solder connection. Problems associated with failure of such connections are avoidable by inspecting the surface of the nickel layer for excessive small particle formation.

Abstract: A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer, which only wraps the patterned semiconductor layer; forming a second patterned conducting layer on the barrier layer and above the source and the drain. In the display element manufactured by the method, the barrier layer only wraps the patterned semiconductor layer.

Abstract: A method of filling a conductive material in a three dimensional integration feature formed on a surface of a wafer is disclosed. The feature is optionally lined with dielectric and/or adhesion/barrier layers and then filled with a liquid mixture containing conductive precursor, such as a solution with dissolved ruthenium precursor or a dispersion or suspension with conductive particles (e.g., gold, silver, copper), and the substrate is rotated while the mixture is on its surface. Then, the liquid carrier is dried from the feature, leaving a conductive layer in the feature. These two steps are optionally repeated until the feature is filled up with the conductor. Then, the conductor is annealed in the feature, thereby forming a dense conductive plug in the feature.

Abstract: Methods are provided for reducing the aspect ratio of contacts to bit lines in fabricating an IC including logic and memory. The method includes the steps of forming a first group of device regions to be contacted by a first level of metal and a second group of memory bit lines to be contacted by a second level of metal, the first level separated from the second level by at least one layer of dielectric material. Conductive material is plated by electroless plating on the device regions and bit lines and first and second conductive plugs are formed overlying the conductive material. The first conductive plugs are contacted by the first level of metal and the second conductive plugs are contacted by the second level of metal. The thickness of the plated conductive material provides a self aligned process for reducing the aspect ratio of the conductive plugs.

Abstract: A method of forming a metal line in a semiconductor device including forming a first insulation layer and a first etch stop layer on a conductive layer, and forming a first photosensitive layer pattern on the first etch stop layer; forming a first opening by etching the first etch stop layer; forming a second insulation layer and a second etch stop layer on the first insulation layer and the first etch stop layer, and forming a second photosensitive layer pattern on the second etch stop layer; forming a second opening by etching the second etch stop layer; simultaneously forming an inter-connection groove and a via hole by etching the first insulation layer and the second insulation layer using the second etch stop layer and the first etch stop layer as a mask; and forming a metal line by filling the inter-connection groove and the via hole with conductive materials.

Abstract: Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions.

Abstract: Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions.

Abstract: Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions.

Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.

Abstract: An electroless plating system includes a plating solution, and controlling reducing agents in the plating solution for deposition over outlier features smaller than about five hundred nanometers and isolated by about one thousand nanometers.

Abstract: A method for plating a second metal directly to a first metal without utilizing a mask. A semiconductor substrate is provided including at least one metal feature and at least one insulating layer covering the metal feature and the substrate. At least one recess is formed in the at least one insulating layer thereby exposing at least a portion of the metal feature. At least one conductive barrier layer is formed over the insulating layer and the exposed portion of the metal feature. A plating seed layer of a first metal is formed over the at least one barrier layer. A photoresist layer is deposited over the plating seed layer. Portions of the photoresist layer and portions of the plating seed layer outside of the at least one recess are removed. Photoresist remaining in the at least one recess is removed. A second metal is electroplated to the plating seed layer in the recess, using the barrier layer to conduct electrical current.

Abstract: A method for making an integrated circuit device includes forming at least one interconnect structure adjacent a substrate by forming at least one barrier layer, forming a doped copper seed layer on the at least one barrier layer, and forming a copper layer on the doped copper seed layer. The method may further include annealing the integrated circuit device after forming the copper layer to diffuse the dopant from the doped copper seed layer into grain boundaries of the copper layer. The doped copper seed layer may include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant to provide the enhanced electromigration resistance. Forming the copper layer may comprise plating the copper layer. In addition, forming the copper layer may comprise forming the copper layer to include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant.