Abstract: A semiconductor package and a method for manufacturing the same capable of supplying power easily without an increase in the number of pads for power supply. The semiconductor package includes a semiconductor chip having a plurality of pads including pads for power supply disposed in a center portion and an internal wiring disposed to be exposed to outside; an insulating film formed on the semiconductor to expose the pads for power supply and the internal wirings; and re-distribution lines formed on the insulating film to connect between the exposed portions of the pads for power supply and the internal wiring.

Abstract: A method for forming a semiconductor chip or wafer includes following steps. A semiconductor substrate is provided, and then a polymer layer is deposited over the semiconductor substrate, wherein the polymer layer comprises polyimide. The polymer layer with a temperature profile having a peak temperature between 200 and 320 degrees Celsius. Alternatively, the temperature profile may comprises a period of time with a temperature higher than 320 degree Celsius, wherein the period of time is shorter than 45 minutes.

Abstract: A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is formed and the wafer is then submerged in a solution to electroless plate a blanket conformal copper seed layer. A partial filling of deeper gaps with copper reduces the effective aspect ratios of the deeper gaps to the extent that ECP could be used to complete the copper filling of the gaps without forming pinhole like voids. ECP is then used to complete the copper filling of the gaps. The wafer is annealed and CMP performed to planarize the surface, giving rise to a structure in which the gaps are filled with copper and are separated by the dielectric layer.

Abstract: In electric plating of supplying a current between an anode electrode and a cathode electrode as a plated body immersed in a plating solution thereby forming a plated film comprising a conductor on a surface of the cathode electrode, a preliminary electrolytic electrode that comes in contact with the plating solution before the cathode electrode comes in contact with the plating solution is disposed, and the cathode electrode is brought into contact with the plating solution while supplying a preliminary electrolytic current between the preliminary electrolytic electrode and the anode electrode, whereby a uniform plated film with no voids can be formed while suppressing dissolution of the underlying conductive film in the electric plating treatment.

Abstract: The invention provides a CSP type semiconductor device with high reliability. The semiconductor device includes a pad electrode formed on a semiconductor substrate, a first passivation film covering an end portion of the pad electrode and having a first opening on the pad electrode, a plating layer formed on the pad electrode in the first opening, a second passivation film covering an exposed portion of the pad electrode between an end portion of the first passivation film and the plating layer, covering an end portion of the plating layer, and having a second opening on the plating layer, and a conductive terminal formed on the plating layer in the second opening.

Abstract: A method of forming an EL-Cu enhanced noble metal layer begins with providing a semiconductor substrate in a reaction chamber, wherein the semiconductor substrate includes a trench etched into a dielectric layer. Next, an organometallic precursor containing a noble metal and a reactive gas are pulsed into the reaction chamber proximate to the semiconductor substrate where they react to form a noble metal layer directly on the dielectric layer within the trench. The substrate is then moved into an electroless plating bath and an electroless plating process deposits a copper seed layer onto the noble metal layer. The substrate is then removed from the plating bath.

Abstract: In an enhanced technique for electroless metal deposition, the substrate is heated to or above the operating temperature for the specific plating solution, while the plating solution may be maintained at a non-critical low temperature to substantially prevent spontaneous self-decomposition within the plating tool. Hence, significant advantages with respect to process control and cost of ownership may be achieved.

Abstract: A method for fabricating a recess gate in a semiconductor device is provided. The method includes selectively etching an active region of a substrate to form a recess pattern, performing a post treatment on the recess pattern using a plasma, and forming a gate pattern in the recess pattern.

Abstract: The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing.

Abstract: Techniques to improve characteristics of processed semiconductor substrates are described, including cleaning a substrate using a preclean process, the substrate comprising a dielectric region and a conductive region, introducing a hydroquinone to the substrate after cleaning the substrate using the preclean operation, and forming a capping layer over the conductive region of the substrate after introducing the hydroquinone.

Abstract: A through hole (114) is formed in a wafer (104) comprising a semiconductor substrate (110). A seed layer (610) is sputtered on the bottom surface of the wafer. The seed is not deposited over the through hole's sidewalls adjacent the top surface of the wafer. A conductor (810) is electroplated into the through hole. In another embodiment, a seed is deposited into an opening in a wafer through a dry film resist mask (1110). The dry film resist overhangs the edges of the opening, so the seed is not deposited over the opening's sidewalls adjacent the top surface of the wafer. In another embodiment, a dielectric (120) is formed in an opening in a semiconductor substrate (110) by a non-conformal physical vapor deposition (PVD) process that deposits the dielectric on the sidewalls but not the bottom of the opening. A seed (610) is formed on the bottom by electroless plating. A conductor (810) is electroplated on the seed.

Abstract: A method for manufacturing a wiring substrate by an electroless plating method that precipitates metal without using a plating resist is provided. The method includes the steps of: (a) providing a catalyst layer having a predetermined pattern on a substrate; (b) dipping the substrate in an electroless plating solution to thereby precipitate metal on the catalyst layer to provide a first metal layer; (c) washing a top surface of the substrate with water; and (d) dipping the substrate in an electroless plating solution to thereby precipitate metal on the first metal layer to provide a second metal layer.

Abstract: The present invention relates to a process for selectively coating certain areas of a composite surface with a conductive film, to a process for fabricating interconnects in microelectronics, and to processes and methods for fabricating integrated circuits, and more particularly to the formation of networks of metal interconnects, and also to processes and methods for fabricating microsystems and connectors.

Abstract: By performing an electroless deposition and an electro deposition process in situ, highly reliable metallizations may be provided, wherein limitations with respect to contaminations and device scaling, encountered by conventional chemical vapor deposition (CVD), atomic layer deposition (ALD) and physical vapor deposition (PVD) techniques for the formation of seed layers may be overcome. In some embodiments, a barrier layer is also deposited on the basis of a wet chemical deposition process.

Abstract: A method for producing a color-converting light-emitting device is provided that can prevent the deposition of elements caused by ion migration during an electrophoresis process used to deposit a phosphor layer on the light emitting device. An anode and a light-emitting device having a semiconductor light-emitting element are disposed in a solution in which phosphor particles are dispersed. An auxiliary cathode can be disposed between the light-emitting device and the anode. A DC voltage can be applied between one electrode of the light-emitting device and the anode so that the electrical potential of the electrode is lower than that of the anode, thereby moving the particles to a surface of the semiconductor light-emitting element and allowing them to deposit thereon. The electrical potential of the auxiliary cathode is maintained lower than that of the surface of the semiconductor light-emitting element.

Abstract: Silicide formation processes are disclosed that use an electrochemical displacement reaction in the absence of an externally applied current or potential. In an embodiment, a method for forming an integrated circuit comprises: depositing a metallic material upon select areas of a semiconductor topography comprising silicon by contacting the semiconductor topography with an aqueous solution comprising an acid and a metal salt to cause an electrochemical displacement reaction in the absence of an externally applied current or potential, wherein a concentration of the metal salt in the aqueous solution is about 0.01 millimolar to about 0.5 millimolar; and annealing the metallic material to form a silicide upon the areas of the semiconductor topography comprising the silicon.

Abstract: A metal film-forming method of the present invention can form a metal film having different film qualities in the thickness direction, in a continuous manner using a single processing solution. The metal film-forming method including: providing a substrate having embedded interconnects formed in interconnect recesses provided in a surface of the substrate; and forming a metal film, having different film qualities in the thickness direction, on surfaces of the interconnects in a continuous manner by changing the flow state of a processing solution relative to the surface of the substrate while keeping the surface of the substrate in contact with the processing solution.

Abstract: Methods of forming a roughened metal surface on a substrate are provided, along with structures comprising such roughened surfaces. In preferred embodiments roughened surfaces are formed by selectively depositing metal or metal oxide on a substrate surface to form discrete, three-dimensional islands. Selective deposition may be obtained, for example, by modifying process conditions to cause metal agglomeration or by treating the substrate surface to provide a limited number of discontinuous reactive sites. The roughened metal surface may be used, for example, in the manufacture of integrated circuits.

Abstract: A method of manufacturing an interconnect substrate by electroless plating, including: (a) forming a catalyst layer with a specific pattern on a substrate; (b) immersing the substrate in a first electroless plating solution including a first metal to deposit the first metal on the catalyst layer to form a first metal layer; and (c) immersing the substrate in a second electroless plating solution including a second metal to deposit the second metal on the first metal layer to form a second metal layer, an ionization tendency of the first metal being higher than an ionization tendency of the second metal.

Abstract: A method of filling a conductive material in a three dimensional integration structure feature formed on a surface of a wafer is disclosed. The feature is filled with a dispersion containing a plurality of conductive particles and a solvent. Then, the solvent is removed from the feature, leaving the plurality of conductive particles in the feature. These two steps are repeated until the feature is filled up with the conductive particles. Then, the conductive particles are annealed in the feature, thereby forming a dense conductive plug in the feature.

Abstract: A semiconductor device includes a first barrier metal layer and a second barrier metal layer, a third barrier metal layer, and a metal line. The first barrier metal layer and the second barrier metal layer are formed and on a top surface of an insulating layer over a semiconductor substrate on the bottom surface of trenches formed in the insulating layer. The third barrier metal layer is formed on sidewalls of trenches. The metal line gap-fills the trenches. In a method of forming a metal line of a semiconductor device, trenches are formed within an insulating layer over a semiconductor substrate. A first barrier metal layer and a second barrier metal layer are formed on a bottom surface of the trenches and on a top surface of the insulating layer. A third barrier metal layer is formed on sidewalls of trenches. A metal line gap-fills the trenches.

Abstract: An electroless plating method and the apparatus for performing the same are provided. The method includes providing a plating solution; contacting a front surface of the wafer with the plating solution; and incurring a plating reaction substantially simultaneously on an entirety of the front surface of the wafer. The step of incurring a plating reaction substantially simultaneously includes lift-dispense electroless plating and face-down immersion.

Abstract: A method for electroless plating of a substrate is provided that comprises exposing an electroless plating reagent comprising a metal to be plated and at least one reducing agent to a solid phase Activation Material to form an activated electroless plating reagent prior to application of the electroless plating reagent to the substrate. The activated electroless plating reagent is applied to a substrate in the process chamber under conditions to cause the metal of the electroless plating reagent to deposit on the substrate. Systems and modules are also described.

Abstract: A power semiconductor substrate comprising an insulating planar base, at least one conductor track and at least one contact area as part of the conductor track, wherein a layer of a metallic material is disposed on the contact area by means of pressure sintering. The associated method comprises the steps of: producing a power semiconductor substrate that includes a planar insulating base, conductor tracks and contact areas; arranging a pasty layer, composed of a metallic material and a solvent, on at least one contact area of the power semiconductor substrate; and applying pressure to the pasty layer.

Abstract: A method for fabricating a conductive layer is provided. First, a substrate is provided and a patterned adhesion layer is formed on the substrate. Next, a chemical plating process is performed to form a first metal layer on the patterned adhesion layer by placing the substrate in an electroplating solution and the electroplating solution is shocked. Thereafter, a second metal layer is formed on the first metal layer by performing a plating process.

Abstract: Described is a method for forming a stackable interconnect. The interconnect is formed by depositing a first contact on a substrate; depositing a seed layer (SL) on the substrate; depositing a metal mask layer (MML) on the SL; depositing a bottom anti-reflection coating (BARC) on the MML; forming a photoresist layer (PR) on the BARC; removing a portion of the PR; etching the BARC and the MML to expose the SL; plating the exposed SL to form a first plated plug; removing the layers to expose the SL; removing an unplated portion of the SL; depositing an inter layer dielectric (ILD) on the interconnect; etching back the ILD to expose the first plated plug; and depositing a second contact on the first plated plug. Using the procedures described above, a second plated plug is then formed on the first plated plug to form the stackable plugged via interconnect.

Abstract: The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing.

Abstract: A method for depositing a Ru metal layer on a patterned substrate from a film precursor vapor delivered from a multi-tray film precursor evaporation system. The method comprises providing a patterned substrate in a process chamber of a deposition system, and forming a process gas containing Ru3(CO)12 precursor vapor and a carrier gas comprising CO gas. The process gas is formed by: providing a solid Ru3(CO)12 precursor in a plurality of spaced trays within a precursor evaporation system, wherein each tray is configured to support the solid precursor and wherein the plurality of spaced trays collectively provide a plurality of surfaces of solid precursor; heating the solid precursor in the plurality of spaced trays in the precursor evaporation system to a temperature greater than about 60° C.

Abstract: According to various exemplary embodiments, a spring device that includes a substrate, a self-releasing layer provided over the substrate and a stressed-metal layer provided over the self-releasing layer is disclosed, wherein an amount of stress inside the stressed-metal layer results in a peeling force that is higher than an adhesion force between the self-releasing layer and the stressed-metal layer. Moreover, a method of manufacturing a spring device, according to various exemplary embodiments, includes providing a substrate, providing a self-releasing layer over the substrate and providing a stressed-metal layer over the self-releasing layer wherein an amount of stress inside the stressed-metal layer results in a peeling force that is higher than an adhesion force between the self-releasing layer and the stressed-metal layer is also disclosed in this invention.

Abstract: In a method for manufacturing a semiconductor device, either a nickel layer or a nickel-based metal layer is formed on a semiconductor substrate by using a plating process. Then, either the nickel layer or the nickel-based metal layer is washed with one of an aqueous hydrochloric acid solution and an aqueous sulfuric acid solution.

Abstract: A CoWB film is formed as a cap metal on a Cu interconnection line formed on a substrate or wafer W, by repeating a plating step and a post-cleaning step a plurality of times. The plating step is arranged to apply electroless plating containing CoWB onto the Cu interconnection line. The post-cleaning step is arranged to clean the wafer W by use of a cleaning liquid, after the plating step.

Abstract: Methods of electroless plating metal on a dielectric material includes dipping the dielectric in a solution containing attractive catalytic metal particles and a metal salt solution. A thicker metallic layer can be deposited on top of the resulting layer by electroplating. Electrical circuits and multichip modules including such circuits can be formed having one or more dielectric layers comprised of latex and one or more layers of conductive leads, one or more dielectric layers comprised of a flexible dielectric material, and one or more layers of electrically conductive material patterned to interconnect such ICs. Frames that hold ICs against a substrate may be employed to planarize their top surfaces against the substrate, as well as standard photolithographic techniques in creating conductive paths on the dielectric material between the ICs.

Abstract: A method and apparatus for electrochemically processing metal and barrier materials is provided. In one embodiment, a method for electrochemically processing a substrate includes the steps of establishing an electrically-conductive path through an electrolyte between an exposed layer of barrier material on the substrate and an electrode, pressing the substrate against a processing pad assembly, providing motion between the substrate and pad assembly in contact therewith and electrochemically removing a portion of the exposed layer during a first electrochemical processing step in a barrier processing station.

Abstract: A structure and process are provided that are capable of reducing the occurrence of discontinuities within the metallization, such as voiding or seams, formed during electroplating at the edges of semiconductor metallization arrays. The structure includes a metallization bar located around the periphery of the array. The process employs the structure during electroplating.

Abstract: A dry-in/dry-out system is disclosed for wafer electroless plating. The system includes an upper zone for wafer ingress/egress and drying operations. Proximity heads are provided in the upper zone to perform the drying operations. The system also includes a lower zone for electroless plating operations. The lower zone includes an electroless plating apparatus that implements a wafer submersion by fluid upwelling method. The upper and lower zones of the system are enclosed by a dual-walled chamber, wherein the inner wall is a chemically inert plastic and the outer wall is a structural metal. The system interfaces with a fluid handling system which provides the necessary chemistry supply and control for the system. The system is ambient controlled. Also, the system interfaces with an ambient controlled managed transfer module (MTM).

Abstract: A method of manufacturing a circuit substrate of the present invention, includes the steps of forming an n-layered (n is an integer of 1 or more) wiring layer connected electrically to a metal plate on the metal plate, forming an electroplating layer on a connection pad portion of an uppermost wiring layer of the n-layered wiring layer by an electroplating utilizing the metal plate and the wiring layer as a plating power-supply path, and removing the metal plate.

Abstract: Methods of fabricating an interconnect utilizing an electroless deposition technique, which fundamentally consists of providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, and electrolessly depositing a conductive material within the opening. Various processing steps and structures may be utilized in the fabrication of the interconnect, which may include but is not limited to forming barrier layers, utilizing seed materials, utilizing activation materials, and treating the dielectric material to be receptive to electroless deposition.

Abstract: A method for forming a seed layer for damascene copper wiring is provided. The method comprises the step of forming a seed layer, during damascene copper wiring formation, using an electroless plating solution comprising a water-soluble nitrogen-containing polymer and glyoxylic acid as a reducing agent, wherein the weight-average molecular weight (Mw) of the water-soluble nitrogen-containing polymer is 1,000 to less than 100,000. Preferably, the electroless plating solution further comprises phosphinic acid.

Abstract: A cap layer for a metal feature such as a copper interconnect on a semiconductor wafer is formed by immersion plating a more noble metal (e.g. Pd) onto the copper interconnect and breaking up, preferably by mechanical abrasion, loose nodules of the noble metal that form on the copper interconnect surface. The mechanical abrasion removes plated noble metal which is only loosely attached to the copper surface, and then continued exposure of the copper surface to immersion plating chemicals leads to plating at new sites on the surface until a continuous, well-bonded noble metal layer has formed. The method can be implemented conveniently by supplying immersion plating chemicals to the surface of a wafer undergoing CMP or undergoing scrubbing in a wafer-scrubber apparatus.

Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Abstract: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g.

Abstract: The invention relates to a method for producing an electronic component on a surface of a substrate with the electronic component having, seen at right angles to the surface of the substrate, at least two electrical functional layers which are arranged one above the other and such that they overlap at least in a surface area F, with the at least two electrical functional layers on the substrate being structured directly or indirectly using a continuous process, with a first electrical functional layer of the at least two electrical functional layers being structured such that a first length/width dimension of the first electrical functional layer parallel to the surface of the substrate and in a relative movement direction of the substrate is at least 5 ?m longer/wider, preferably more than 1 mm longer/wider, than a length/width dimension of the surface area F in the relative movement direction and parallel to the surface of the substrate.

Abstract: The present invention provides a plating method and a plating apparatus which can securely form a metal film (protective film) by electroless plating on the exposed surfaces of a base metal, such as interconnects without the formation of voids in the base metal. The plating method including providing a semiconductor device having an embedded interconnect structure, carrying out pretreatment of interconnects with a pre-treatment liquid containing a surface activating agent for the interconnects, carrying out catalytic treatment of the interconnects with a catalytic treatment liquid containing catalyst metal ions and an excessive etching inhibitor for the interconnects, and forming a protective film by electroless plating selectively on the surfaces of the interconnects.

Abstract: Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions.

Abstract: The present methods provide tools for growing conformal metal thin films, including metal nitride, metal carbide and metal nitride carbide thin films. In particular, methods are provided for growing such films from aggressive chemicals. The amount of corrosive chemical compounds, such as hydrogen halides, is reduced during the deposition of transition metal, transition metal carbide, transition metal nitride and transition metal nitride carbide thin films on various surfaces, such as metals and oxides. Getter compounds protect surfaces sensitive to hydrogen halides and ammonium halides, such as aluminum, copper, silicon oxide and the layers being deposited, against corrosion. Nanolaminate structures incorporating metallic thin films, and methods for forming the same, are also disclosed.

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Abstract: By forming an activation/nucleation layer selectively at a bottom of an opening, efficient electroless deposition techniques may be used for forming contacts, vias and trenches of advanced semiconductor devices. By selectively providing the activation material, a self-aligned bottom-to-top fill behavior may be obtained.

Abstract: The present invention relates to a method of forming a core/shell nanocrystal of semiconductor material. Typically the core may comprise CdTe and the shell may be CdS. The shell is synthesised on the core in an aqueous solution. In the method, the previously synthesised cores are placed in the aqueous solution, reactants that form the shell and a thiol such as 3-mercaptopropionic acid (MPA) are added, and the mixture is refluxed until the completion of the shell at the desired thickness. The synthesis of the shell is aided by the provision of an interface zone between the shell and core so that lattice mismatch between the core and shell is reduced. The interface zone may be produced using a method that provides a gradient alloyed core with increased levels of sulphur, for example, at the surface relative to the centre of the core. Alternatively the interface zone may be a separate layer on a homogenous core.