Abstract: A metal suicide film and method of forming the same are provided. The method comprises depositing metal silicide layers onto a substrate assembly with alternating layers of silicon. The resulting metal silicide film has a disrupted grain structure and smaller grain sizes than prior art films of the same thickness, which increases the resistance of the material to stress cracks in subsequent thermal processing and reduces the overall residual stress of the material.

Abstract: A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.

Abstract: Disclosed is a method for depositing a tungsten silicide layer on a wafer coated with a polysilicon layer in a CVD process chamber. A surface of the polysilicon layer is pre-treated by introducing a hydrogen compound gas including any elements among group III elements or group V elements of the periodic table into the CVD process chamber. The tungsten silicide layer is deposited on the polysilicon layer by introducing a silane source gas and a tungsten source gas into the CVD process chamber. Since the surface of the polysilicon layer is pre-treated using the hydrogen compound gas before the tungsten silicide layer is deposited on the polysilicon layer, void generation is prevented on an interfacial surface between the tungsten silicide layer and the polysilicon layer.

Abstract: A method of fabricating a self-aligned silicide (salicide). A gate and a source/drain region are formed in the substrate. An ion implantation process is performed to dope surfaces of the gate and the source/drain region with metal ions. A thermal process is performed to have the metal ions react with silicon in surfaces of the gate and the source/drain region, so as to form silicide layers on the gate and the source/drain region. The metal ions include cobalt ions, titanium ions, nickel ions, platinum ions and palladium ions.

Abstract: A method for forming a metal/dielectric multi-layered interconnect. A conductive layer is formed over a substrate. A protective film is formed over the conductive layer. A first high-density plasma fluorinated silica glass (HDP-FSG) layer is formed over the substrate by performing a HDP chemical vapor deposition with a low bias-voltage power. A second HDP-FSG layer is formed over the first HDP-FSG film by performing a HDP chemical vapor deposition at a higher bias-voltage power. A chemical-mechanical polishing is carried out to planarize the FSG layer. A silicon oxynitride is formed over the FSG layer. A via opening is formed in the FSG layer above the conductive layer. A barrier layer is formed onto the via opening and silicon oxynitride. Tungsten is deposited over the substrate filling the via opening. A tungsten chemical-mechanical polishing is carried out to remove excess tungsten and barrier layer above the silicon oxynitride layer.

Abstract: A semiconductor device comprises impurity diffusion layers formed in a semiconductor substrate and containing a metal element, whose siliciding activation energy is less than 1.8 eV, at a concentration of more than 1×1011 atoms/cm2 and less than 1×1015 atoms/cm2, an insulating film formed on the semiconductor substrate, contact holes formed in the insulating film on the impurity diffusion layers, and contact plugs formed via the contact holes. Accordingly, there is provided the semiconductor device that has a connection structure between an impurity-containing semiconductor layer and a conductive film and is capable of suppressing a leakage current generated at a contact portion between the impurity diffusion layer and the conductive film.

Abstract: A dual salicidation process has the steps of: covering a sacrificial layer on the top of a polysilicon gate conductor; performing a thermal oxidization process to form a poly-oxide spacer on the sidewall of the polysilicon gate conductor; forming source/drain regions within the substrate at the outer lateral surfaces of the poly-oxide spacer;removing the sacrificial layer; performing a first salicidation process to convert the polysilicon gate conductor to a silicide gate conductor; performing a second salicidation process to form silicide structures upon the source/drain regions.

Abstract: Method for fabricating a polycide dual gate in a semiconductor device fabricates a dual gate having polycide gate electrodes. The polycide can be a cobalt polycide, for example. The method can include forming polysilicon pattern layers on a first and a second regions of a semiconductor substrate, forming a blocking layer to expose top surfaces of the polysilicon pattern layers and mask the substrate, and forming a metal layer on an entire surface and then is annealed to form a gate electrode having a stack of the polysilicon pattern layer under a silicide layer. Impurity ions of opposite conductivities in the first and second regions can be respectively deposited and diffused to form source/drain regions in surfaces of the substrate on both sides of the gate electrode. The implanted impurity ions can further implant ions in the silicide/polysilicon pattern layer gate to reduce fabrication steps or simplify the fabrication process.

Abstract: A method to fabricate a 1T-RAM device, comprising the following steps. A semiconductor substrate having an access transistor area and an exposed bottom plate within a capacitor area proximate the access transistor area is provided. A gate with an underlying gate dielectric layer within the access transistor area are formed. The gate and underlying gate dielectric layer having sidewall spacers formed over their respective exposed side walls. A top plate with an underlying capacitor layer over the bottom plate within the capacitor area are formed. The top plate and underlying capacitor layer having sidewall spacers formed over their respective exposed side walls. A patterned resist protect oxide (RPO) layer is formed over at least the drain of the structure not to be silicided. Metal silicide portions are formed over the structure not protected by the RPO layer.

Abstract: A method of fabricating bipolar junction transistors particularly suitable for electrostatic discharge protection and high voltage MOSFETs. In accordance with the invention, a mask covers bird's beaks formed between field oxide layers and doped regions of a semiconductor substrate. A silicide layer is then added to the exposed surface of the doped regions. The mask prevents the silicide layer from overlying the bird's beaks, thereby precluding the silicide layer from degrading the breakdown junction voltage of the transistor.

Abstract: A method of forming a silicide layer in contact with a silicon substrate. The method comprises forming the silicide layer by supplying a silicon-containing source that is different from the silicon substrate, such that the silicon in the silicide layer originates primarily from the silicon-containing source.

Abstract: Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate.

Abstract: A semiconductor device includes a semiconductor substrate having a device element, an interlayer dielectric layer (silicon oxide layer, BPSG layer) formed on the semiconductor substrate, a through hole defined in the interlaver dielectric layer, a barrier layer formed on surfaces of the interlayer dielectric layer and the through hole, and a wiring layer formed on the barrier layer. The barrier layer includes a first metal oxide layer formed from an oxide of a metal that forms the barrier layer (e.g., a first titanium oxide layer), a metal nitride layer formed from a nitride of the metal that forms the barrier layer (e.g., a titanium nitride layer), and a second metal oxide layer formed from an oxide of the metal that forms the barrier layer (e.g., a second titanium oxide layer). The semiconductor device thus manufactured has a barrier layer of an excellent barrier capability.

Abstract: A method for electromagnetically shielding circuits which combine to form an integrated circuit device provides isolated silicon islands surrounded laterally and subjacently by conductive material. The isolated silicon islands may be covered individually or as a group by a conductive cover. The integrated circuit may include at least one silicon island including an analog circuit and at least one silicon island including a digital circuit, the analog and digital circuits electromagnetically shielded from one another. The method for forming the structure includes providing a first semiconductor substrate and hydrophilically bonding a substructure to the first semiconductor substrate. The substructure includes the isolated silicon islands surrounded by the conductive material. The substructure may be formed on a second semiconductor substrate by implanting an impurity region into an upper portion of the second semiconductor substrate.

Abstract: A new method of forming MOS transistors with self-aligned silicide has been achieved. A gate oxide layer is formed overlying a semiconductor substrate. A polysilicon layer is deposited. The polysilicon layer and the gate oxide layer are patterned to form gates. Ions are implanted to form lightly doped drain regions. A dielectric layer is deposited. The dielectric layer is polished down to expose the top surface of the gates. The dielectric layer is then anisotropically etched down to form dielectric sidewall spacers. The dielectric sidewall spacers cover a portion of the vertical sidewalls of the gates while exposing a portion of the vertical sidewalls of the gates. Ions are implanted to form source and drain regions. A metal layer is deposited. Contact surfaces are formed between the metal layer with: the exposed top surfaces of the gates, the exposed portions of the vertical sidewalls of the gates, and the exposed source and drain regions.

Abstract: Tungsten silicide layers are formed on a substrate and a semiconductor component has deep trench capacitors with a filling of tungsten silicide. The tungsten silicide layers are deposited on the substrate at a temperature of less than 400° C. and at a pressure of less than 10 torr from the vapor phase. The vapor phase hs a tungsten-containing precursor substance and a silicon-containing precursor substance. The molar ratio of the silicon-containing precursor compound to the tungsten-containing precursor compound in the vapor phase is selected to be greater than 500.

Abstract: A leadframe for use with integrated circuit chips comprising a plated layer of gold selectively covering areas of said leadframe intended for solder attachment; and said gold layer providing a visual distinction to said areas.

Abstract: A method for making a gate in an integrated circuit. A gate layer is formed on a substrate, and a blocking layer is formed on the gate layer. The blocking layer is masked with a photoresist layer, and the photoresist layer is developed to define an exposed gate area. The blocking layer is etched in the gate area to expose the gate layer in the gate area, and the photoresist layer is removed. A metal layer is formed on the blocking layer and on the gate layer in the gate area. The metal layer is selectively reacted with the gate layer in the gate area to form a hard mask over the gate layer in the gate area. The metal layer is removed from the blocking layer. The blocking layer is selectively etched without substantially etching the hard mask in the gate area, to expose the gate layer surrounding the gate area. The exposed gate layer is etched to define a gate in the gate area. The hard mask remains on the gate, and functions as an electrical contact to the gate.

Abstract: A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (TixAly)1-zNz film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a nMOS region, a (TixAly)1-zNz film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.

Abstract: A ternary metal silicide layer is formed between a silicon substrate and a barrier layer, in a contact structure including: a substrate having a silicon part; an insulating layer formed on the substrate, and having a connection hole that reaches the silicon part, a barrier layer formed at least on an inner surface of the connection hole; and a conductive member buried inside the barrier layer.

Abstract: A MOS transistor includes a substrate, an insulation layer, a gate and a dielectric layer. The substrate includes a drain and a source separately positioned on the surface of the substrate. The insulation layer is positioned on the surface of the substrate between the drain and the source. The gate includes a conducting layer positioned on the insulation layer having a bottom side, a top side, a left side and a right side, and a metallic silicide layer positioned on the top side of the conducting layer wherein the width of the metallic silicide layer is greater than that of the bottom side of the conducting layer. The dielectric layer covers the drain, the source and the metallic silicide layer. The transistor includes at least one empty side slot positioned between the dielectric layer and the left side or right side of the conducting layer below the metallic silicide layer.

Abstract: A method of forming a semiconductor substrate (and resultant structure), includes providing a semiconductor substrate to be silicided including a source and drain formed therein on respective sides of a gate, depositing a metal film over the gate, source and drain regions, reacting the metal film with Si at a first predetermined temperature, to form a metal-silicon alloy, etching the unreacted metal, depositing a silicon film over the source drain and gate regions, annealing the substrate at a second predetermined temperature, to form a metal-Si2 alloy, and selectively etching the unreacted Si.

Abstract: Disclosed is a method for manufacturing a silicide layer of semiconductor device. The disclosed comprises the steps of: depositing a lower metal layer on the surface of semiconductor substrate and then, performing a plasma treatment; and depositing an upper metal layer on the plasma-treated lower metal layer and then, performing a thermal treatment process, thereby forming a silicide layer on the surface of semiconductor substrate.

Abstract: A method of de-oxidizing a surface onto which a refractory metal or molecule which contains a refractory metal atom will be adhered. The method utilizes a plasma which includes a gas such as argon, nitrogen, helium or hydrogen, or a mixture of any of the foregoing, to remove oxygen molecules from the surface to which adherence of the refractory metal is desired. Radicals in the plasma coat the surface to prevent further oxidation thereof. The method also includes techniques for depositing refractory metals onto a surface such as a substrate or layer of semiconductor material on which integrated circuitry has been fabricated.

Abstract: The method of manufacturing a semiconductor device of the present invention comprises a step of forming a titanium layer (2) on silicon-containing layers (a gate electrode (14) and an impurity layer (18)) which are formed on a silicon substrate (1); a step of forming a protective layer (3) having compression stress on the silicon substrate (1), on the titanium layer (2); and a step of forming a titanium silicide layer by reacting silicon in the silicon containing layer and titanium in the titanium layer (2) by thermal processing. The compression stress of the protective layer is preferably in the range from 1×109 Dyne/cm2 to 2×1010 Dyne/cm2. The protective layer (3) is preferably made from at least one metal selected from the group consisting of tungsten, cobalt, tantalum, and molybdenum. According to the present invention, a fine interconnecting effect is suppressed by avoiding the effect of a stress which obstructs a phase transition in the titanium silicide layer.

Abstract: A method of manufacturing a semiconductor device (2) on a substrate (1), said semiconductor device comprising an active area (5, 6, 16) in the substrate (1) demarcated by spacers (10-13, 20-23) and arranged so as to contact an interconnect (29) including TiSi2; the method including:

Abstract: A semiconductor device and method for manufacturing the semiconductor device employing mixed metal silicide technology is disclosed. A semiconductor device is provided having a doped silicon region, such as a source/drain. A first metal layer comprising titanium and a second metal layer comprising nickel are deposited over the semiconductor device. The device is subjected to rapid thermal annealing. The resulting device has a mixed metal silicide layer over the doped silicon region, the mixed metal silicide layer and the doped silicon region having smooth interface between them.

Abstract: A semiconductor device comprising a substrate, a conductor and an insulating film provided on the surface of the substrate, part of the surface of the substrate being electrically connected with the conductor through a contact hole made in the insulating film, wherein a barrier layer present between part of the surface of the substrate and the conductor is provided only on the bottom of the contact hole, and the barrier layer provided on the bottom comprises amorphous titanium silicon nitride. This can provide a structure that has a barrier layer with a low contact resistance, enables formation of a conductor film of good quality on the barrier layer, and can attain a good electrical conduction even at fine contact holes.

Abstract: A programmable substrate and a method of making a programmable substrate for use with array-type packages, including Ball Grid Arrays(BGA), Pin Grid Arrays (PGA) and Column Grid Arrays (CGA) includes a nonconductive programmable substrate with a cavity in the top of the substrate. The cavity is sized to receive an integrated circuit (IC) die. An array of electrically conductive vias pass through the substrate. A plurality of electrical traces are formed on the top of the substrate. The traces extend radially from an edge of the die cavity to the periphery of the substrate so as to pass between and near the vias. Each trace is electrically connected to a pad of the IC die by a wire bond. Each via is connected on a bottom surface of the substrate to a solder ball, pin, or other means for electrically and mechanically attaching the substrate to a printed circuit board. The traces are programmably connected to a selected via, e.g.

Abstract: A method for forming a MOSFET includes the steps of forming cobalt silicide layers on a polysilicon gate electrode and source/drain regions, implanting impurity ions to form source/drain extensions and diffusing the impurity ions in the source/drain extensions The temperature of the heat treatment for diffusing step is lower than the maximum of the temperatures of the heat treatment for forming the silicide layer, whereby a MOSFET having excellent short-channel characteristics and a higher reliability can be obtained.

Abstract: In a process for producing a first electrode and a second electrode, the first electrode and the second electrode are provided on an electrode material. A cluster ion source is used to apply clusters of the electrode material to the first electrode and/or the second electrode.

Abstract: In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from being adsorbed onto the surface of the first conductive layer. In one embodiment, a second conductive layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates an oxide formed between the two layers as a result of subsequent thermal treatments. In another embodiment, a dielectric layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates the ability of the first conductive layer to incorporate oxygen from the dielectric.

Abstract: The semiconductor device of the present invention includes: a substrate; a first conductor film supported by the substrate; an insulating film formed on the substrate to cover the first conductor film, an opening being formed in the insulating film; and a second conductor film, which is formed within the opening of the insulating film and is in electrical contact with the first conductor film. The second conductor film includes: a silicon-containing titanium nitride layer formed within the opening of the insulating film; and a metal layer formed over the silicon-containing titanium nitride layer. The metal layer is mainly composed of copper.

Abstract: A method of depositing a metal nitride material, formed by the decomposition of an organometallic precursor, useful as a barrier layer for an integrated circuit using a conducting metal. More particularly, the invention provides a method of depositing a niobium nitride layer on a substrate for use in copper metallization. In one aspect of the invention an organometallic precursor having the formula Nb(NRR′)5, the formula (NRR′)3Nb═NR″, or combinations thereof, is introduced into a processing chamber in the presence of a processing gas, such as ammonia, and the metal nitride film is deposited by the thermal or plasma enhanced decomposition of the precursor on a substrate. The deposited niobium nitride layer is then exposed to a plasma to remove contaminants, reduce the film's resistivity, and densify the film.

Abstract: In a semiconductor device, a contact stud (100) contacts a semiconductor substrate (10); the stud is embedded in an insulating structure with a first insulating layer (20) and a second insulating layer (20′). During manufacturing, (a) the first layer (20) is provided above the substrate (10); (b) a hole in the first layer exposes a portion of the upper surface of the substrate to receive the stud; (c) a contact material (30, 40) is provided at the top of the resulating structure; (d) a first chemical-mechanical polishing (CMP) removes the contact material from the surface of the first layer outside the hole; (e) residuals (50) of the contact material are cleaned away from the upper surface; (f) the second insulating layer (20′) is provided at the surface of the resulting structure; (g) and further polishing is applied.

Abstract: The present invention relates to chemical vapor deposition processes related to the manufacture of integrated circuit devices. In accordance with one embodiment of the present invention, a process for forming an electrical contact to a silicon substrate is provided wherein a semiconductor wafer is positioned in a reaction chamber wherein the semiconductor wafer includes an insulating layer disposed over a semiconductor substrate, and the insulating layer defines a contact opening therein. The contact opening defines insulating side wall regions herein. The insulating side walls extend from an upper surface region of the insulating layer to an exposed semiconductor region of the semiconductor substrate. A set of reactants are introduced into the reaction chamber, RF plasma is generated in the vicinity of the semiconductor wafer, and the temperature and pressure of the reaction chamber is regulated.

Abstract: A method is provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). In one embodiment, a titanium precursor and a silicon precursor are contacted in the presence of hydrogen, to form titanium silicide. In another embodiment, a titanium precursor contacts silicon to form to form titanium silicide.

Abstract: A method of de-oxidizing a surface onto which a refractory metal or molecule which contains a refractory metal atom will be adhered. The method utilizes a plasma which includes a gas such as argon, nitrogen, helium or hydrogen, or a mixture of any of the foregoing, to remove oxygen molecules from the surface to which adherence of the refractory metal is desired. Radicals in the plasma coat the surface to prevent further oxidation thereof. The method also includes techniques for depositing refractory metals onto a surface such as a substrate or layer of semiconductor material on which integrated circuitry has been fabricated.

Abstract: A novel method for forming a C54 phase titanium disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A titanium layer is deposited overlying the silicon regions to be silicided. The substrate is subjected to a first annealing whereby the titanium is transformed to phase C40 titanium disilicide where it overlies the silicon regions and wherein the titanium not overlying the silicon regions is unreacted. The unreacted titanium layer is removed. The substrate is subjected to a second annealing whereby the phase C40 titanium disilicide is transformed to phase C54 titanium disilicide to complete formation of a phase 54 titanium disilicide film in the manufacture of an integrated circuit.

Abstract: An integrated circuit device, and a method of manufacturing the same, including nickel silicide on a silicon substrate fabricated with an iridium interlayer. In one embodiment the method comprises depositing an iridium (Ir) interface layer between the Ni and Si layers prior to the silicidation reaction. The thermal stability is much improved by adding the thin iridium layer. This is shown by the low junction leakage current of the ultra-shallow junction, and by the low sheet resistance of the silicide, even after annealing at 850° C.

Abstract: Methods of forming refractory metal silicide components are described. In accordance with one implementation, a refractory metal layer is formed over a substrate. A silicon-containing structure is formed over the refractory metal layer and a silicon diffusion restricting layer is formed over at least some of the silicon-containing structure. The substrate is subsequently annealed at a temperature which is sufficient to cause a reaction between at least some of the refractory metal layer and at least some of the silicon-containing structure to at least partially form a refractory metal silicide component. In accordance with one aspect of the invention, a silicon diffusion restricting layer is formed over or within the refractory metal layer in a step which is common with the forming of the silicon diffusion restricting layer over the silicon-containing structure.

Abstract: A method for forming an improved RPO layer by using a composite layer and a two-step etching process in a salicide process in the fabrication of integrated circuits is described. Isolation areas are formed on a semiconductor substrate surrounding and electrically isolating device areas wherein at least one device area is to be silicided and wherein at least one device area is not to be silicided. A composite resist protective oxide layer is formed overlying device areas comprising a first layer of oxide and a second layer of silicon oxynitride. The silicon oxynitride layer is dry etched away overlying the device area to be silicided. Thereafter, the oxide layer is wet etched away overlying the device area to be silicided. Silicidation is performed to complete fabrication of the integrated circuit device.

Abstract: A method for manufacturing a semiconductor device employing mixed metal silicide technology is disclosed. The method comprises providing a semiconductor device having a doped silicon region, such as a source/drain, sequentially layering a first metal comprising cobalt, and a second layer comprising nickel over the semiconductor device, and subjecting the device to rapid thermal annealing. The resulting device has a mixed metal silicide layer overtop the doped silicon region, wherein the mixed metal silicide layer and the doped silicon region form a smooth boundary between them.

Abstract: The present invention is related to a method of forming a polycrystalline cobalt disilicide or another near noble metal silicide on a silicon substrate. The method comprises the steps of depositing a layer or layers comprising a cobalt-alloy (Ni, Pd, Pt) and a refractory metal on at least a part of said substrate, said part comprising at least a first and a second part, said second part being covered; thereafter heating said silicon substrate in a first heating step and a second heating step and therebetween treating said substrate with at least one chemical solution, said chemical solution selectively etching non-silicidecobalt (or Ni, Pd, Pt) and said refractory metal and cobalt-refractory (or Ni, Pd, Pt-refractory) metal alloys from said substrate except from said first part.

Abstract: A semiconductor device and a method of forming same are disclosed.

Abstract: A method of forming a crystalline phase material includes, a) providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase; and b) annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. The stress inducing material preferably induces compressive stress within the first crystalline phase during the anneal to the second crystalline phase to lower the required activation energy to produce a more dense second crystalline phase. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials for providing into layers are Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material.

Abstract: A method of manufacturing a semiconductor device in a salicide process to lower a contact resistance between a junction and a metal wiring, wherein a TiSi2 layer is formed on the junction at the same time when Ti is deposited by means of a plasma vapor deposition method using TiCl4 gas and H2 gas. Therefore, the method can simplify the process and reduce the amount of consumption of silicon atoms in the junction, compared to the conventional salicide process by which a TiSi2 layer is formed by annealing process after Ti is deposited, thus realizing a stable leakage current characteristic.

Abstract: Provided herein is a method of depositing alpha-tantalum film on a semiconductor wafer by depositing a tantalum nitride film on a wafer; and then depositing a tantalum film over the tantalum nitride film using wafer bias. The tantalum film as deposited is in alpha phase. Also provided is a method of depositing Cu barrier and seed layer on a semiconductor wafer, comprising the steps of depositing a tantalum nitride layer on a wafer; depositing a tantalum layer over the tantalum nitride layer using wafer bias, wherein the resulting tantalum barrier layer is in alpha phase; and then depositing Cu seed layer over the alpha-tantalum barrier layer. Further provided is a method of depositing alpha-tantalum film/layer using two-chamber process, wherein the tantalum nitride and subsequently deposited tantalum films/layers can be deposited in two separate chambers, such as IMP or SIP chambers. Still further provided is a method of depositing alpha-tantalum film by depositing PVD tantalum film on CVD films.

Abstract: A semiconductor process is provided that creates fully-salicided transistors. in a first region and partially-salicided transistors in a second region. Each of the fully-salicided transistors includes a salicided gate electrode and salicided active regions. Each of the partially-salicided transistors includes a salicided gate electrode and active regions that are free from salicide. A silicide blocking layer prevents the formation of salicide in the active regions of the partially-salicided transistors. The silicide blocking layer is deposited over the first and second regions, and then removed over the first region. The remaining portion of the silicide blocking layer over the second region is then etched back until the upper surfaces of the gate electrodes in the second region are exposed. The remaining portions of the silicide blocking layer covers the active regions in the second region. A refractory metal is then deposited over the resulting structure and reacted.

Abstract: A method for forming a metal layer located over a metal underlayer of a semiconductor device, using a metal halogen gas. The method involves supplying a predetermined reaction gas into a reaction chamber for a predetermined period of time prior to deposition of the metal layer. The reaction gas has a higher reactivity with an active halogen element of a metal halogen gas supplied to form the metal layer, compared to a metal element of the metal halogen gas. As the metal halogen gas is supplied into the reaction chamber, the reaction gas reacts with the halogen radicals of the metal halogen gas, so that the metal underlayer is protected from being contaminated by impurities containing the halogen radicals.