Abstract: A method for fabricating a transistor of semiconductor is disclosed.

Abstract: A submicron contact opening fill using a chemical vapor deposition (CVD) TiN liner/barrier and a high temperature, e.g., greater than about 385° C., physical vapor deposition (PVD) aluminum alloy layer that substantially fills the submicron contact.

Abstract: By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number of interface defects located between the grown silicon layer and the initial substrate surface may be significantly reduced. Consequently, deleterious effects such as charge carrier gettering or creating diffusion paths for dopants may be suppressed.

Abstract: The invention provides a semiconductor device, and a manufacturing method, comprising a semiconductor substrate, a gate insulating film, a gate electrode, and a source-drain diffusion layer. A silicide film is formed on the gate electrode and the source-drain diffusion layer. The silicide film is thicker on the gate electrode than on the source-drain diffusion layer. The manufacturing method comprises forming a gate electrode on a gate insulating film, followed by forming a source-drain diffusion layer. Then, atoms inhibiting a silicidation are selectively introduced into the source-drain diffusion layer, and a high melting point metal film is formed on the gate electrode and the source-drain diffusion layer. The high melting point metal film is converted into silicide films selectively on the gate electrode and the source-drain diffusion layer.

Abstract: A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a heat treatment is performed to convert the metals into metal silicides so as to improve the electrical conductivity of the silicon-containing regions. In this way, silicide portions may be formed that are individually adapted to specific silicon-containing regions so that device performance of individual semiconductor elements or the overall performance of a plurality of semiconductor elements may be significantly improved. Moreover, a semiconductor device is disclosed comprising at least two silicon-containing regions having formed therein differing silicide portions, wherein at least one silicide portion comprises a noble metal.

Abstract: Methods of forming MOS transistors include forming lightly and heavily doped source/drain regions adjacent to one another in a substrate and a gate electrode with a sidewall spacer thereon. A salicide process is performed on a surface of the heavily doped source/drain region to provide a first suicide layer self-aligned to the sidewall spacer. At least a portion of the sidewall spacer is removed to expose a portion of the lightly doped source/drain region adjacent to the first silicide layer. A salicide process in performed on the exposed portion of the lightly doped source/drain region to provide a second silicide layer adjacent to the first suicide layer. Related devices are also disclosed.

Abstract: The present invention provides a method for enhancing uni-directional diffusion of a metal during silicidation by using a metal-containing silicon alloy in conjunction with a first anneal in which two distinct thermal cycles are performed. The first thermal cycle of the first anneal is performed at a temperature that is capable of enhancing the uni-directional diffusion of metal, e.g., Co and/or Ni, into a Si-containing layer. The first thermal cycle causes an amorphous metal-containing silicide to form. The second thermal cycle is performed at a temperature that converts the amorphous metal-containing silicide into a crystallized metal rich silicide that is substantially non-etchable as compared to the metal-containing silicon alloy layer or a pure metal-containing layer. Following the first anneal, a selective etch is performed to remove any unreacted metal-containing alloy layer from the structure.

Abstract: A method of optimizing the formation of nickel silicide on regions of a MOSFET structure, has been developed. The method features formation of nickel silicide using an anneal procedure performed at a temperature below which nickel silicide instability and agglomeration occurs. A thin titanium interlayer is first formed on the MOSFET structure prior to nickel deposition, allowing an anneal procedure, performed after nickel deposition, to successfully form nickel silicide at a temperature of about 400° C. To obtain the desired conformality and thickness uniformity the thin titanium interlayer is formed via an atomic layer deposition procedure.

Abstract: A method for fabricating semiconductor devices includes forming a protective layer on a metallic layer prior to forming a metallic silicide layer, the protective layer having a thickness greater than that of the metallic layer.

Abstract: Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing process to form a copper wiring within a damascene pattern. At this time, the chemical mechanical polishing process is overly performed so that the top surface of the copper wiring is concaved and is lower than the surface of the interlayer insulating film of the low dielectric constant neighboring it. Furthermore, an annealing process is performed so that the top surface of the copper wiring is changed from the concaved shape to a convex shape while stabilizing the copper wiring. A copper anti-diffusion insulating film is then formed on the entire structure including the top surface of the copper wiring having the convex shape.

Abstract: A low resistance Co silicide layer with less leakage current is formed over the surface of the source and drain of a MISFET by optimizing the film forming conditions and annealing conditions upon formation of Co (cobalt) silicide. More specifically, a low resistance source and drain (n+ type semiconductor regions, p+ type semiconductor regions) with less junction leakage current are formed, upon formation of a Co silicide layer by heat treating a Co film deposited over the source and drain (n+ type semiconductor regions, p+ type semiconductor regions) of the MISFET, by depositing the Co film at a temperature as low as 200° C. or less, carrying out heat treatment in three stages to convert the Co silicide layer from a dicobalt silicide (Co2Si) layer to a cobalt monosilicide (CoSi) layer and, then, to a cobalt disilicide (CoSi2) layer, successively.

Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.

Abstract: A manufacturing method of a semiconductor device includes forming a cobalt film on a silicon substrate on which a diffusion layer is formed, forming a titanium film on the cobalt film using a titanium target having a surface from which a nitride film has previously been removed, forming a titanium nitride film containing titanium on the cobalt film by a reactive sputtering process using a nitrogen gas and the titanium target, and performing an annealing to react the cobalt film with the silicon substrate, thereby accomplishing silicification.

Abstract: A semiconductor device includes a semiconductor substrate, an element-isolating region formed in the semiconductor substrate, a real element region formed in the semiconductor substrate and outside the element-isolating region and having a metal silicide layer formed on the surface thereof, and a dummy element region formed in the semiconductor substrate and outside the element-isolating region and having a metal silicide layer formed on the surface thereof. The ratio of the sum of pattern areas of the real element region and dummy element region occupied in a 1 ?m-square range of interest including the element region is 25% or more.

Abstract: A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.

Abstract: A TiSiN film is used as a barrier metal layer for a semiconductor device to prevent the diffusion of Cu. The TiSiN film is formed by a plasma CVD process or a thermal CVD process. TiCl4 gas, a silicon hydride gas and NH3 gas are used as source gases for forming the TiSiN film by the thermal CVD process. TiCl4 gas, a silicon hydride gas, H2 gas and N2 gas are used as source gases for forming a TiSiN film by the plasma CVD process.

Abstract: A method of manufacturing a ceramic film includes a step of forming a ceramic film 30 by crystallizing a raw material body 20. The raw material body 20 contains different types of raw materials in a mixed state. The different types of raw materials differ from one another in at least one of a crystal growth condition and a crystal growth mechanism in the crystallization of the raw materials. According to this manufacturing method, a surface morphology of the ceramic film can be improved.

Abstract: Methods of making a semiconductor structure are disclosed. A refractory metal layer containing W, TiW, Ta, or TaN and semiconductor layer are formed on a substrate that contains copper in, for example, a via therein. A portion of the refractory metal layer and semiconductor layer is removed by etching using a fluorine-containing compound. By using W, TiW, Ta, or TaN as the refractory metal layer material and employing fluorine-based etching, the copper portion in the substrate is not substantially etched, thus preventing corrosion of the copper portion.

Abstract: A method for forming a barrier metal of a semiconductor device wherein a TiSiN layer having an atomic layer thickness is deposited by performing deposition of an Si layer inside a contact hole of a semiconductor device using an atomic layer deposition process and by performing deposition of a precursor layer on the Si layer. By repetition of this ALD process, the TiSiN layer is thickly formed at a desired thickness. Then, the TiSiN layer is plasma processed under the atmosphere of a nitrogen gas and a hydrogen gas, or an ammonia gas, and thus impurities are removed from the TiSiN layer. Therefore, it is easy to thickly form the TiSiN layer for the barrier metal. It is possible to reduce resistivity of the TiSiN layer to a relatively low level. Thereby, it is possible to decrease a contact resistance of the TiSiN layer and, further, to enhance an electrical characteristic of the semiconductor device.

Abstract: A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device having a first well region in a semiconductor substrate, first source/drain silicide areas in the first well region, and a first type gate isolated from the first source/drain silicide areas; forming a second type semiconductor device having a second well region in the semiconductor substrate, second source/drain silicide areas in the second well region, and a second type gate isolated from the second source/drain silicide areas; selectively forming a first metal layer over the second type semiconductor device; performing a first fully silicided (FUSI) gate formation on only the second type gate; depositing a second metal layer over the first and second type semiconductor devices; and performing a second FUSI gate formation on only the first type gate.

Abstract: A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided. In the present invention, ions that are capable of attaching to defects within the Si-containing layer are implanted into the Si-containing layer prior to formation of metal silicide. The implanted ions stabilize the film, because the implants were found to substantially prevent agglomeration or at least delay agglomeration to much higher temperatures than in cases in which no implants were used.

Abstract: Disclosed is a method for forming a bit-line of a semiconductor device. In a line patterning process for forming a bit-line in a DRAM (Dynamic Random Access Memory) of a semiconductor device, a barrier metal layer and a tungsten layer are sequentially formed on an interlayer insulating film comprising a contact hole to fill the contact hole by a CVD (Chemical Vapor Deposition) method. Then, the barrier metal layer and the tungsten layer are removed until the interlayer insulating film is exposed, and a tungsten layer having small thickness is re-formed on the exposed interlayer insulating film by a PVD (physical Vapor Deposition) method. As a result, the bit-line area is reduced as much as the barrier metal layer removed from the upper portion of interlayer insulating film, thereby having low bit-line capacitance.

Abstract: Embodiments of the invention generally relate to an apparatus and method of integration of titanium and titanium nitride layers. One embodiment includes providing one or more cycles of a first set of compounds such as a titanium precursor and a reductant, providing one or more cycles of a second set of compounds such as the titanium precursor and a silicon precursor and providing one or more cycles of a third set of compounds such as the titanium precursor and a nitrogen precursor. Another embodiment includes depositing a titanium layer on a substrate, depositing a passivation layer containing titanium silicide, titanium silicon nitride or combinations thereof over the titanium layer and subsequently depositing a titanium nitride layer over the passivation layer. Still another embodiment comprises depositing a titanium layer on a substrate, soaking the titanium layer with a silicon precursor and subsequently depositing a titanium nitride layer thereon.

Abstract: A method for depositing metal layers on semiconductor substrates by a thermal chemical vapor deposition (TCVD) process. The TCVD process utilizes high flow rate of a dilute process gas containing a metal-carbonyl precursor to deposit a metal layer. In one embodiment of the invention, the metal-carbonyl precursor can be selected from at least one of W(CO)6, Ni(CO)4, Mo(CO)6, Co2(CO)8, Rh4(CO)12, Re2(CO)10, Cr(CO)6, and Ru3(CO)12. In another embodiment of the invention, a method is provided for depositing a W layer from a process gas comprising a W(CO)6 precursor at a substrate temperature of about 410° C. and a chamber pressure of about 200 mTorr.

Abstract: A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.

Abstract: In forming a thin conductive layer in an interconnect structure by sputter deposition including a re-sputtering step, a flash deposition step is performed after the re-sputtering step to provide a sufficient layer thickness at critical locations, such as at positions of structure irregularities. The flash deposition step may be performed for a fixed process time so that less effort in process control is required while, at the same time, an increased reliability may be obtained compared to conventional approaches without a flash deposition.

Abstract: A process is described for creating a uniformly thick layer of titanium, cobalt, or nickel silicide over a layer of polysilicon that has features or a non-planar topography. A dual layer of metal is deposited onto patterned polysilicon such that the first layer covers the bottoms and tops of the non-planar topography and the second layer covers the sidewalls and tops of the non-planar topography. By heating the metal, etching away any un-reacted metal, and heating the result a second time, a metal silicide layer of uniform thickness, reduced stress and reduced resistivity is formed.

Abstract: The present invention provides a technique for forming a metal silicide, such as a cobalt disilicide, even at extremely scaled device dimensions without unduly degrading the film integrity of the metal silicide. To this end, an ion implantation may be performed, advantageously with silicon, prior to a final anneal cycle, thereby correspondingly modifying the grain structure of the precursor of the metal silicide.

Abstract: A method for forming a tantalum-containing gate electrode structure by providing a substrate having a high-k dielectric layer thereon in a process chamber and forming a tantalum-containing layer on the high-k dielectric layer in a thermal chemical vapor deposition process by exposing the substrate to a process gas containing TAIMATA (Ta(N(CH3)2)3(NC(C2H5)(CH3)2)) precursor gas. In one embodiment of the invention, the tantalum-containing layer can include a TaSiN layer formed from a process gas containing TAIMATA precursor gas, a silicon containing gas, and optionally a nitrogen-containing gas. In another embodiment of the invention, a TaN layer is formed on the TaSiN layer. The TaN layer can be formed from a process gas containing TAIMATA precursor gas and optionally a nitrogen-containing gas. A computer readable medium executable by a processor to cause a processing system to perform the method and a processing system for forming a tantalum-containing gate electrode structure are also provided.

Abstract: A method of manufacturing a semiconductor device is disclosed wherein a tungsten single atomic layer is deposited in a contact or via hole of a silicon substrate. A tungsten nitride (WN) layer is formed by plasma processing the tungsten single atomic layer using an atomic layer deposition process, which is repeated to form the tungsten nitride layer having a desired thickness as the barrier metal. A tungsten layer is then deposited on the semiconductor substrate to fill the contact hole. The tungsten nitride layer and the tungsten layer are in-situ deposited in a same reaction chamber for tungsten process. Accordingly, the step coverage of the tungsten nitride layer, is improved, thus reducing the contact defects of the fine contact hole, which has a high aspect ratio.

Abstract: A processing method for fabricating silicide is provided. First of all, a semiconductor structure having a semiconductor surface and an insulation surface is provided. Next, an epitaxial layer on the semiconductor surface is formed. And, the semiconductor structure is treated. The treat step is that the removal rate of the insulation surface is faster than the removal rate of the epitaxial layer. Then, a metal layer on the epitaxial layer is formed. Finally, heating the epitaxial layer forms silicide. The treatment step prevents the insulation surface from the formation of the silicide so as to reduce the degradation of device characteristics.

Abstract: Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat.

Abstract: A physical vapor deposition sputtering process for enhancing the <0002> preferred orientation of a titanium layer uses hydrogen before or during the deposition process. Using the oriented titanium layer as a base layer for a titanium, titanium nitride, aluminum interconnect stack results in formation of an aluminum layer with predominant <111> crystallographic orientation which provides enhanced resistance to electromigration. In one process, a mixture of an inert gas, usually argon, and hydrogen is used as the sputtering gas for PVD deposition of titanium in place of pure argon. Alternatively, titanium is deposited in a two-step process in which an initial burst of hydrogen is introduced into the reaction chamber in a separate, first step. Pure argon is used as the sputtering gas for the titanium deposition in a second step. The method is broadly applicable to the deposition of metallization layers.

Abstract: Disclosed is a method for manufacturing a semiconductor device, more particularly to a method of forming a spacer on side-walls of a titanium polycide gate. The method for manufacturing the semiconductor device is as follows. There is provided a semiconductor substrate in which a gate oxide layer, a polysilicon layer, a titanium silicide layer and a patterned hard mask layer are sequentially formed. Herein, the titanium polycide gate is fabricated by an etching step employing the patterned hard mask. Afterward, the substrate is thermal-treated at temperature of 700˜750° C. according to a gate re-oxidation process, thereby forming a re-oxidation layer on side-walls of the gate and on the substrate surface. Next, an oxide layer for spacer is deposited on the resultant at process temperature of 350˜750 C., and a nitride layer is deposited on the oxide layer.

Abstract: Titanium-containing films exhibiting excellent uniformity and step coverage are deposited on semiconductor wafers in a cold wall reactor which has been modified to discharge plasma into the reaction chamber. Titanium tetrabromide, titanium tetraiodide, or titanium tetrachloride, along with hydrogen, enter the reaction chamber and come in contact with a heated semiconductor wafer, thereby depositing a thin titanium-containing film on the wafer's surface. Step coverage and deposition rate are enhanced by the presence of the plasma. The use of titanium tetrabromide or titanium tetraiodide instead of titanium tetrachloride also increases the deposition rate and allows for a lower reaction temperature. Titanium silicide and titanium nitride can also be deposited by this method by varying the gas incorporated with the titanium precursors.

Abstract: A breakdown voltage of a capacitive element is improved by re-crystallizing a tungsten silicide film under a dielectric film. In forming the capacitive element which uses a polycrystalline silicon film and the tungsten silicide film as a lower electrode, the tungsten silicide film is re-crystallized by heating using an RTA (Rapid Thermal Annealing) system before forming a silicon oxide film used as the dielectric film. By doing so, an interface between the silicon oxide film and the tungsten silicide film is prevented from becoming uneven and a breakdown voltage of the dielectric film is improved drastically. Thus an amount of electric charge stored in the capacitive element is increased as well as it is made possible that the capacitive element is applied to a semiconductor device operating at higher voltage.

Abstract: A method of forming a conductive metal silicide by reaction of metal with silicon is described. A method includes providing a semiconductor substrate with an exposed elemental silicon-containing surface. At least one of a nitride, boride, carbide, or oxide-comprising layer is atomic layer deposited onto the exposed elemental silicon-containing surface to a thickness no greater than 15 Angstroms. This ALD-deposited layer is exposed to plasma and a conductive reaction layer including at least one of an elemental metal or metal-rich silicide is deposited onto the plasma-exposed layer. Metal of the conductive reaction layer is reacted with elemental silicon of the substrate effective to form a conductive metal silicide-comprising contact region electrically connecting the conductive reaction layer with the substrate. Other aspects and implementations are contemplated.

Abstract: A method of manufacturing a semiconductor device is disclosed wherein a WSiN layer is deposited in a contact hole as a barrier metal using an ALD process. A tungsten layer is deposited on the WSiN layer in the nucleation stage thereof. Then, using a CVD process, the contact hole is completely filled with a tungsten layer. The WSiN layer is continuously and uniformly deposited in the contact hole having high aspect ratio, and the tungsten layer in the nucleation stage can be continuously and uniformly deposited on the WSiN layer, thus completely filling the contact hole with a tungsten layer deposited by the CVD process.

Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain regions and on the gate. Trenches are formed in the semiconductor substrate around the gate. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.

Abstract: A bumped wafer for use in making a chip device. The bumped wafer includes two titanium layers sputtered alternatingly with two copper layers over a non-passivated die. The bumped wafer further includes under bump material under solder bumps contained thereon.

Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.

Abstract: Methods for fabricating a semiconductor device with salicide are disclosed. One example method includes forming a gate electrode structure having a gate oxide film, a gate electrode, and a protection film stacked on a substrate in succession, and gate spacers on sidewalls of the stack of the gate oxide film, the gate electrode, and the protection film; forming an insulating film on an entire surface of the substrate, the insulating film exposing upper portions of the gate electrode and the gate spacers; and removing portions of the protection film and the gate spacers, to expose an upper portion of the gate electrode. The example method may also include applying a salicide forming metal on an entire surface of the substrate; and performing a heat treatment process to form salicide on the gate electrode and the gate spacers, selectively.

Abstract: This invention offers a manufacturing method which does not cause a reduction in thickness of a silicon substrate or a carbon contamination in forming a transistor having an LDD stricture and silicide layers formed by a salicide technology. After a gate electrode is formed on the silicon substrate through a gate insulation film, an insulation film made of the same material as the gate insulation film is formed on the gate electrode. A first insulation film made of a material different from the material of the gate insulation film and the insulation film on the gate electrode and a second insulation film made of the same material as the material of the gate insulation film and the insulation film on the gate electrode are formed over the silicon substrate. Spacers made of the second insulation film are formed by dry-etching. Then the LDD structure and openings for forming the silicide layers are formed using wet-etching.

Abstract: A method (and resulting structure) for fabricating a silicide for a semiconductor device, includes depositing a metal or an alloy thereof on a silicon substrate, reacting the metal or the alloy to form a first silicide phase, etching any unreacted metal, depositing a silicon cap layer over the first silicide phase, reacting the silicon cap layer to form a second silicide phase, for the semiconductor device, and etching any unreacted silicon. The substrate can be either a silicon-on-insulator (SOI) substrate or a bulk silicon substrate.

Abstract: A method (and structure) of forming a vertically-self-aligned silicide contact to an underlying SiGe layer, includes forming a layer of silicon of a first predetermined thickness on the SiGe layer and forming a layer of metal on the silicon layer, where the metal layer has a second predetermined thickness. A thermal annealing process at a predetermined temperature then forms a silicide of the silicon and metal, where the predetermined temperature is chosen to substantially preclude penetration of the silicide into the underlying SiGe layer.

Abstract: It is a general object of the present invention to provide an improved method of fabrication in the formation of an improved copper metal diffusion barrier layer having the structure, W/WSiN/WN, in single and dual damascene interconnect trench/contact via processing with 0.10 micron nodes for MOSFET and CMOS applications. The diffusion barrier is formed by depositing a tungsten nitride bottom layer, followed by an in situ SiH4/NH3 or SiH4/H2 soak forming a WSiN layer, and depositing a final top layer of tungsten. This invention is used to manufacture reliable metal interconnects and contact vias in the fabrication of MOSFET and CMOS devices for both logic and memory applications and the copper diffusion barrier formed, W/WSiN/WN, passes a stringent barrier thermal reliability test at 400° C. Pure single barrier layers, i.e., single layer WN, exhibit copper punch through or copper spiking during the stringent barrier thermal reliability test at 400° C.

Abstract: A method of forming an integrated circuit, and an integrated circuit, are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.

Abstract: A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum nitride barrier layer, on a substrate by using an atomic layer deposition process (a vapor deposition process that includes a plurality of deposition cycles) with a refractory metal precursor compound, an organic amine, and an optional silicon precursor compound.

Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a layer of a first material (layer 622 of FIG. 6a) over the substrate; forming a photoresist layer (layer 626 of FIG. 6b) over the layer of the first material; patterning the layer of the first material; removing the photoresist layer after patterning the layer of the first material; and subjecting the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen or deuterium so as to remove residue from the first material. Preferably, the step of removing the photoresist layer is performed by subjecting the semiconductor wafer to the plasma which incorporates a gas which substantially includes hydrogen or deuterium.

Abstract: A method of detecting silicide encroachment to the sidewalls of a gate electrode includes forming silicide at a device, with sidewall spacers defining a desired separation of the silicide from the sidewalls of the gate electrode. After silicide formation, the sidewall spacers are removed and line-of-sight monitoring is performed of the region previously obscured by the sidewall spacers, thereby permitting detection of silicide encroachment.