Abstract: Methods of forming refractory metal suicide components are described. In accordance with one implementation, a refractory metal layer is formed over a substrate. A silicon-containing structure is formed over the refractory metal layer and a silicon diffusion restricting layer is formed over at least some of the silicon-containing structure. The substrate is subsequently annealed at a temperature which is sufficient to cause a reaction between at least some of the refractory metal layer and at least some of the silicon-containing structure to at least partially form a refractory metal silicide component. In accordance with one aspect of the invention, a silicon diffusion restricting layer is formed over or within the refractory metal layer in a step which is common with the forming of the silicon diffusion restricting layer over the silicon-containing structure.

Abstract: The present invention provides metallic films containing a Group IVB or VB metal, silicon and optionally nitrogen by utilizing atomic layer deposition (ALD). In particularly, the present invention provides a low temperature thermal ALD method of forming metallic silicides and a plasma-enhanced atomic layer deposition (PE-ALD) method of forming metallic silicon nitride film. The methods of the present invention are capable of forming metallic films having a thickness of a monolayer or less on the surface of a substrate. The metallic films provided in the present invention can be used for contact metallization, metal gates or as a diffusion barrier.

Abstract: A cluster tool and a number of different processes for making a cobalt-silicide material are disclosed. Combinations of alloyed layers of Co—Ti—along with layers of Co—are arranged and heat treated so as to effectuate a silicide reaction. The resulting structures have extremely low resistance, and show little line width dependence, thus making them particularly attractive for use in semiconductor processing. A cluster tool is configured with appropriate sputter targets/heat assemblies to implement many of the needed operations for the silicide reactions, thus resulting in higher savings, productivity, etc.

Abstract: The present invention provides a method of fabricating a semiconductor device, which could advance the commercialization of semiconductor devices with a copper interconnect. In a process of metal interconnect line fabrication, a TiN thin film combined with an Al intermediate layer is used as a diffusion barrier on trench or via walls. For the formation, Al is deposited on the TiN thin film followed by copper filling the trench. Al diffuses to TiN layer and reacts with oxygen or nitrogen, which will stuff grain boundaries efficiently, thereby blocking the diffusion of copper successfully.

Abstract: A cobalt-containing film on a silicon-containing conductive region, and a titanium-rich capping layer is formed on cobalt-containing film. The atomic % ratio of titanium to other elements (if any) in the titanium-rich capping layer is more than one (1). The resultant structure is annealed so that cobalt of the cobalt-containing film and silicon of the silicon-containing conductive region react with each other to form a cobalt silicide film. When the formation of the cobalt-containing film is carried out at a high temperature, a diffusion restraint interface film is also formed.

Abstract: A method of preventing formation of titanium oxide within a semiconductor device structure during a high temperature treatment of the device structure includes forming a passivation layer to preclude formation of titanium oxide at a titanium/oxide interface of a semiconductor device structure. The method includes providing a substrate assembly including at least an oxide region and forming a layer of titanium over a surface of the oxide region. The oxide region surface is treated with a plasma comprising nitrogen prior to forming the titanium layer so as to form a passivation layer upon which the titanium layer is formed. A thermal treatment is performed on the substrate assembly with the passivation layer substantially inhibiting diffusion of oxygen from the oxide layer during the thermal treatment of the substrate assembly. Generally, the passivation layer comprises SixOyNz.

Abstract: A TiSiN film is used as a barrier metal layer for a semiconductor device to prevent the diffusion of Cu. The TiSiN film is formed by a plasma CVD process or a thermal CVD process. TiCl4 gas, a silicon hydride gas and NH3 gas are used as source gases for forming the TiSiN film by the thermal CVD process. TiCl4 gas, a silicon hydride gas, H2 gas and N2 gas are used as source gases for forming a TiSiN film by the plasma CVD process.

Abstract: Embodiments of the present invention generally relate to an apparatus and method of integration of titanium and titanium nitride layers. One embodiment includes providing one or more cycles of a first set of compounds, providing one or more cycles of a second set of compounds, and providing one or more cycles of a third set of compounds. One cycle of the first set of compounds includes introducing a titanium precursor and a reductant. One cycle of the second set of compounds includes introducing the titanium precursor and a silicon precursor. One cycle of the third set of compounds includes introducing the titanium precursor and a nitrogen precursor. Another embodiment includes depositing a titanium layer utilizing titanium halide. Then, a passivation layer is deposited over the titanium layer utilizing titanium halide. The passivation layer may comprise titanium silicide, titanium silicon nitride, and combinations thereof.

Abstract: The semiconductor device of the present invention includes: a substrate; a first conductor film supported by the substrate; an insulating film formed on the substrate to cover the first conductor film, an opening being formed in the insulating film; and a second conductor film, which is formed within the opening of the insulating film and is in electrical contact with the first conductor film. The second conductor film includes: a silicon-containing titanium nitride layer formed within the opening of the insulating film; and a metal layer formed over the silicon-containing titanium nitride layer. The metal layer is mainly composed of copper.

Abstract: An aluminum-containing film having an oxygen content within the film. The aluminum-containing film is formed by introducing hydrogen gas and oxygen gas along with argon gas into a sputter deposition vacuum chamber during the sputter deposition of aluminum or aluminum alloys onto a semiconductor substrate. The aluminum-containing film so formed is hillock-free and has low resistivity, relatively low roughness compared to pure aluminum, good mechanical strength, and low residual stress.

Abstract: A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has silicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area at the N+/P+ junction of the polysilicon line, and silicide is not present on the N+ active area and the P+ active area. The presence of this selective silicidation creates a beneficial low-resistance connection between the N+ region of the polysilicon line and the P+ region of the polysilicon line. The absence of silicidation on the N+ and P+ active areas, specifically on the PFET and NFET structures, prevents current leakage associated with the silicidation of devices.

Abstract: A process for fabricating interconnects is provided. First, a substrate having a dielectric layer and silicon-containing mask layer on the dielectric layer is provided. The dielectric layer is patterned to form an opening. Thereafter, a metallic glue layer is formed over the silicon-containing mask layer and the interior surfaces of the opening. A metallic layer is formed over the substrate to fill the opening and cover the metallic glue layer. A thermal treatment process is next carried out so that the metallic glue layer reacts with the silicon-containing mask layer to form a metal silicide layer. A portion of the metallic layer is removed to expose the metal silicide layer. A solution mixture containing hydrogen peroxide, sulfuric acid, water and hydrofluoric acid is used to remove the metal silicide layer. The silicon-containing mask layer is also removed to expose the dielectric layer.

Abstract: A metallization stack is provided for use as a contact structure in an integrated MEMS device. The metallization stack includes a titanium-tungsten adhesion and barrier layer formed with a platinum layer formed on top. The platinum feature is formed by sputter etching the platinum in argon, followed by a wet etch in aqua regia using an oxide hardmask. Alternatively, the titanium-tungsten and platinum layers are deposited sequentially and patterned by a single plasma etch process with a photoresist mask.

Abstract: A semiconductor device that includes cobalt-silicide based contacts is disclosed, as well as a process for making the same. Combinations of alloyed layers of Co—Ti— along with layers of Co— are arranged and heat treated so as to effectuate a silicide reaction on a silicon substrate. The resulting structures have extremely low resistance, and show little line width dependence, thus making them particularly attractive for use in semiconductor devices and processes.

Abstract: A method for forming salicides with lower sheet resistance and increased sheet resistance uniformity over a semiconductor process wafer including providing a semiconductor process wafer having exposed silicon containing areas at a process surface; depositing a metal layer including at least one of cobalt and titanium over the process surface; carrying out at least one thermal annealing process to react the metal layer and silicon to form a metal silicide over the silicon containing areas; and, wet etching unsilicided areas of the metal layer with a wet etching solution including phosphoric acid (H3PO4), nitric acid (HNO3), and a carboxylic acid to leave salicides covering silicon containing areas at the process surface.

Abstract: There is provided a method of forming a barrier metal which is designed to be interposed between a metal layer and an insulating layer, both constituting a multi-layered structure of semiconductor device, the method comprising the steps of positioning a substrate having the insulating layer formed thereon at a predetermined position inside a processing vessel forming a processing space, and alternately introducing a gas containing a refractory metallic atom, a gas containing Si atom and a gas containing N atom into the processing vessel under a predetermined processing pressure, thereby allowing a refractory metal nitride or a refractory metal silicon nitride to be deposited on the insulating layer by way of atomic layer deposition.

Abstract: A method of manufacturing a high performance MOS device and transistor gate stacks comprises forming a gate dielectric layer over a semiconductor substrate; forming a barrier layer over the gate dielectric layer by an ALD type process; and forming a gate electrode layer over the barrier layer. The method enables the use of hydrogen plasma, high energy hydrogen radicals and ions, other reactive radicals, reactive oxygen and oxygen containing precursors in the processing steps subsequent to the deposition of the gate dielectric layer of the device. The ALD process for forming the barrier layer is performed essentially in the absence of plasma and reactive hydrogen radials and ions. This invention makes it possible to use oxygen as a precursor in the deposition of the metal gates. The barrier film also allows the use of hydrogen plasma in the form of either direct or remote plasma in the deposition of the gate electrode.

Abstract: A GaN layer 31 is subjected to etching, so as to form an island-like structure having, for example, a dot, stripe, or grid shape, thereby providing a trench/mesa structure including mesas and trenches whose bottoms sink into the surface of a substrate base 1. Subsequently, a GaN layer 32 is lateral-epitaxially grown with the top surfaces of the mesas and sidewalls of the trenches serving as nuclei, to thereby fill upper portions of the trenches (depressions of the substrate base 1), and then epitaxial growth is effected in the vertical direction. In this case, propagation of threading dislocations contained in the GaN layer 31 can be prevented in the upper portion of the GaN layer 32 that is formed through lateral epitaxial growth.

Abstract: A method of forming a conductive structure having a length that is less than the length define by photolithographic patterning. A silicon layer (12) is formed in a MeOx dielectric layer (11) is photolithographically patterned to a predetermined first length. A metal layer (31) is formed conformally to at least the sidewalls of the silicon layer and then is reacted with the silicon to form a metal silicide (41). In particular, metal silicide abutments (411,412) are formed contiguous to sidewalls (421,422) of a reduced conductor (42). The remaining metal layer and the metal silicide are etched away, resulting in a conductor having predetermined second length that is less than the predetermined first length.

Abstract: A system and method to form a stacked barrier layer for copper contacts formed on a substrate. The substrate is serially exposed to first and second reactive gases to form an adhesion layer. Then, the adhesion layer is serially exposed to third and fourth reactive gases to form a barrier layer adjacent to the adhesion layer. This is followed by deposition of a copper layer adjacent to the barrier layer.

Abstract: A memory device and method of manufacturing thereof, wherein a silicide material is selectively formed over active regions of a memory device. A silicide material may also be formed on the top surface of wordlines adjacent the active regions during the selective silicidation process. A single nitride insulating layer is used, and portions of the workpiece are covered with photoresist during the formation of the silicide material.

Abstract: An SixNy or SiOxNy liner is formed on a MOS device. Cobalt is then deposited and reacts to form an epitaxial CoSi2 layer underneath the liner. The CoSi2 layer may be formed through a solid phase epitaxy or reactive deposition epitaxy salicide process. In addition to high quality epitaxial CoSi2 layers, the liner formed during the invention can protect device portions during etching processes used to form device contacts. The liner can act as an etch stop layer to prevent excessive removal of the shallow trench isolation, and protect against excessive loss of the CoSi2 layer.

Abstract: A method for forming a metal interconnect comprises exposing a dielectric layer to an etch chemistry containing nitrogen-containing compound such as NH3, NF3 or N2O. The nitrogen-containing compound provides selectivity and/or profile control comparable to that provided by N2, while avoiding poisoning of photoresist by embedded N2.

Abstract: A method of forming a barrier metal film formed of a nitride film including tungsten by thermal CVD. The method includes positioning a substrate in a processing vessel and forming a WSi film on one side of the substrate by supplying a process gas including WF6 gas and at least one of SiR4 gas, SiH2Cl2 gas and Si2H6 gas into the processing vessel while a processing pressure in the processing vessel is maintained. The method also includes shutting off the supplying of the process gas into the processing vessel and completely removing the process gas from the processing vessel by supplying a purging gas into the processing vessel after the shutting off the supplying. The WSi film is nitrided by supplying NH3 gas or MMH gas into the processing vessel from which the process gas has been removed, to form a WSixNy film.

Abstract: The invention includes methods of forming metal silicide having bulk resistance of less than 30 micro-ohms-centimeter. The metal of the metal silicide can be selected from Groups 3, 4, 8, 9 and 10 of the periodic table, with an exemplary metal being titanium. An exemplary method includes forming a titanium-containing layer directly against tantalum silicide. After the titanium-containing layer is formed directly against the tantalum silicide, titanium of the titanium-containing layer is converted to titanium silicide. Constructions formed in accordance with methodology of the present invention can be incorporated into circuitry associated with semiconductor devices, such as, for example, wordlines and bitlines.

Abstract: A selfaligned process for a flash memory comprises applying a solution with a high etch selectivity to etch the sidewall of the tungsten silicide in the gate structure of the flash memory during a clean process before forming a spacer for the gate structure. This process prevents the gate structure from degradation caused by thermal stress.

Abstract: A silicide method for integrated circuit and semiconductor device fabrication wherein a layer of nickel is formed over at least one silicon region of a substrate and a layer of cobalt is formed over the nickel layer. The cobalt/nickel bi-layer is then annealed to transform the bi-layer to a bi-silicide film having a cobalt-rich silicide portion and a nickel-rich silicide portion.

Abstract: An NMOS ESD clamping device and methods for making the same are disclosed in which the device includes N type drain and source regions formed in a semiconductor substrate and a gate overlying a P-type channel region in the substrate between the source and drain regions. A first silicide region is formed in the drain and/or the source region with a first thickness. A second thin silicide region is formed in the substrate between the gate and the drain having a second thickness less than the first thickness, wherein the thin silicide increases the ESD current clamping capability of the device to provide improved ESD circuit protection.

Abstract: After a silicidation blocking pattern is formed on a substrate including silicon, the silicidation blocking pattern is hardened by a thermal annealing process. The substrate is rinsed to remove a native oxide film formed on the substrate, and then a silicide film is formed on a portion of the substrate exposed by the silicidation blocking pattern. The silicide film can thus be formed in an exact portion of the substrate, and the substrate is not damaged during rinsing.

Abstract: In an apparatus and method for forming a silicide wire in a semiconductor device, a first gate film is provided with a first silicide layer in a first region (for example a wiring region of the device that is relatively thicker than a second silicide layer on a second gate film in a second region of the device. In this manner, the operating speed of the semiconductor device is improved.

Abstract: The present invention provides a technique for forming a metal silicide, such as a cobalt disilicide, even at extremely scaled device dimensions without unduly degrading the film integrity of the metal silicide. To this end, an ion implantation may be performed, advantageously with silicon, prior to a final anneal cycle, thereby correspondingly modifying the grain structure of the precursor of the metal silicide.

Abstract: The polysilicon gate electrode of a MOS transistor may be substantially completely converted into a metal silicide without sacrificing the drain and source junctions in that a thickness of the polysilicon layer, for forming the gate electrode, is targeted to be substantially converted into metal silicide in a subsequent silicidation process. The gate electrode, substantially comprised of metal silicide, offers high conductivity even at critical dimensions in the deep sub-micron range, while at the same time the effect of polysilicon gate depletion is significantly reduced. Manufacturing of the MOS transistor, having the substantially fully-converted metal silicide gate electrode, is essentially compatible with standard MOS process technology.

Abstract: A thick metal layer is formed on a semiconductor integrated circuit in multiple different deposition chambers. A first portion of the metal layer is formed in a first deposition chamber, the first thickness being approximately half the target thickness. The substrate is then removed from the first chamber and transported to a second chamber. The deposition of the same metal layer continues in a second chamber, having the same grain structure and orientation. The second portion of the metal layer is grown to achieve the final thickness. By using two different deposition chambers to form the single metal layer, layers in excess of 25,000 angstroms in thickness can be obtained.

Abstract: A semiconductor device has a SALICIDE structure with low leakage currents, while maintaining shallow source and drain regions. A method of manufacturing the semiconductor device includes forming source and drain regions in a first semiconductor layer, the source region and the drain region being separated from each other forming a gate insulating film between the source region and the drain region on the first semiconductor layer and a gate electrode on the gate insulating film, forming a metal silicide layer having a first compound phase on the source region, the drain region and the gate electrode, forming a second semiconductor layer on the metal silicide layer having the first compound phase where the second semiconductor layer is adapted to react with the metal silicide layer, and forming a metal silicide layer having a second compound phase by causing the second semiconductor layer and the metal silicide layer having the first compound phase to selectively react with each other.

Abstract: Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.

Abstract: To provide a technique for manufacturing a wiring line having a low resistance and a high heat resistance so as to make an active matrix type display device larger and finer. The wiring line is constructed of a laminated structure of a refractory metal, a low resistance metal and a refractory metal, and the wiring line is further protected with an anodized film. As a result, it is possible to form the wiring line having the low resistance and the high heat resistance and to form a contact with an upper line easily.

Abstract: A MOS field effect transistor for reducing the resistance between a source and a drain includes a gate insulation layer and a gate electrode sequentially formed on a semiconductor substrate includes deep source/drain regions formed in upper portions of the semiconductor substrate at both sides of the gate electrode. Source/drain extension regions are formed in upper portions of the semiconductor substrate extending from the deep source/drain regions toward a channel region below the gate electrode to be thinner than the deep source/drain regions. A first silicide layer having a first thickness is formed on the surface of each of the deep source/drain regions. A second silicide layer having a second thickness thinner than the first thickness of the first silicide layer is formed to extend from the first silicide layer in a predetermined upper portion of each of the source/drain extension regions.

Abstract: A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.

Abstract: A method of reducing the contact resistance of metal suicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g.

Abstract: A gate electrode structure in a semiconductor device has a doped polysilicon (DOPOS) film, a tungsten silicide film, a tungsten silicide nitride film, a tungsten nitride film and a tungsten film consecutively as viewed from the substrate. The tungsten silicide nitride film is formed between the tungsten silicide film and the tungsten nitride film by a plurality of heat treatments. The tungsten silicide nitride film has a small thickness of 2 to 5 nm and has a lower interface resistance for achieving a low-resistance gate electrode, suited for a higher-speed operation of the semiconductor device.

Abstract: Disclosed is a method for manufacturing a silicide layer of semiconductor device. The disclosed comprises the steps of: depositing a lower metal layer on the surface of semiconductor substrate and then, performing a plasma treatment; and depositing an upper metal layer on the plasma-treated lower metal layer and then, performing a thermal treatment process, thereby forming a silicide layer on the surface of semiconductor substrate.

Abstract: A method for forming an epitaxial cobalt silicide layer on a MOS device includes sputter depositing cobalt in an ambient to form a first layer of cobalt suicide on a gate and source/drain regions of the MOS device. Subsequently, cobalt is sputter deposited again in an ambient of argon to increase the thickness of the cobalt silicide layer to a second thickness.

Abstract: A method (and resultant structure) of forming a semiconductor device, includes forming a metal-back-gate over a substrate and a metal back-gate, forming a passivation layer on the metal back-gate to prevent the metal back-gate from reacting with radical species, and providing an intermediate gluing layer between the substrate and the metal back-gate to enhance adhesion.

Abstract: Tungsten silicide layers are formed on a substrate and a semiconductor component has deep trench capacitors with a filling of tungsten silicide. The tungsten silicide layers are deposited on the substrate at a temperature of less than 400° C. and at a pressure of less than 10 torr from the vapor phase. The vapor phase hs a tungsten-containing precursor substance and a silicon-containing precursor substance. The molar ratio of the silicon-containing precursor compound to the tungsten-containing precursor compound in the vapor phase is selected to be greater than 500.

Abstract: It is a general object of the present invention to provide an improved method of fabrication in the formation of an improved copper metal diffusion barrier layer having the structure, W/WSiN/WN, in single and dual damascene interconnect trench/contact via processing with 0.10 micron nodes for MOSFET and CMOS applications. The diffusion barrier is formed by depositing a tungsten nitride bottom layer, followed by an in situ SiH4/NH3 or SiH4/H2 soak forming a WSiN layer, and depositing a final top layer of tungsten. This invention is used to manufacture reliable metal interconnects and contact vias in the fabrication of MOSFET and CMOS devices for both logic and memory applications and the copper diffusion barrier formed, W/WSiN/WN, passes a stringent barrier thermal reliability test at 400° C. Pure single barrier layers, i.e., single layer WN, exhibit copper punch through or copper spiking during the stringent barrier thermal reliability test at 400° C.

Abstract: A process of siliciding uses alloys to reduce the adverse affects of germanium on silicide regions. The alloy can include nickel and at least one of vanadium, tantalum, and tungsten. The process can utilize one or two annealing steps. The process allows better silicidation in SMOS devices. The silicided regions can be provided above a silicon/germanium substrate.

Abstract: A method of fabricating contact holes on a semiconductor chip with a plurality of gates and a first mask layer includes filling a dielectric layer into the inter-gate space of two gates, polishing the dielectric layer until the surface of the dielectric layer is coplanar with the gates, depositing a second mask layer, etching the second mask layer to form a bit line opening in an array area and simultaneously forming a gate opening and a substrate opening in a periphery area, removing a portion of the dielectric layer through the bit line opening and the substrate opening to form a bit line contact hole and a substrate contact hole, filling a metal layer into the bit line contact hole and the substrate contact hole, and etching the first mask layer through the gate opening to form a gate contact hole.

Abstract: A semiconductor device with an epitaxially grown titanium silicide layer having a phase of C49 and a method for fabricating the same. The titanium silicide layer has a predetermined interfacial energy that does not transform the phase of the titanium layer, and thus, occurrences of agglomeration of the titanium layer and a grooving phenomenon can be prevented. The semiconductor device includes: a silicon layer; an insulation layer formed on the silicon layer, wherein a partial portion of the insulation layer is opened to form a contact hole exposing a partial portion of the silicon layer. An epitaxially grown titanium silicide layer having a phase of C49 and is formed on the exposed silicon substrate disposed within the contact hole; and a metal layer is formed on an upper surface of the titanium silicide layer.

Abstract: Methods for reducing the contact resistance presented by the interface between a silicide and a doped silicon region are presented. In a first method, a silicide layer and a doped silicon region form an interface. Either a damage-only species or a heavy, metal is implanted through the silicide layer into the doped silicon region immediately adjacent the interface. In a second method, a second metal is added to the refractory metal before formation of the silicide. After annealing the refractory metal and the doped silicon region, the second metal diffuses into the doped silicion region immediately adjacent the interface without forming additional phases in the silicide.

Abstract: The present invention is generally directed to various methods of forming metal silicide regions on transistors based upon gate critical dimensions. In one illustrative embodiment, the method comprises forming a layer of refractory metal above a plurality of transistors, reducing a thickness of at least a portion of the layer of refractory metal above at least some of the transistors and performing at least one anneal process to form metal silicide regions above the transistors. In another illustrative embodiment, the method comprises forming a layer of refractory metal above the plurality of transistors, reducing the thickness of the layer of refractory metal above a first of the transistors having a gate electrode with a critical dimension that is less than a critical dimension of a gate electrode structure of another of the plurality of transistors, and performing at least one anneal process to form metal silicide regions on the plurality of transistors.