Abstract: Titanium-containing films exhibiting excellent uniformity and step coverage are deposited on semiconductor wafers in a cold wall reactor which has been modified to discharge plasma into the reaction chamber. Titanium tetrabromide, titanium tetraiodide, or titanium tetrachloride, along with hydrogen, enter the reaction chamber and come in contact with a heated semiconductor wafer, thereby depositing a thin titanium-containing film on the wafer's surface. Step coverage and deposition rate are enhanced by the presence of the plasma. The use of titanium tetrabromide or titanium tetraiodide instead of titanium tetrachloride also increases the deposition rate and allows for a lower reaction temperature. Titanium silicide and titanium nitride can also be deposited by this method by varying the gas incorporated with the titanium precursors.

Abstract: A novel method for forming a C54 phase titanium disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A titanium layer is deposited overlying the silicon regions to be silicided. The substrate is subjected to a first annealing whereby the titanium is transformed to phase C40 titanium disilicide where it overlies the silicon regions and wherein the titanium not overlying the silicon regions is unreacted. The unreacted titanium layer is removed. The substrate is subjected to a second annealing whereby the phase C40 titanium disilicide is transformed to phase C54 titanium disilicide to complete formation of a phase 54 titanium disilicide film in the manufacture of an integrated circuit.

Abstract: In a semiconductor device having a cobalt silicide film, at least nickel or iron is contained in the cobalt silicide film for preventing the rise of resistance incidental to thinning of the film.

Abstract: A method of ensuring against deterioration of an underlying silicide layer over which a refractory material layer is deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD) is realized by first providing a continuous polysilicon layer prior to the refractory material deposition. The continuous polysilicon layer, preferably no thicker than 50 Å, serves a sacrificial purpose and prevents interaction between any fluorine that is released during the refractory material deposition step from interacting with the underlying silicide.

Abstract: Metallurgy structures for input/output pads of an electronic devices can be adapted to receive both solder and wire bonds. First and second metallurgy structures, for example, can be provided on respective first and second input/output pads of an electronic device such that the first and second common metallurgy structures have a shared structure adapted to receive both solder and wire bonds. A solder bond can thus be applied to the first metallurgy structure, and a wire bond can be applied to the second metallurgy structure.

Abstract: Methods of forming refractory metal suicide components are described. In accordance with one implementation, a refractory metal layer is formed over a substrate. A silicon-containing structure is formed over the refractory metal layer and a silicon diffusion restricting layer is formed over at least some of the silicon-containing structure. The substrate is subsequently annealed at a temperature which is sufficient to cause a reaction between at least some of the refractory metal layer and at least some of the silicon-containing structure to at least partially form a refractory metal silicide component. In accordance with one aspect of the invention, a silicon diffusion restricting layer is formed over or within the refractory metal layer in a step which is common with the forming of the silicon diffusion restricting layer over the silicon-containing structure.

Abstract: A method and apparatus for forming a barrier metal layer in semiconductor devices are disclosed. A disclosed method for forming a barrier metal layer in a semiconductor device forms an interlayer insulating layer on a front face of a semiconductor substrate having a contact area and patterns the interlayer insulating layer to open the contact area. The disclosed method further places the semiconductor substrate in a chamber, injects reactant gas and precursor into the chamber, transforms the gas into plasma gas and causes the plasma gas to react with the precursor to form a single TiSiN film covering the contact area.

Abstract: The present invention is related to a method for forming a titanium silicide contact in a semiconductor device capable of minimizing consumptions of a silicon substrate and performing a low-temperature deposition through the use of an atomic layer deposition technique. The method includes the steps of: forming an inter-layer insulation layer on a silicon substrate; forming a contact hole exposing a portion of the silicon substrate by selectively etching the inter-layer insulation layer; forming a titanium silicide layer on the exposed portion of the silicon substrate by employing an atomic layer deposition technique using a source gas of titanium tetrachloride and a silicon-containing gas; forming a metal barrier layer on the resulting structure; and forming a contact plug by filling a conductive material into the contact hole and planarizing the deposited conductive material.

Abstract: Disclosed is a method for forming bit lines of a semiconductor device capable of solving an issue on overlay between a bit line contact and a bit line when bit lines of DRAM are formed.

Abstract: Metal nitride and metal oxynitride extrusions often form on metal suicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etch comprising an oxidizing agent and a chelating agent selectively removes the extrusions from a wordline in a memory array. In another embodiment, the wet etch includes a base that adjusts the pH of the etch to selectively remove certain extrusions relative to other substances in the wordline. Accordingly, new metal silicide structures can be used to form novel wordlines and other types of integrated circuits.

Abstract: A cluster tool and a number of different processes for making a cobalt-silicide material are disclosed. Combinations of alloyed layers of Co—Ti— along with layers of Co— are arranged and heat treated so as to effectuate a silicide reaction. The resulting structures have extremely low resistance, and show little line width dependence, thus making them particularly attractive for use in semiconductor processing. A cluster tool is configured with appropriate sputter targets/heat assemblies to implement many of the needed operations for the silicide reactions, thus resulting in higher savings, productivity, etc.

Abstract: The present invention provides a semiconductor device having a metal suicide layer and a method for forming the metal silicide layer, the semiconductor device having a metal silicide-semiconductor contact structure, wherein the semiconductor device includes a substrate, an insulation layer with an opening, in which a metal silicide layer is formed using a native metal silicide with a first phase and a second phase, upon which a conductive layer is formed. The second phase has a first stoichiometrical composition ratio different from a second stoichiometrical composition ratio of the first phase. A reaction between the metal silicide layer of the first phase and the silicon results in the metal silicide layer of the second phase having high phase stability and low resistance.

Abstract: A semiconductor device having a bump electrode comprising a substrate having a dielectric layer formed thereon, an aluminum contact pad on the substrate wherein at least a portion of the aluminum contact pad is exposed through the dielectric layer on the substrate. The aluminum contact pad is provided with an under bump metallurgy including a aluminum layer formed on the exposed portion of the aluminum contact pad, a nickel-vanadium layer formed on the aluminum layer and a titanium layer formed on the nickel-vanadium layer. A gold bump formed on the titanium layer acts as the bump electrode.

Abstract: The present invention provides a system for preventing excess silicon consumption in a semiconductor wafer by depositing a metal layer (114) on top of a native oxide layer above a silicide layer (110) of the semiconductor wafer and then reducing the native oxide layer to form low resistance contacts. The native oxide layer is reduced using a rapid thermal annealing process within a temperature range to preserve the integrity of the silicide layer (110) and reduce excess silicon consumption. The temperature range can be greater than 350° C. and less than 615° C., but is optimal between 485° C. to 550° C.

Abstract: A method for forming a cobalt silicide layer employs a sequential treatment of a silicon substrate with a hydrofluoric acid material followed by a wet chemical oxidant material. A cobalt material layer is then formed upon the sequentially treated silicon substrate and the silicon substrate/cobalt material layer laminate is thermally annealed to form a cobalt silicide layer. Use of the wet chemical oxidant material for treating the silicon substrate provides the cobalt silicide layer with enhanced electrical properties.

Abstract: A versatile system for forming diffusion barriers in semiconductor processing that simplifies device processing, utilizing existing production compounds and materials while resulting in uniform and proper device structuring, is disclosed, providing a system using a reactive plasma to selectively form diffusion barriers and provide selective oxidation.

Abstract: The present invention provides a method for forming a metal silicide layer in an active area of the semiconductor device. The method for forming the metal silicide layer includes: forming a source/drain junction area on a silicon substrate; forming an attack protection layer on the source/drain junction area, wherein the attack protection layer is electrically conductive and prevents a silicon substrate attack caused by chlorine (Cl) gas; forming a titanium (Ti) layer over the attack protection layer through a low pressure chemical vapor deposition (LPCVD) process using a source gas of TiCl4; and diffusing the Ti layer into the attack protection layer to thereby form a metal silicide layer.

Abstract: A method is presented for forming a transistor gate structure. A gate oxide layer is formed. Gate material is deposited on the gate oxide layer. A layer of silicon oxynitride is deposited on the gate material. The layer of silicon oxynitride, the gate material and the gate oxide layer are etched to form a gate structure. A silicon oxynitride region remains on top of the gate structure. A wet chemical process is performed to remove the silicon oxynitride region from the top of the gate structure. After performing the wet chemical process, spacers are formed around the gate structure.

Abstract: A Cu interconnect, e.g.; a dual damascene structure, is formed with improved electromigration resistance and increased via chain yield by depositing a barrier layer in an opening by CVD, depositing a flash layer of &agr;-Ta by PVD, at a thickness less than 30 Å, on the bottom of the barrier layer, depositing a seedlayer and then filling the opening with Cu. Embodiments include depositing a thin &agr;-Ta layer, as at a thickness less than 10 Å, and/or as discontinuous regions of clusters of atoms on sides of the opening.

Abstract: A gate oxide layer and a gate are sequentially formed on a substrate, and a source/drain extension is formed in the substrate thereafter. A liner layer is then formed to cover the substrate, and a first dielectric layer and a second dielectric layer are sequentially formed on the liner layer. By performing an etching process, a L-shaped spacer is formed on either side of the gate. Portions of the liner layer uncovered by the L-shaped spacer are then removed, and a step source/drain extension and a source/drain are simultaneously formed in the substrate thereafter. Finally, a salicide process is performed to form a silicide layer on the gate and on portions of the silicon substrate surface above the source/drain.

Abstract: An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a cobalt (Co) interface layer between the Ni and Si layers prior to the silicidation reaction. The cobalt interlayer regulates the flux of the Ni atoms through the cobalt/nickel/silicon alloy layer formed from the reaction of the cobalt interlayer with the nickel and the silicon so that the Ni atoms reach the Si interface at a similar rate, i.e., without any orientation preference, so as to form a uniform layer of nickel silicide. The nickel silicide may be annealed to form a uniform crystalline nickel disilicide. Accordingly, a single crystal nickel silicide on (100) Si or on amorphous Si is achieved wherein the nickel silicide has improved stability and may be utilized in ultra-shallow junction devices.

Abstract: A main electrode is connected to an n-type semiconductor layer selectively formed on a major surface of a silicon substrate. A silicide layer is interposed between the main electrode and the semiconductor layer. The silicide layer is heat-treated at 600° C. to 850° C. for at least 30 minutes, to have an epitaxial layer selectively epitaxially growing in a specific direction such as the <110> direction toward the semiconductor layer. Therefore, irregularities are formed on the interface between the suicide layer and the semiconductor layer. The interface resistivity between the silicide layer and the semiconductor layer is low due to the presence of the epitaxial layer, and besides the contact area of the interface is large due to the irregularities of the interface. Consequently, the contact resistance between the main electrode and the semiconductor layer is effectively reduced. Thus, the contact resistance between the main electrode and the semiconductor substrate is reduced.

Abstract: A method for providing gates of transistors with at least two different work functions utilizes a silicidation of two different metals at different times, silicidation for one gate and polysilicon for the other, or silicidation using a single metal with two differently doped silicon structures. Thus the problem associated with performing silicidation of two different metals at the same time is avoided. If the two metals have significantly different silicidation temperatures, the one with the lower temperature silicidation will likely have significantly degraded performance as a result of having to also experience the higher temperature required to achieve silicidation with the other metal.

Abstract: In one implementation, an etching process includes forming a carbon containing material over a substrate and plasma etching at a temperature of at least 400° C. using a hydrogen or oxygen containing plasma. In one implementation, a plasma etching process includes forming openings in a masking layer over a substrate and etching material beneath the masking through the openings. The masking layer is removed and the substrate is plasma etched at a temperature of at least 400° C. In one implementation, an etching process includes forming a residue over the substrate during a first etching and subsequently plasma etching to remove the residue. In one implementation, a chemical vapor deposition process includes positioning a semiconductor substrate within a plasma enhanced chemical vapor deposition reactor, plasma etching using a first gas chemistry, depositing a material over the substrate within the reactor using a second gas chemistry.

Abstract: The invention describes a method for the selective dry etching of tantalum and tantalum nitride films. Tantalum nitride layers (30) are often used in semiconductor manufacturing. The semiconductor substrate is exposed to a reducing plasma chemistry which passivates any exposed copper (40). The tantalum nitride films are selectively removed using an oxidizing plasma chemistry.

Abstract: A method of fabricating a semiconductor structure including the steps of: providing a silicon substrate having a surface; forming by atomic layer deposition a monocrystalline seed layer on the surface of the silicon substrate; and forming by atomic layer deposition one or more layers of a monocrystalline high dielectric constant oxide on the seed layer, where providing a substrate includes providing a substrate having formed thereon a silicon oxide, and wherein forming by atomic layer deposition a seed layer further includes depositing a layer of a metal oxide onto a surface of the silicon oxide, flushing the layer of metal oxide with an inert gas, and reacting the metal oxide and the silicon oxide to form a monocrystalline silicate.

Abstract: A method for manufacturing contact plug is disclosed. A dielectric layer is formed over a substrate having a conductive region. A contact opening is formed in the dielectric layer and exposing the conductive region within the opening. A first refractory metal layer is formed over the dielectric layer, and the sidewalls and bottom of the contact opening. A first refractory metal nitride layer is formed on the first refractory metal layer. A first plasma treatment step is carried out to transform the first refractory metal nitride layer into a first metal nitrided barrier layer. A thermal-process is carried out to form metal silicide on the conductive region. A second refractory metal nitride layer is formed on the first metal nitride barrier layer. A second plasma treatment step is carried out to transform the second refractory metal nitride layer into a second metal nitrided barrier layer.

Abstract: An impurity ion of a polarity opposite to that of an impurity ion forming an n-type diffusion layer is implanted into a lower portion of the n-type diffusion region in a region, in which n-channel type MISFET is to be formed, vertically with respect to a main surface of a semiconductor to form a first p-type pocket layer. Subsequently, an impurity of a p conduction type is implanted into a region between the n-type diffusion region and the first p-type pocket layer obliquely relative to the main surface of the semiconductor substrate to form a second p-type pocket layer. In this arrangement, the concentration of the impurity ion forming the second p-type pocket layer is made higher than the concentration of the impurity ion used to form the first p-type pocket layer.

Abstract: A composition and methods for using the composition in removing processing byproducts is provided. The composition can be non-aqueous or semi-aqueous. The non-aqueous composition includes a non-aqueous solvent and one or more components including a fluoride compound and a pyridine compound. The semi-aqueous composition includes glacial acetic acid and one or more components including a fluoride compound and a pyridine compound. The composition can be used in removing processing byproducts from substrate assembly, including MRAM devices, that include at least a metal containing region and processing byproducts, where removing the processing byproducts includes exposing the substrate assembly to the composition for a time effective to remove at least a portion of the processing byproducts.

Abstract: A method of forming (and apparatus for forming) tantalum suicide layers (including tantalum silicon nitride layers), which are typically useful as diffusion barrier layers, on a substrate by using a vapor deposition process with a tantalum halide precursor compound, a silicon precursor compound, and an optional nitrogen precursor compound.

Abstract: Tungsten silicide WSix is grown through reduction of WF6 with SiCl2H2, and the flow rate between WF6 and SiCl2H2 is controlled in such a manner that the composition ratio x ranges from 2.0 to 2.2 in an initial stage for forming cores on a doped polysilicon layer, and is treated with heat at 700 degrees to 850 degrees in centigrade so as to grow tungsten silicide grains with <001> orientation faster than tungsten silicide grains with <101> orientation; the tungsten silicide WSix is tightly adhered to the doped polysilicon, and the abnormal oxidation is restricted during the heat treatment.

Abstract: A semiconductor device adopting an interlayer contact structure between upper and lower conductive layers and a method of manufacturing the semiconductor device adopting the structure are provided. The lower conductive layer includes a first conductive layer and a first silicide layer stacked together. The upper conductive layer includes a second conductive layer doped with impurities and a second silicide layer stacked together. In the interlayer contact structure, the first and second conductive layers are in direct contact with each other. This decreases the contact resistance between the two conductive layers and improves the electrical properties of the device.

Abstract: An integrated circuit device having a semiconductor substrate includes a gate structure on the semiconductor substrate. Source/drain regions are on opposite sides of the gate structure. A contact pad is on at least one of the source/drain region, and a silicide cap is on a surface of the contact pad opposite the respective source/drain region.

Abstract: A semiconductor process is provided that creates transistors having polycide gates in a first region of a semiconductor substrate and transistors having salicide gates in a second region of the semiconductor substrate. A polysilicon layer having a first portion in the first region and a second portion in the second region is formed over the semiconductor substrate. Then, a first dielectric layer is formed over the second portion of the polysilicon layer. Metal silicide is deposited over first portion of the polysilicon layer and the first dielectric layer. The metal silicide overlying the first dielectric layer is removed as is the first dielectric layer. The metal silicide and the polysilicon layer are etched to form polycide gates in the first region and polysilicon gates in the second region. A second dielectric layer is formed over the first region. Refractory metal is then deposited over the resulting structure and reacted. As a result, salicide is formed on the polysilicon gates of the second region.

Abstract: Using plating, metal gates for N channel and P channel transistors are formed of different materials to achieve the appropriate work function for these N and P channel transistors. The plating is achieved with a seed layer consistent with the growth of the desired layer. The preferred materials are selected from the platinum metals, which comprise ruthenium, ruthenium oxide, iridium, palladium, platinum, nickel, osmium, and cobalt. These are attractive metals because they are relatively high conductivity, can be plated, and provide a good choice of work functions for forming P and N channel transistors.

Abstract: A method for depositing a film on a substrate is provided. In one aspect, the method includes providing a metal-containing precursor to an activation zone, and activating the metal-containing precursor to form an activated precursor. The activated precursor gas is transported to a reaction chamber, and a film is deposited on the substrate using a cyclical deposition process, wherein the activated precursor gas and a reducing gas are alternately adsorbed on the substrate. Also provided is a method of depositing a film on a substrate using an activated reducing gas.

Abstract: A semiconductor device includes sidewall insulating films formed on sides of the gate electrode layer respectively facing source and drain regions, and silicide layers formed on the source and drain regions. Oxygen-introduced portions are respectively formed in the source and drain regions near the sidewall insulating films. The oxygen-introduced portions contain oxygen atoms that are locally distributed on the interfaces between the silicide layers and the silicon layers of the source or drain regions at a concentration of 4.5×1019 cm−3 or more and an areal density of 5×1013 cm−2 or more. The oxygen-introduced portions form an Ohmic contact between the silicide layers and the silicon layers of the source or drain regions.

Abstract: A method for forming silicide contacts includes forming a layer on silicon-containing active device regions such as source, drain, and gate regions. The layer contains a metal that is capable of forming one or more metal silicides and a material that is soluble in a first metal silicide but not soluble in a second metal silicide, or is more soluble in the first metal silicide than in the second metal silicide. The layer may be formed by vapor deposition methods such as physical vapor deposition, chemical vapor deposition, evaporation, laser ablation, or other deposition method. A method for forming silicide contacts includes forming a metal layer, then implanting the metal layer and/or underlying silicon layer with a material such as that described above. The material may be implanted in the silicon layer prior to formation of the metal layer. Contacts formed include a first metal silicide and a material that is more soluble in a first metal silicide than in a second metal silicide.

Abstract: A method of forming ultra-shallow junctions in a semiconductor wafer forms the gate and source/drain junctions having upper surfaces at first metal suicide regions on the gate and source/drain junctions. These first metal silicide regions have a higher resistivity. Amorphous silicon is deposited on the first metal suicide regions by plasma enhanced chemical vapor deposition (PECVD). The PECVD process may be a lower pressure deposition process, performed at multiple stations to form the amorphous silicon layer in multiple layers. This creates a more uniform amorphous silicon layer across the wafer and different patterning densities, thereby improving device performance and characteristics. Annealing is then performed to form second metal silicide regions of a lower resistivity, by diffusion reaction of the first metal silicide regions and the amorphous silicon that was deposited by the PECVD process.

Abstract: A ternary metal silicide layer is formed between a silicon substrate and a barrier layer, in a contact structure including: a substrate having a silicon part; an insulating layer formed on the substrate, and having a connection hole that reaches the silicon part, a barrier layer formed at least on an inner surface of the connection hole; and a conductive member buried inside the barrier layer.

Abstract: This invention provides a solution to increase the yield strength and fatigue strength of miniaturized springs, which can be fabricated in arrays with ultra-small pitches. It also discloses a solution to minimize adhesion of the contact pad materials to the spring tips upon repeated contacts without affecting the reliability of the miniaturized springs. In addition, the invention also presents a method to fabricate the springs that allow passage of relatively higher current without significantly degrading their lifetime.

Abstract: A method for manufacturing a semiconductor device can simply form a silicide film for reducing ohmic contact between a metal line and a substrate and a ternary phase thin film as an amorphous diffusion prevention film between a metal line and the silicide film. The method for manufacturing a semiconductor device includes the steps of sequentially forming a first refractory metal and a second refractory metal on a semiconductor substrate, forming a silicide film on an interface between the semiconductor substrate and the first refractory metal, and reacting the semiconductor substrate with the first and second refractory metals on the silicide film to form a ternary phase thin film.

Abstract: Method for depositing a tantalum silicide barrier film on a semiconductor device including a silicon-based substrate with recessed features by low temperature thermal CVD. The tantalum silicide barrier film exhibits high conformality and low fluorine or chlorine impurity content. A specific embodiment of the method for depositing the tantalum silicide barrier layer includes depositing tantalum silicide by TCVD from the reaction of a TaF5 or TaCl5 precursor vapor with silane gas on a 250° C.-450° C. heated substrate.

Abstract: A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal layer, etching anisotropically and selectively with respect to the metal the silicon layer, reacting the metal with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.

Abstract: A process for forming a low resistivity titanium silicide layer on the surface of a silicon semiconductor substrate. In the process, an effective amount of a metallic element such as indium, gallium, tin, or lead is implanted or deposited on the surface of the silicon substrate. A titanium layer is deposited on the surface of the silicon substrate, and a rapid thermal annealing of the titanium-coated silicon substrate is performed to form low resistivity titanium silicide. In preferred processes, the metallic element is indium or gallium, and more preferably the metallic element is indium. A semiconductor device that has a titanium silicide layer on the surface of a silicon substrate is also provided.

Abstract: A semiconductor device is provided with semiconducting sidewall spacers used in the formation of source/drain regions. The semiconducting sidewall spacers also reduce the possibility of suicide shorting through shallow source/drain junctions. Embodiments include doping the semiconducting sidewall spacers so that they serve as a source of impurities for forming source/drain extensions during activation annealing.

Abstract: Reliable contacts/vias are formed by filling an opening in a dielectric layer with W and laser thermal annealing to eliminate or significantly reduce voids. Embodiments include depositing W to fill a contact/via opening in an interlayer dielectric, laser thermal annealing in N2 to elevate the temperature of the W filling the contact/via opening and reflow the W thereby eliminating voids. Embodiments include conducting CMP either before or subsequent to laser thermal annealing.

Abstract: Disclosed is a system for fabricating a semiconductor device (100). A layer of cobalt (32) is deposited onto a silicon region (104, 106, 108) and annealed to form a cobalt silicide layer (118, 120, 122). Silicon layers (124, 126, 128) are selectively deposited onto the cobalt silicide layers (118, 120, 122). The semiconductor device (100) is annealed to form disilicide layers (130, 132, 134) from the cobalt silicide layers (118, 120, 122) and the silicon contained in silicon regions (104, 106, 108) and silicon layers (124, 126, 128).

Abstract: A thin film forming method characterized by at least a first step and a second step which steps may be repeated. The first step is the step of supplying a compound containing at least one kind of metal element onto a substrate, and the second step is the step of irradiating the substrate with energy particles in order to introduce the metal element into the substrate. A semiconductor device manufacturing method of the present invention uses the thin film forming method described above in the manufacturing of a semiconductor device.

Abstract: A method for preventing polycide gate spiking, which essentially comprises the following steps: forms an oxide layer on a substrate; forming a polysilicon layer on the oxide layer; sputtering a barrier layer on the polysilicon layer; performing a first rapid thermal process; sputtering a silicide layer on the barrier layer; performing a photolithography process and an etching process to remove part of the silicide layer, part of the barrier layer and part of the polysilicon layer to form a polycide gate; and performing a second rapid thermal process. Further, as it is necessary to use both rapid thermal processes, the invention can be expanded such that only one rapid thermal process is applied. Both rapid thermal processes use almost no oxygen.