Aluminum Or Aluminum Alloy Conductor Patents (Class 438/688)
  • Patent number: 9330911
    Abstract: A light-emitting device, such as a light-emitting diode (LED), has a group III-nitride current spreading layer which is either doped with transition metal, or comprises alternating transition metal nitride layer and group III-nitride layer. Also provided is a light-emitting device, such as a light-emitting diode (LED), having a quantum well doped with transition metal. Also provided is a method of forming transition-metal containing AlInGaN electrical conductive material.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: May 3, 2016
    Assignee: INVENLUX LIMITED
    Inventors: Jianping Zhang, Chunhui Yan
  • Patent number: 9202636
    Abstract: A photoelectric conversion element comprising: a substrate; a first electrode; a photoelectric conversion layer comprising a semiconductor layer containing a dye and a semiconductor and a charge transport layer; and a second electrode, in this order, wherein the photoelectric conversion layer comprises a compound represented by Formula (1), wherein R1 and R2 each represent a hydrogen atom or an alkyl group which may have a substituent, X, Y and Z each represent a hydrogen atom or a substituent, wherein at least one of X, Y and Z is an electron withdrawing group.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: December 1, 2015
    Assignee: KONICA MINOLTA BUSINESS TECHNOLOGIES, INC.
    Inventors: Takayuki Ishikawa, Kazuya Isobe, Hidekazu Kawasaki
  • Patent number: 9040346
    Abstract: In one embodiment, a semiconductor package includes a semiconductor chip having a first contact region on a first major surface and a second contact region on an opposite second major surface. The semiconductor chip is configured to regulate flow of a current from the first contact region to the second contact region. An encapsulant is disposed at the semiconductor chip. A first contact plug is disposed within the encapsulant and coupled to the first contact region. A second side conductive layer is disposed under the second major surface and coupled to the second contact region. A through via is disposed within the encapsulant and coupled to the second side conductive layer. The first contact plug and the through via form terminals above the first major surface for contacting the semiconductor package.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ivan Nikitin, Edward Fuergut
  • Patent number: 9018088
    Abstract: Growing spin-capable multi-walled carbon nanotube (MWCNT) forests in a repeatable fashion will become possible through understanding the critical factors affecting the forest growth. Here we show that the spinning capability depends on the alignment of adjacent MWCNTs in the forest which in turn results from the synergistic combination of a high areal density of MWCNTs and short distance between the MWCNTs. This can be realized by starting with both the proper Fe nanoparticle size and density which strongly depend on the sheet resistance of the catalyst film. Simple measurement of the sheet resistance can allow one to reliably predict the growth of spin-capable forests. The properties of pulled MWCNTs sheets reflect that there is a relationship between their electrical resistance and optical transmittance. Overlaying either 3, 5, or 10 sheets pulled out from a single forest produces much more repeatable characteristics.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: April 28, 2015
    Assignee: Board of Regents, The University of Texas Systems
    Inventors: Jae Hak Kim, Gil Sik Lee, Kyung Hwan Lee, Lawrence J. Overzet
  • Patent number: 8975182
    Abstract: A method for manufacturing a semiconductor device is carried out by readying each of a semiconductor element, a substrate having Cu as a principal element at least on a surface, and a ZnAl solder chip having a smaller shape than that of the semiconductor element; disposing the semiconductor element and the substrate so that respective bonding surfaces face each other, and sandwiching the ZnAl eutectic solder chip between the substrate and the semiconductor element; increasing the temperature of the ZnAl solder chip sandwiched between the substrate and the semiconductor element while applying a load to the ZnAl solder chip such that the ZnAl solder chip melts to form a ZnAl solder layer; and reducing the temperature of the ZnAl solder layer while applying a load to the ZnAl solder layer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: March 10, 2015
    Assignees: Nissan Motor Co., Ltd., Sumitomo Metal Mining Co., Ltd., Sanken Electric Co., Ltd., Fuji Electric Co., Ltd.
    Inventors: Satoshi Tanimoto, Yusuke Zushi, Yoshinori Murakami, Takashi Iseki, Masato Takamori, Shinji Sato, Kohei Matsui
  • Publication number: 20150056788
    Abstract: A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.
    Type: Application
    Filed: September 30, 2014
    Publication date: February 26, 2015
    Inventors: Gerhard Schmidt, Josef-Georg Bauer, Carsten Schaeffer, Oliver Humbel, Angelika Koprowski, Sirinpa Monayakul
  • Patent number: 8963325
    Abstract: According to example embodiments of inventive concepts, a power device includes a semiconductor structure having a first surface facing a second surface, an upper electrode, and a lower electrode. The upper electrode may include a first contact layer that is on the first surface of the semiconductor structure, and a first bonding pad layer that is on the first contact layer and is formed of a metal containing nickel (Ni). The lower electrode may include a second contact layer that is under the second surface of the semiconductor structure, and a second bonding pad layer that is under the second contact layer and is formed of a metal containing Ni.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Baik-woo Lee, Young-hun Byun, Seong-woon Booh, Chang-mo Jeong
  • Patent number: 8927428
    Abstract: A process for the formation of at least one aluminum p-doped surface region of an n-type semiconductor substrate comprising the steps: (1) providing an n-type semiconductor substrate, (2) applying and drying an aluminum paste on at least one surface area of the n-type semiconductor substrate, (3) firing the dried aluminum paste, and (4) removing the fired aluminum paste with water, wherein the aluminum paste employed in step (2) includes particulate aluminum, an organic vehicle and 3 to 20 wt. % of glass frit, based on total aluminum paste composition.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: January 6, 2015
    Assignee: E I du Pont de Nemours and Company
    Inventors: Kenneth Warren Hang, Alistair Graeme Prince, Michael Rose, Richard John Sheffield Young
  • Publication number: 20140377952
    Abstract: An Al wiring film having a tapered shape is obtained easily and in a stable manner. An Al wiring film has a double-layer structure including a first Al alloy layer made of Al or an Al alloy, and a second Al alloy layer laid on the first Al alloy layer and having a composition different from a composition of the first Al alloy layer by containing at least one element of Ni, Pd, and Pt. The second Al alloy layer is etched by an alkaline chemical solution used in a developing process of a photoresist, and an end portion of the second Al alloy layer recedes from an end portion of the photoresist. Thereafter, by performing wet etching using the photoresist as a mask, a cross section of the Al wiring film becomes a tapered shape.
    Type: Application
    Filed: July 24, 2014
    Publication date: December 25, 2014
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kazuyuki FUJIWARA, Kazunori INOUE, Takahito YAMABE
  • Patent number: 8906806
    Abstract: A method of manufacturing a semiconductor device comprises forming a contact hole within an interlayer insulating film of a substrate and forming a contact plug while the substrate is heated. In forming the contact plug, the substrate is held on a stage within the chamber of a sputtering apparatus through a chuck, and an ESC voltage applied to the chuck is increased stepwise in a plurality of steps. First target power is applied to a target within the chamber to form a first Al film in the contact hole. Next, second target power higher than the first target power is applied to the target within the chamber to form a second Al film on the first Al film.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: December 9, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Katsuhiko Tanaka
  • Patent number: 8866298
    Abstract: A semiconductor component includes a semiconductor die and a copper-containing electrical conductor. The semiconductor die has a semiconductor device region, an aluminum-containing metal layer on the semiconductor device region, and at least one additional metal layer on the aluminum-containing metal layer which is harder than the aluminum-containing metal layer. The copper-containing electrical conductor is bonded to the at least one additional metal layer of the semiconductor die via an electrically conductive coating of the copper-containing electrical conductor which is softer than the copper of the copper-containing electrical conductor.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies AG
    Inventor: Reinhold Bayerer
  • Patent number: 8809184
    Abstract: One method disclosed herein includes forming a plurality of source/drain contacts that are conductively coupled to a source/drain region of a plurality of transistor devices, wherein at least one of the source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in a first active region and to a second source/drain region in a second active region, and forming a patterned mask layer that covers the first and second active regions and exposes at least a portion of the local interconnect structure positioned above an isolation region that separates the first and second active regions. The method further includes performing an etching process through the patterned mask layer to remove a portion of the local interconnect structure, thereby defining a recess positioned above a remaining portion of the local interconnect structure, and forming an insulating material in the recess.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: August 19, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Lei Yuan, Jin Cho, Jongwook Kye, Harry J. Levinson
  • Patent number: 8802552
    Abstract: A method for manufacturing a MOSFET includes the steps of: forming a gate oxide film on an active layer, forming a gate electrode on the gate oxide film, forming a source contact electrode in ohmic contact with the active layer, and forming an interlayer insulating film made of silicon dioxide so as to cover the gate electrode after the source contact electrode is formed. The step of forming a source contact electrode includes the steps of forming a metal layer including aluminum so as to be in contact with the active layer, and alloying the metal layer.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: August 12, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Takeyoshi Masuda
  • Patent number: 8796747
    Abstract: A semiconductor chip having a photonics device and a CMOS device which includes a photonics device portion and a CMOS device portion on a semiconductor chip; a metal or polysilicon gate on the CMOS device portion, the metal or polysilicon gate having a gate extension that extends toward the photonics device portion; a germanium gate on the photonics device portion such that the germanium gate is coplanar with the metal or polysilicon gate, the germanium gate having a gate extension that extends toward the CMOS device portion, the germanium gate extension and metal or polysilicon gate extension joined together to form a common gate; spacers formed on the germanium gate and the metal or polysilicon gate; and nitride encapsulation formed on the germanium gate. A method is also disclosed pertaining to fabricating the semiconductor chip.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Solomon Assefa, William M. J. Green, Steven M. Shank, Yurii A. Vlasov
  • Patent number: 8785258
    Abstract: A highly reliable semiconductor device which includes a transistor including an oxide semiconductor is provided. In the semiconductor device including a bottom-gate transistor including an oxide semiconductor layer, a stacked layer of an insulating layer and an aluminum film is provided in contact with the oxide semiconductor layer. Oxygen doping treatment is performed in such a manner that oxygen is introduced to the insulating layer and the aluminum film from a position above the aluminum film, whereby a region containing oxygen in excess of the stoichiometric composition is formed in the insulating layer, and the aluminum film is oxidized to form an aluminum oxide film.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: July 22, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20140183720
    Abstract: Methods of manufacturing semiconductor integrated circuits having a compressive nitride layer are disclosed. In one example, a method of fabricating an integrated circuit includes depositing an aluminum layer over a semiconductor substrate, depositing a tensile silicon nitride layer or a neutral silicon nitride layer over the aluminum layer, and depositing a compressive silicon nitride layer over the tensile silicon nitride layer or the neutral silicon nitride layer. The compressive silicon nitride layer is deposited at a thickness that is at least about twice a thickness of the tensile silicon nitride layer or the neutral silicon nitride layer. Further, there is no delamination present at an interface between the aluminum layer and the tensile silicon nitride layer or the neutral silicon nitride layer, or at an interface between tensile silicon nitride layer or the neutral silicon nitride layer and the compressive nitride layer.
    Type: Application
    Filed: December 31, 2012
    Publication date: July 3, 2014
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Scott Beasor, Jay Strane, Man Fai Ng, Brett H. Engel, Chang Yong Xiao, Michael P. Belyansky, Tsung-Liang Chen, Kyung Bum Koo
  • Patent number: 8748319
    Abstract: Embodiments of the invention may provide a method of printing one or more print tracks on a print support, or substrate, comprising two or more printing steps in each of which a layer of material is deposited on the print support according to a predetermined print profile. In each printing step, subsequent to the first step, each layer of material is deposited at least partially on top of the layer of material printed in the preceding printing step, so that each layer of printed material has an identical or different print profile with respect to at least a layer of material underneath. The method may further comprise depositing material in each printing step that is equivalent to or different from the material deposited in at least one of other the print layers.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: June 10, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Marco Galiazzo, Andrea Baccini, Giorgio Cellere, Luigi De Santi, Gianfranco Pasqualin, Tommaso Vercesi
  • Patent number: 8735290
    Abstract: A reactive evaporation method for forming a group III-V amorphous material attached to a substrate includes subjecting the substrate to an ambient pressure of no greater than 0.01 Pa, and introducing active group-V matter to the surface of the substrate at a working pressure of between 0.05 Pa and 2.5 Pa, and group III metal vapor, until an amorphous group III-V material layer is formed on the surface.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: May 27, 2014
    Assignee: Mosaic Crystal Ltd.
    Inventor: Moshe Einav
  • Patent number: 8735276
    Abstract: Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: May 27, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Hyun-Soo Chung, Jae-Shin Cho, Dong-Ho Lee, Dong-Hyeon Jang, Seong-Deok Hwang, Seung-Duk Baek
  • Patent number: 8722530
    Abstract: A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: May 13, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gregory S. Spencer, Phillip E. Crabtree, Dean J. Denning, Kurt H. Junker, Gerald A. Martin
  • Patent number: 8691688
    Abstract: A method of processing a substrate is provided. The method includes: providing a substrate, wherein the substrate includes a silicon layer; etching the substrate to form a cavity; filling a first conductor in part of the cavity; performing a first thermal treatment on the first conductor; filling a second conductor in the cavity to fill-up the cavity; and performing a second thermal treatment on the first conductor and the second conductor.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: April 8, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Hsin-Yu Chen, Yu-Han Tsai, Chun-Ling Lin, Ching-Li Yang, Home-Been Cheng
  • Patent number: 8664759
    Abstract: An integrated circuit die includes a substrate having an upper surface, at least one active device formed in a first area of the upper surface of the substrate, and a plurality of layers formed on the upper surface of the substrate above the at least one active device. A first stacked heat conducting structure is provided, spanning from a point proximate the first area of the upper surface of the substrate through the plurality of layers. A lateral heat conducting structure is formed above the uppermost layer of the plurality of layers and in thermal contact with the first stacked heat conducting structure. The invention advantageously facilitates the dissipation of heat from the integrated circuit die, particularly from high-power sources or other localized hot spots.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: March 4, 2014
    Assignee: Agere Systems LLC
    Inventor: Vivian Ryan
  • Patent number: 8653665
    Abstract: There is provided a film forming method for forming a film on a target object having thereon an insulating layer 1 that is made of a low-k film and having a recess 2 whose bottom surface is exposed to a metallic layer 3. The film forming method includes forming a first-metal-containing film containing a first metal such as ruthenium (Ru); and after forming the first-metal-containing film, forming a second-metal-containing film containing a second metal such as a manganese (Mn) having a barrier property against a filling metal to be filled in the recess.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: February 18, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Hidenori Miyoshi
  • Patent number: 8647984
    Abstract: The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer made of an insulating material containing Si and O; a groove forming step of forming a groove in the insulating layer; a metal film applying step of covering the inner surface of the groove with a metal film made of MnOx (x: a number greater than zero) by sputtering; and a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu on the metal film.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: February 11, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Yuichi Nakao, Satoshi Kageyama
  • Publication number: 20140004700
    Abstract: A manufacturing method includes forming a wiring layer including a first wiring connected to a gate electrode of a semiconductor element, a second wiring having an area in an orthogonal projection onto a plane including a surface of the semiconductor substrate larger than the first wiring, and a third wiring connected to a protective element, from a conductive material film by etching using plasma on the conductive material film. In the forming the wiring layer, the etching is conducted in a manner that a part that becomes the first wiring of the conductive material film is separated from the part that becomes the second wiring of the conductive material film earlier than a part that becomes the third wiring of the conductive material film.
    Type: Application
    Filed: June 24, 2013
    Publication date: January 2, 2014
    Inventor: Yasushi Nakata
  • Patent number: 8580135
    Abstract: A mold of the present invention includes: a base 12 made of glass or plastic; an inorganic underlayer 14 provided on a surface of the base 12; a buffer layer 16 provided on the inorganic underlayer 14, the buffer layer 16 containing aluminum; an aluminum layer 18a provided on a surface of the buffer layer 16; and a porous alumina layer 20 provided on a surface of the aluminum layer 18a. The porous alumina layer 20 has a plurality of recessed portions 22 whose two-dimensional size viewed in a direction normal to the surface is not less than 10 nm and less than 500 nm. The mold of the present invention has excellent adhesion between the aluminum layer and the base.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: November 12, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hidekazu Hayashi, Kiyoshi Minoura, Akinobu Isurugi
  • Patent number: 8575021
    Abstract: Methods for substrate processing are described. The methods include forming a material layer on a substrate. The methods include selecting constituents of a molecular masking layer (MML) to remove an effect of variations in the material layer as a result of substrate processing. The methods include normalizing the surface characteristics of the material layer by selectively depositing the MML on the material layer.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 5, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Thomas R. Boussie, Tony P. Chiang, Anh Duong, Zachary Fresco, Nitin Kumar, Chi-I Lang, Sandra G. Malhotra, Jinhong Tong
  • Patent number: 8552559
    Abstract: A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective electroplating technology, is located on top of the fine line interconnection scheme. It is especially useful for long distance lines, clock, power and ground buses, and other applications such as high Q inductors and bypass lines. The fine line interconnections are more appropriate to be used for local interconnections. The combined structure of coarse and fine line interconnections forms a new interconnection scheme that not only enhances IC speed, but also lowers power consumption.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: October 8, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
  • Patent number: 8551884
    Abstract: A method of manufacturing a semiconductor device comprises forming a contact hole within an interlayer insulating film of a substrate and forming a contact plug while the substrate is heated. In forming the contact plug, the substrate is held on a stage within the chamber of a sputtering apparatus through a chuck, and an ESC voltage applied to the chuck is increased stepwise in a plurality of steps. First target power is applied to a target within the chamber to form a first Al film in the contact hole. Next, second target power higher than the first target power is applied to the target within the chamber to form a second Al film on the first Al film.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: October 8, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Katsuhiko Tanaka
  • Patent number: 8546270
    Abstract: An atomic layer deposition apparatus and an atomic layer deposition method increase productivity. The atomic layer deposition apparatus includes a reaction chamber, a heater for supporting a plurality of semiconductor substrates with a given interval within the reaction chamber and to heat the plurality of semiconductor substrates and a plurality of injectors respectively positioned within the reaction chamber and corresponding to the plurality of semiconductor substrates supported by the heater. The plurality of injectors are individually swept above the plurality of semiconductor substrates to spray reaction gas.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Hyun Kim, Ki-Vin Im, Hoon-Sang Choi, Moon-Hyeong Han
  • Patent number: 8486222
    Abstract: A substrate processing apparatus includes a processing chamber configured to process a substrate, a substrate support member provided within the processing chamber to support the substrate, a microwave generator provided outside the processing chamber, a waveguide launch port configured to supply a microwave generated by the microwave generator into the processing chamber, wherein the central position of the waveguide launch port is deviated from the central position of the substrate supported on the substrate support member and the waveguide launch port faces a portion of a front surface of the substrate supported on the substrate support member, and a control unit configured to change a relative position of the substrate support member in a horizontal direction with respect to the waveguide launch port.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: July 16, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Tokunobu Akao, Unryu Ogawa, Masahisa Okuno, Shinji Yashima, Atsushi Umekawa, Kaichiro Minami
  • Patent number: 8455360
    Abstract: A method for fabricating a storage node of a semiconductor device includes forming a sacrificial dielectric pattern with a storage node hole on a substrate, forming a support layer on the sacrificial dielectric pattern, forming a storage node, supported by the support layer, in the storage node hole, performing a full dip-out process to expose the outer wall of the storage node, and performing a cleaning process for removing or reducing a bridge-causing material formed on the surface of the support layer.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: June 4, 2013
    Assignee: SK Hynix Inc.
    Inventors: Hyo Geun Yoon, Ji Yong Park, Sun Jin Lee
  • Patent number: 8450209
    Abstract: A method of forming a non-volatile memory device includes providing a substrate having a surface and forming a first dielectric overlying the surface, forming a first wiring comprising aluminum material over the first dielectric, forming a silicon material over the aluminum material to form an intermix region consuming a portion of the silicon material and aluminum material, annealing to formation a first alloy from the intermix region, forming a p+ impurity polycrystalline silicon over the first alloy material, forming a first wiring structure from at least a portion of the first wiring, forming a resistive switching element comprising an amorphous silicon material formed over the p+ polycrystalline silicon, and forming a second wiring structure comprising at least a metal material over the resistive switching element.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: May 28, 2013
    Assignee: Crossbar, Inc.
    Inventor: Scott Brad Herner
  • Publication number: 20130119531
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming an underlayer film that contains atoms selected from the group consisting of aluminum, boron and alkaline earth metal; and forming a silicon oxide film on the underlayer film by a CVD method or an ALD method by use of a silicon source containing at least one of an ethoxy group, a halogen group, an alkyl group and an amino group, or a silicon source of a siloxane system.
    Type: Application
    Filed: March 19, 2012
    Publication date: May 16, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Kenichiro Toratani
  • Patent number: 8440566
    Abstract: The method is adapted for forming an aluminum nitride thin film having a high density and a high resistance to thermal shock by a chemical vapor deposition process and includes steps of mixing a gas containing aluminum atoms (Al) and a gas containing nitrogen atoms (N) with a gas containing oxygen atoms (O) and feeding the mixture to a member to be covered by an aluminum nitride thin film.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: May 14, 2013
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Koji Kato, Shoji Kano, Waichi Yamamura
  • Patent number: 8435899
    Abstract: A microcolumnar structured material having a desired material. The columnar structured material includes columnar members obtained by introducing a filler into columnar holes formed in a porous material. The porous material has the columnar holes formed by removing columnar substances from a structured material in which the columnar substances containing a first component are dispersed in a matrix member containing a second component capable of forming a eutectic with the first component. The matrix member may be removed. In the columnar structured material, the filler is a conductive material, and an electrode can be structured by electrically connecting the conductive materials in at least a part of a plurality of holes to a conductor.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: May 7, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hirokatsu Miyata, Albrecht Otto, Akira Kuriyama, Miki Ogawa, Hiroshi Okura, Kazuhiko Fukutani, Tohru Den
  • Patent number: 8426973
    Abstract: An integrated circuit including an insulating layer having first and second opposite surfaces. The circuit includes, in a first area, first conductive portions of a first conductive material, located in the insulating layer, flush with the first surface and continued by first vias of the first conductive material, of smaller cross-section and connecting the first conductive portions to the second surface. The circuit further includes, in a second area, second conductive portions of a second material different from the first conductive material and arranged on the first surface and second vias of the first conductive material, in contact with the second conductive portions and extending from the first surface to the second surface.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: April 23, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Stephan Niel, Jean-Michel Mirabel
  • Patent number: 8420530
    Abstract: A method for forming interconnects in a substrate, the substrate comprising a semiconductor layer on an oxide layer forming a silicon-on-oxide substrate, the method comprising forming a plurality of holes into the substrate to the semiconductor layer, and metalizing the plurality of holes to form the interconnects.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: April 16, 2013
    Assignee: Agency for Science, Technology and Research
    Inventors: Naing Tun Thet, Christian Joachim, Natarajan Chandrasekhar
  • Patent number: 8404558
    Abstract: In a preferred method of formation embodiment, a metal foil or film is obtained or formed with micro-holes. The foil is anodized to form metal oxide. One or more self-patterned metal electrodes are automatically formed and buried in the metal oxide created by the anodization process. The electrodes form in a closed circumference around each microcavity in a plane(s) transverse to the microcavity axis, and can be electrically isolated or connected. Preferred embodiments provide inexpensive microplasma device electrode structures and a fabrication method for realizing microplasma arrays that are lightweight and scalable to large areas. Electrodes buried in metal oxide and complex patterns of electrodes can also be formed without reference to microplasma devices—that is, for general electrical circuitry.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: March 26, 2013
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: J. Gary Eden, Sung-Jin Park, Kwang-Soo Kim
  • Patent number: 8399317
    Abstract: In one aspect, an apparatus may include a metal gate of a transistor. An etch stop layer may be selectively formed over the metal gate. The etch stop layer may include a metal compound. An insulating layer may be over the etch stop layer. A conductive structure may be included through the insulating layer to the metal gate. Methods of making such transistors are also disclosed.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: March 19, 2013
    Assignee: Intel Corporation
    Inventors: Andrew Ott, Sean King, Ajay Sharma
  • Patent number: 8354334
    Abstract: A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: January 15, 2013
    Assignee: Alpha & Omega Semiconductor Inc.
    Inventor: Il Kwan Lee
  • Patent number: 8304336
    Abstract: A method for fabricating a solar cell using inductively coupled plasma chemical vapor deposition (ICP-CVD) including a first electrode, a P layer, an intrinsic layer, an N-type layer and a second electrode. The method includes forming an intrinsic layer including a hydrogenated amorphous silicon (Si) thin film by an inductively coupled plasma chemical vapor deposition (ICP-CVD) device using mixed gas including hydrogen (H2) gas and silane (SiH4) gas. In the mixed gas, silane gas is in a ratio of 8 to 10 relative to mixed gas.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: November 6, 2012
    Assignee: Korea Institute of Industrial Technology
    Inventors: Chaehwan Jeong, Jong Ho Lee, Ho-Sung Kim, Seongjae Boo
  • Patent number: 8288273
    Abstract: A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: October 16, 2012
    Assignee: Alpha & Omega Semiconductor Inc.
    Inventor: Il Kwan Lee
  • Patent number: 8283245
    Abstract: In one example, a method for fabricating a solar cell comprising a first electrode, a first-type layer, an intrinsic layer, a second-type layer and a second electrode is disclosed. At least one of the second-type layer, the intrinsic layer and the first-type layer is formed as a crystallized Si layer by an inductively coupled plasma chemical vapor deposition (ICP-CVD) device using mixed gas including hydrogen (H2) gas and silane (SiH4) gas, the mixed gas having a silane gas (SiH4) in a ratio of 0.016 to 0.02.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: October 9, 2012
    Assignee: Korea Institute of Industrial Technology
    Inventors: Chaehwan Jeong, Jong Ho Lee, Ho-Sung Kim, Seongjae Boo
  • Patent number: 8268714
    Abstract: In one example, a method for fabricating a solar cell comprising a first electrode, a first-type layer, an intrinsic layer, a second-type layer and a second electrode is disclosed. The method comprising forming a second-type layer including an amorphous silicon (Si) carbide thin film by an inductively coupled plasma chemical vapor deposition (ICP-CVD) device using mixed gas including hydrogen (H2) gas, silane (SiH4) gas, diborane (B2H6) and ethylene (C2H4) gas, wherein the ethylene (C2H4) gas includes 60% hydrogen gas diluted ethylene gas, the diborane gas is 97% hydrogen gas diluted diborane gas, the mixed gas includes 1 to 1.2% ethylene gas and 6 to 6.5% diborane gas.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: September 18, 2012
    Assignee: Korea Institute of Industrial Technology
    Inventors: Chaehwan Jeong, Jong Ho Lee, Ho-Sung Kim, Seongjae Boo
  • Publication number: 20120211792
    Abstract: A package substrate is disclosed. The package substrate includes a substrate body having a conductive portion, a plurality of insulation portions and two surfaces opposing to each other; and a plurality of bonding layers for heat dissipation formed on the two surfaces of the substrate body, conducted via the conductive portion and separated from one another by the insulation portions. A method for forming the package substrate is also disclosed.
    Type: Application
    Filed: May 19, 2011
    Publication date: August 23, 2012
    Applicant: VIKING TECH CORPORATION
    Inventors: Shih-Long Wei, Shen-Li Hsiao, Chien-Hung Ho
  • Patent number: 8242487
    Abstract: There is provided an anode for an organic electronic device. The anode is a conducting inorganic material having an oxidized surface layer. The surface layer is non-conductive and hole-transporting.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: August 14, 2012
    Assignee: E I du Pont de Nemours and Company
    Inventor: Shiva Prakash
  • Patent number: 8193030
    Abstract: Nonvolatile memory devices may be fabricated to include a switching device on a substrate and/or a storage node electrically connected to the switching device. A storage node may include a lower metal layer electrically connected to the switching device, a first insulating layer, a middle metal layer, a second insulating layer, an upper metal layer, a carbon nanotube layer, and/or a passivation layer stacked on the lower metal layer.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: June 5, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-wook Moon, Joong S. Jeon, El Mostafa Bourim, Hyun-deok Yang
  • Patent number: 8168543
    Abstract: Methods of forming a barrier layer are provided. In one embodiment, the method includes providing a substrate into a physical vapor deposition (PVD) chamber, supplying at least two reactive gases and an inert gas into the PVD chamber, sputtering a source material from a target disposed in the processing chamber in the presence of a plasma formed from the gas mixture, and forming a metal containing dielectric layer on the substrate from the source material. In another embodiment, the method includes providing a substrate into a PVD chamber, supplying a reactive gas the PVD chamber, sputtering a source material from a target disposed in the PVD chamber in the presence of a plasma formed from the reactive gas, forming a metal containing dielectric layer on the substrate from the source material, and post treating the metal containing layer in presence of species generated from a remote plasma chamber.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: May 1, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Xinyu Fu, Keyvan Kashefizadeh, Ashish Subhash Bodke, Winsor Lam, Yiochiro Tanaka, Wonwoo Kim
  • Patent number: 8120184
    Abstract: The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise one or both of aluminum silane and aluminum silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: February 21, 2012
    Assignee: Micron Technology, Inc.
    Inventor: John Smythe