Aluminum Or Aluminum Alloy Conductor Patents (Class 438/688)
  • Patent number: 8119525
    Abstract: Methods of controlling deposition of metal on field regions of a substrate in an electroplating process are provided. In one aspect, a dielectric layer is deposited under plasma on the field region of a patterned substrate, leaving a conductive surface exposed in the openings. Electroplating on the field region is reduced or eliminated, resulting in void-free features and minimal excess plating. In another aspect, a resistive layer, which may be a metal, is used in place of the dielectric. In a further aspect, the surface of the conductive field region is modified to change its chemical potential relative to the sidewalls and bottoms of the openings.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: February 21, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Jick M. Yu, Wei D. Wang, Rongjun Wang, Hua Chung
  • Patent number: 8110504
    Abstract: The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer made of an insulating material containing Si and O; a groove forming step of forming a groove in the insulating layer; a metal film applying step of covering the inner surface of the groove with a metal film made of MnOx (x: a number greater than zero) by sputtering; and a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu on the metal film.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: February 7, 2012
    Assignee: Rohm Co., Ltd.
    Inventors: Yuichi Nakao, Satoshi Kageyama
  • Patent number: 8088688
    Abstract: A method of forming a non-volatile memory device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring material comprising at least an aluminum material is formed overlying the first dielectric material. The method forms a silicon material overlying the aluminum material and forms an intermix region consuming a portion of the silicon material and a portion of the aluminum material. The method includes an annealing process to cause formation of a first alloy material from the intermix region and a polycrystalline silicon material having a p+ impurity characteristic overlying the first alloy material. A first wiring structure is formed from at least a portion of the first wiring material. A resistive switching element comprising an amorphous silicon material is formed overlying the polycrystalline silicon material having the p+ impurity characteristic.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: January 3, 2012
    Assignee: Crossbar, Inc.
    Inventor: Scott Brad Herner
  • Patent number: 8076778
    Abstract: A semiconductor device and related method for fabricating the same include providing a stacked structure including an insulating base layer and lower and upper barrier layers with a conductive layer in between, etching the stacked structure to provide a plurality of conductive columns that each extend from the lower barrier layer, each of the conductive columns having an overlying upper barrier layer cap formed from the etched upper barrier layer, wherein the lower barrier layer is partially etched to provide a land region between each of the conductive lines, forming a liner layer over the etched stacked structure exposing the land region, and etching the liner layer and removing the exposed land region to form a plurality of conductive lines.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: December 13, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Kuo Liang Wei, Hsu Sheng Yu, Hong-Ji Lee
  • Patent number: 8071482
    Abstract: A manufacturing method for a silicon carbide semiconductor device is disclosed. It includes an etching method in which an Al film and Ni film are laid on an SiC wafer in this order and wet-etched, whereby a two-layer etching mask is formed in which Ni film portions overhang Al film portions. Mesa grooves are formed by dry etching by using this etching mask.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: December 6, 2011
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Yasuyuki Kawada
  • Patent number: 8067304
    Abstract: A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: November 29, 2011
    Assignee: Alpha and Omega Semiconductor, Inc.
    Inventor: Il Kwan Lee
  • Patent number: 8067310
    Abstract: A method for manufacturing a semiconductor device, includes: forming a first metal layer on a semiconductor substrate, the semiconductor substrate including a diffusion layer; forming an insulating layer having an opening on the first metal layer; forming a second metal layer on the first metal layer in the opening of the insulating layer; removing the insulating layer; covering an exposed surface of the second metal layer with a third metal layer, the third metal layer including a metal having an ionization tendency lower than that of the second metal layer; and forming an electrode interconnect including the first metal layer, the second metal layer, and the third metal layer by removing the first metal layer using the third metal layer as a mask.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: November 29, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomomi Imamura, Tetsuo Matsuda, Yoshinosuke Nishijo
  • Patent number: 8062978
    Abstract: Crystalline aluminum oxide layers having increased energy band gap, charge trap memory devices including crystalline aluminum oxide layers and methods of manufacturing the same are provided. A method of forming an aluminum oxide layer having an increased energy band gap includes forming an amorphous aluminum oxide layer on a lower film, introducing hydrogen (H) or hydroxyl group (OH) into the amorphous aluminum oxide layer, and crystallizing the amorphous aluminum oxide layer including the H or OH.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: November 22, 2011
    Assignee: Samsung Electronics Co., Inc.
    Inventors: Sang-moo Choi, Jung-hun Sung, Kwang-soo Seol, Woong-chul Shin, Sang-jin Park
  • Publication number: 20110266674
    Abstract: The present disclosure provides methods for forming semiconductor devices with laser-etched vias and apparatus including the same. In one embodiment, a method of fabricating a semiconductor device includes providing a substrate having a frontside and a backside, and providing a layer above the frontside of the substrate, the layer having a different composition from the substrate. The method further includes controlling a laser power and a laser pulse number to laser etch an opening through the layer and at least a portion of the frontside of the substrate, filling the opening with a conductive material to form a via, removing a portion of the backside of the substrate to expose the via, and electrically coupling a first element to a second element with the via. A semiconductor device fabricated by such a method is also disclosed.
    Type: Application
    Filed: April 28, 2010
    Publication date: November 3, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsing-Kuo Hsia, Chih-Kuang Yu, Ching-Hua Chiu, Troy Wu
  • Patent number: 8043944
    Abstract: Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films on semiconductor substrates as well as the uniform and precise removal of materials from such substrates. In one embodiment, the process includes, providing a supercritical fluid containing at least one reactant, the supercritical fluid being maintained at above its critical point, exposing at least a portion of the surface of the semiconductor substrate to the supercritical fluid, applying acoustic energy, and reacting the at least one reactant to cause a change in at least a portion of the surface of the semiconductor substrate.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: October 25, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Theodore M. Taylor, Stephen J. Kramer
  • Patent number: 8043966
    Abstract: Disclosed are embodiments of a method that both monitors patterning integrity of etched openings (i.e., ensures that lithographically patterned and etched openings are complete) and forms on-chip conductive structures (e.g., contacts, interconnects, fuses, anti-fuses, capacitors, etc.) within such openings. The method embodiments incorporate an electro-deposition process to provide both the means by which pattern integrity of etched openings can be monitored and also the metallization required for the formation of conductive structures within the openings. Specifically, during the electro-deposition process, electron flow is established by applying a current to the back side of the semiconductor wafer, thus, eliminating the need for a seed layer. Electron flow through the wafer and into the electroplating solution is then monitored and used as an indicator of electroplating in the etched openings and, thereby, as an indicator that the openings are completely etched.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: October 25, 2011
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Toshiharu Furukawa, William R. Tonti
  • Patent number: 8043978
    Abstract: Provided is a novel electronic device that comprises graphite, graphene or the like. An electronic device having a substrate, a layer comprising a 6-member ring-structured carbon homologue as the main ingredient, a pair of electrodes, a layer comprising aluminium oxide as the main ingredient and disposed between the pair of electrodes, and a layer comprising aluminium as the main ingredient, wherein the layer comprising aluminium oxide as the main ingredient is disposed between the layer comprising a 6-member ring-structured carbon homologue as the main ingredient and the layer comprising aluminium as the main ingredient so as to be in contact with the two layers.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: October 25, 2011
    Assignee: Riken
    Inventors: Hisao Miyazaki, Kazuhito Tsukagoshi, Syunsuke Odaka, Yoshinobu Aoyagi
  • Publication number: 20110230047
    Abstract: In some embodiments, a method of etching an organosiloxane dielectric material can include: (a) providing the organosiloxane dielectric material; (b) providing a patterned mask over the organosiloxane dielectric material; and (c) reactive ion etching the organosiloxane dielectric material. Other embodiments are disclosed in this application.
    Type: Application
    Filed: May 27, 2011
    Publication date: September 22, 2011
    Applicant: Arizona Board of Regents, for and on behalf of Arizona State University
    Inventor: MICHAEL MARRS
  • Patent number: 8017519
    Abstract: Disclosed is a semiconductor device including: a substrate; a wiring layer formed on the substrate and made of copper or a copper alloy; a copper diffusion barrier film formed on the wiring layer and made of an amorphous carbon film formed by CVD using a processing gas containing a hydrocarbon gas; and a low-k insulating film formed on the copper diffusion barrier film.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: September 13, 2011
    Assignee: Tokyo Electron Limited
    Inventor: Hiraku Ishikawa
  • Patent number: 8017446
    Abstract: Method for manufacturing a rigid power module with a layer that is electrically insulating and conducts well thermally and has been deposited as a coating, the structure having sprayed-on particles that are fused to each other, of at least one material that is electrically insulating and conducts well thermally, having the following steps: manufacturing a one-piece lead frame; populating the lead frame with semiconductor devices, possible passive components, and bonding corresponding connections, inserting the thus populated lead frame into a compression mould so that accessibility of part areas of the lead frame is ensured, pressing a thermosetting compression moulding compound into the mould while enclosing the populated lead frame, coating the underside of the thus populated lead frame by thermal spraying in at least the electrically conducting areas and overlapping also the predominant areas of the spaces, filled with mold compound.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: September 13, 2011
    Assignee: Danfoss Silicon Power GmbH
    Inventors: Ronald Eisele, Mathias Kock, Teoman Senyildiz
  • Patent number: 8003536
    Abstract: A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAl3 liner by reaction of the Ti liner with the material of the aluminum portion. The material of the TiAl3 liner is resistant to electromigration, thereby providing enhanced electromigration resistance to the vertical metallic stack comprising the elemental metal liner, the metal nitride liner, the TiAl3 liner, the aluminum portion, and the metal nitride cap. The effect of enhanced electromigration resistance may be more prominent in areas in which the metal nitride cap suffers from erosion during processing.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: August 23, 2011
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Chapple-Sokol, Daniel A. Delibac, Zhong-Xiang He, Tom C. Lee, William J. Murphy, Timothy D. Sullivan, David C. Thomas, Daniel S. Vanslette
  • Patent number: 8003505
    Abstract: A method of fabricating an image sensor. A method of fabricating an image sensor may include preparing a substrate including a pixel region and/or a logic region having transistors and/or gates. A method of fabricating an image sensor may include forming a first interlayer dielectric film on and/or over a substrate to cover gates. A method of fabricating an image sensor may include forming a first dielectric film to expose an upper surface of at least one gate over a pixel region. A method of fabricating an image sensor may include forming a second interlayer dielectric film over a first interlayer dielectric film and/or dielectric film. A method of fabricating an image sensor may include forming a plurality of contact holes, which may be simultaneously formed over a second interlayer dielectric film. An image sensor may include contacts formed over a second interlayer dielectric film. An image sensor is disclosed.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: August 23, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Hoon Jang
  • Patent number: 7977131
    Abstract: The present invention provides a method of manufacturing a nano-array electrode with a controlled nano-structure by filling a compound having an electron-accepting structure or an electron donating structure into the fine pores of an anodic-oxide porous alumina film obtained by anodically oxidizing aluminum in electrolyte. The spaces defined between the nano-arrays formed of the compound by removing the alumina film are filled with a compound having an electron-donating structure if the nano-arrays have an electron-accepting structure and a compound having an electron-accepting structure if the nano-arrays have an electron-donating structure. A high-performance, high-efficiency photoelectric converting device comprising a nano-array electrode manufactured by the method is also disclosed.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: July 12, 2011
    Assignee: Nippon Oil Corporation
    Inventors: Tsuyoshi Asano, Takaya Kubo, Yoshinori Nishikitani
  • Publication number: 20110130000
    Abstract: A method of manufacturing a semiconductor device includes preparing a substrate on which a fuze line containing copper is formed. The method further includes cutting the fuze line by emitting a laser beam, and applying a composition for etching copper to the substrate to finely etch a cutting area of the fuze line and to substantially remove at least one of a copper residue and a copper oxide residue remaining near the cutting area. The composition for etching copper includes about 0.01 to about 10 percent by weight of an organic acid, about 0.01 to 1.0 percent by weight of an oxidizing agent, and a protic solvent.
    Type: Application
    Filed: November 17, 2010
    Publication date: June 2, 2011
    Inventors: Jung-Dae PARK, Da-Hee Lee, Seung-Ki Chae, Pil-Kwon Jun, Kwang-Shin Lim
  • Patent number: 7888263
    Abstract: In semiconductor integrated circuit and device fabrication interconnect metallization is accomplished by a clad Ag deposited on a SiO2 level on a Si surface. The clad Ag has a layer of an alloy of Ag and Al (5 atomic %) contacting the SiO2, a layer of substantially pure Ag and an outer layer of the Ag and Al alloy. The alloy improves adhesion to the SiO2, avoids agglomeration of the Ag, reduces or eliminates diffusion at the SiO2 surface, reduces electromigration and presents a passive exterior surface.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: February 15, 2011
    Assignee: Arizona Board of Regents
    Inventors: Terry L. Alford, Ekta Misra
  • Patent number: 7871930
    Abstract: A method of manufacturing a light emitting device is provided in which satisfactory image display can be performed by the investigation and repair of short circuits in defect portions of light emitting elements. A backward direction electric current flows in the defect portions if a reverse bias voltage is applied to the light emitting elements having the defect portions. Emission of light which occurred from the backward direction electric current flow is measured by using an emission microscope, specifying the position of the defect portions, and short circuit locations can be repaired by irradiating a laser to the defect portions, turning them into insulators.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: January 18, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hirokazu Yamagata, Yoshimi Adachi, Noriko Shibata
  • Patent number: 7867903
    Abstract: A method of producing a passivated thin film material is disclosed wherein an insulating thin film layer (10), having pinholes (12) therein, is positioned upon an underlying electrically conductive substrate (11). The thin film layer is then electroplated so that the pinholes are filled with a reactive metal. The thin film layer and substrate are then immersed within a silicon doped tetramethylammonium hydroxide (TMAH) solution. Excess silica within the solution precipitates onto the top surfaces of the aluminum plugs (13) to form an electrically insulative cap which electrically insulates the top of the aluminum plug. As an alternative, the previously described metal plugs may be anodized so that at least a portion thereof becomes an oxidized metal which is electrically insulative.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: January 11, 2011
    Assignee: Johnson Research & Development Co., Inc.
    Inventors: Lonnie G Johnson, Davorin Babic
  • Patent number: 7816260
    Abstract: A method for fabricating a semiconductor device according to the present invention includes: a step for forming a wiring layer on a semiconductor substrate; a step for patterning the wiring layer; and a step for covering the wiring layer with a protective insulating film. Moreover, after the step for forming the wiring layer, all required heat treatment steps to be performed prior to the step for covering the wiring layer with the protective insulating film are performed at a temperature lower than a temperature for plastic deformation of the wiring layer.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: October 19, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Makiko Kageyama
  • Patent number: 7811912
    Abstract: A method for manufacturing a semiconductor device includes the steps of forming a first insulation layer on a substrate; forming a damascene pattern in the first insulation layer; conducting a first process for forming metal lines in the damascene pattern; conducting a second process for forming a second insulation layer, having compressive stress greater than tensile stress of the metal lines, on the damascene pattern including the metal lines; forming a passivation layer on the substrate after multi-layered metal lines are formed by the first and second processes; and conducting an annealing process for the substrate including the passivation layer.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: October 12, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young Geun Jang
  • Patent number: 7799628
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a high-k dielectric over a substrate, forming a first metal layer over the high-k dielectric, forming a second metal layer over the first metal layer, forming a first silicon layer over the second metal layer, implanting a plurality of ions into the first silicon layer and the second metal layer overlying a first region of the substrate, forming a second silicon layer over the first silicon layer, patterning a first gate structure over the first region and a second gate structure over a second region, performing an annealing process that causes the second metal layer to react with the first silicon layer to form a silicide layer in the first and second gate structures, respectively, and driving the ions toward an interface of the first metal layer and the high-k dielectric in the first gate structure.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: September 21, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Shi Liu, Hsiang-Yi Wang, Cheng-Tung Lin, Chen-Hua Yu
  • Patent number: 7790617
    Abstract: A method of fabrication of a sputtered metal silicide layer over a copper interconnect. We form a dielectric layer over a conductive layer. We form an interconnect opening in the dielectric layer. We form a copper layer at least filling the interconnect opening. We planarize the copper layer to form a copper interconnect in the interconnect opening. The copper interconnect is over polished to form a depression. We form metal silicide layer over the copper interconnect using a low temperature sputtering process. We can form a cap layer over the metal silicide layer.
    Type: Grant
    Filed: November 12, 2005
    Date of Patent: September 7, 2010
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Yeow Kheng Lim, Wei Lu, Liang Choo Hsia, Jyoti Gupta, Chim Seng Seet, Hao Zhang
  • Patent number: 7754596
    Abstract: A semiconductor device capable of preventing an electrical short between contacts and their adjacent contact pads and a method of manufacturing the same are provided. A first interlayer insulating layer is formed on the semiconductor substrate including the active region. Contact pads pass through the first interlayer insulating layer and contact with the active region. Contacts are formed on the contact pads and are connected to a conductive layer disposed above the contacts. The contact pads have a height lower than a top surface of the first interlayer insulating layer such that the contact pads have smaller thickness than the first interlayer insulating layer.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: July 13, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Byung-jun Park
  • Patent number: 7745327
    Abstract: By appropriately designing a plurality of deposition steps and intermediate sputter processes, the formation of a barrier material within a via opening may be accomplished on the basis of a highly efficient process strategy that readily integrates conductive cap layers formed above metal-containing regions into well-approved process sequences.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: June 29, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Axel Preusse, Michael Friedemann, Robert Seidel, Berit Freudenberg
  • Patent number: 7737024
    Abstract: A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first layer of TiN. The first layer of TiN is amorphous. The second layer of TiN is polycrystalline, having a mixed grain orientation. Finally, an aluminum film is formed on the second layer of titanium nitride. Optionally, a titanium silicide layer is formed on the semiconductor structure prior to the step of forming the first layer of titanium nitride. Interconnects formed according to the invention have polycrystalline aluminum films with grain sizes of approximately less than 0.25 microns.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: June 15, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Wing-Cheong Gilbert Lai, Gurtei Singh Sandhu
  • Patent number: 7732331
    Abstract: The present invention provides a method of fabricating a semiconductor device, which could advance the commercialization of semiconductor devices with a copper interconnect. In a process of metal interconnect line fabrication, a TiN thin film combined with an Al intermediate layer is used as a diffusion barrier on trench or via walls. For the formation, Al is deposited on the TiN thin film followed by copper filling the trench. Al diffuses to TiN layer and reacts with oxygen or nitrogen, which will stuff grain boundaries efficiently, thereby blocking the diffusion of copper successfully.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: June 8, 2010
    Assignee: ASM International N.V.
    Inventors: Ki-Bum Kim, Pekka J. Soininen, Ivo Raaijmakers
  • Patent number: 7704886
    Abstract: A method of forming an integrated circuit structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form a seed layer in a first chamber; and performing a first etch step to remove a portion of the seed layer. The method may further include performing a second deposition step to increase the thickness of the seed layer. At least one of the first etch step and the second deposition step is performed in a second chamber different from the first chamber.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: April 27, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Lin Su, Shing-Chyang Pan, Cheng-Lin Huang, Ching-Hua Hsieh
  • Patent number: 7704898
    Abstract: Disclosed is an apparatus and a method for reducing flash in an injection mold (532 or 542,543) which molds a molded article between a first mold surface and a second mold surface. The apparatus includes an active material actuator (530 or 533a and 533b or 561a and 561b) configured to, in response to application or removal of an electrical actuation signal thereto, change dimension and urge the first mold surface relative to the second mold surface to reduce flash therebetween. The apparatus also includes a transmission structure (533) configured to provide in use, the electrical actuation signal to said active material actuator (530 or 533a and 533b or 561a and 561b) includes a set of active material actuators stacked one against the other to provide a varying sealing force to urge the first mold surface relative to the second mold surface.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: April 27, 2010
    Assignee: Mattson Technology, Inc.
    Inventors: Zsolt Nenyei, Steffen Frigge, Patrick Schmid, Thorsten Hülsmann, Thomas Theiler
  • Publication number: 20100099257
    Abstract: A method for the vapor deposition of aluminum films is provided. Such method employs a dialkyl amido dihydroaluminum compound of the formula [H2AlNR1R2]n wherein R1 and R2 are the same or different alkyl groups having 1 to 3 carbons, and n is an integer of 2 or 3. The aluminum films may be thick or thin and may be aluminum films or may be mixed metal films with aluminum metal. Both CVD and ALD methods may be employed.
    Type: Application
    Filed: November 16, 2006
    Publication date: April 22, 2010
    Applicant: Rohm and Haas Company
    Inventors: Hyun Koock Shin, Bum Soo Kim, Jin Sik Kim, Jun Young Kim, Young Seop Kim, Bo Yearn Cho
  • Patent number: 7694413
    Abstract: A method for forming a copper interconnect is described. An opening in a dielectric layer disposed on a substrate is formed. A barrier layer is formed on the opening. A seed layer is formed on the barrier layer. The seed layer includes a noble metal copper alloy, the copper having less than 50% of the atomic weight of the noble metal copper alloy.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventors: Steven W. Johnston, Chin-Chang Cheng
  • Patent number: 7696089
    Abstract: A method of producing a passivated thin film material is disclosed wherein an insulating thin film layer (10), having pinholes (12) therein, is positioned upon an underlying electrically conductive substrate (11). The thin film layer is then electroplated so that the pinholes are filled with a reactive metal. The thin film layer and substrate are then immersed within a silicon doped tetramethylammonium hydroxide (TMAH) solution. Excess silica within the solution precipitates onto the top surfaces of the aluminum plugs (13) to form an electrically insulative cap which electrically insulates the top of the aluminum plug. As an alternative, the previously described metal plugs may be anodized so that at least a portion thereof becomes an oxidized metal which is electrically insulative.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: April 13, 2010
    Assignee: Johnson Research & Development Co., Inc.
    Inventors: Lonnie G. Johnson, Davorin Babic
  • Patent number: 7691697
    Abstract: A high-reliability power composite integrated semiconductor device uses thick copper electrodes as current collecting electrodes of a power device portion to resist wire resistance needed for reducing ON-resistance. Furthermore, wire bonding connection of the copper electrodes is secured, and also the time-lapse degradation under high temperature which causes diffusion of copper and corrosion of copper is suppressed. Still furthermore, direct bonding connection can be established to current collecting electrodes in the power device portion, and also established to a bonding pad formed on the control circuit portion in the control circuit portion. A pad area at the device peripheral portion which has been hitherto needed is reduced, so that the area of the device is saved, and the manufacturing cost is reduced.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: April 6, 2010
    Assignee: DENSO CORPORATION
    Inventor: Hiroyasu Itou
  • Publication number: 20100055905
    Abstract: Methods of forming aluminum oxide layers on substrates are disclosed. In some embodiments, the method includes depositing an aluminum oxide seed layer on the substrate using a first process having a first deposition rate. The method further includes depositing a bulk aluminum oxide layer atop the seed layer using a metalorganic chemical vapor deposition (MOCVD) process having a second deposition rate greater than the first deposition rate.
    Type: Application
    Filed: September 3, 2008
    Publication date: March 4, 2010
    Applicant: APPLIED MATERIALS, INC.
    Inventors: SHREYAS S. KHER, CHRISTOPHER S. OLSEN, LUCIEN DATE
  • Patent number: 7659195
    Abstract: A method for forming metal lines of a semiconductor device is disclosed. The metal line forming method includes forming plugs by perforating via-holes in an interlayer dielectric layer formed on a semiconductor substrate and burying a conductive material in the via-holes, sequentially forming at least two metal layers on the interlayer dielectric layer formed with the plugs, the metal layers having a difference in the size of metal grains of each metal layer, etching an uppermost first metal layer of the at least two metal layers using a photoresist pattern formed on the first metal layer as an etching mask using a first etching gas, and etching the partially etched first metal layer using a second etching gas.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: February 9, 2010
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Sang Chul Shim
  • Patent number: 7648904
    Abstract: A metal line in a semiconductor device includes an insulation layer having trenches formed therein, a barrier metal layer formed over the insulation layer and the trenches, a metal layer formed over the barrier metal layer, wherein the metal layer fills the trenches, and an anti-galvanic corrosion layer formed on an interface between the metal layer and the barrier metal layer.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: January 19, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Young-Soo Choi, Gyu-Hyun Kim
  • Patent number: 7645703
    Abstract: A method for chemical mechanical polishing of mirror structures. Such mirror structures may be used for displays (e.g., LCOS, DLP), optical devices, and the like. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method forms a first dielectric layer overlying the semiconductor substrate and forms an aluminum layer overlying the dielectric layer. The aluminum layer has a predetermined roughness of greater than 20 Angstroms RMS. The method patterns the aluminum layer to expose portions of the dielectric layer. The method includes forming a second dielectric layer overlying the patterned aluminum layer and exposed portions of the dielectric layer. The method removes a portion of the second dielectric layer.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: January 12, 2010
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Chris C. Yu, Chunxiao Yang, Ziru Ren, Herb Huang
  • Patent number: 7628896
    Abstract: A transparent conductive oxide (TCO) based film is formed on a substrate. The film may be formed by sputter-depositing, so as to include both a primary dopant (e.g., Al) and a co-dopant (e.g., Ag). The benefit of using the co-dopant in depositing the TCO inclusive film may be two-fold: (a) it may prevent or reduce self-compensation of the primary dopant by a more proper positioning of the Fermi level, and/or (b) it may promote declustering of the primary dopant, thereby freeing up space in the metal sublattice and permitting more primary dopant to create electrically active centers so as to improve conductivity of the film. Accordingly, the use of the co-dopant permits the primary dopant to be more effective in enhancing conductivity of the TCO inclusive film, without significantly sacrificing visible transmission characteristics. An example TCO in certain embodiments is ZnAlOx:Ag.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: December 8, 2009
    Assignee: Guardian Industries Corp.
    Inventors: Alexey Krasnov, Yiwei Lu
  • Publication number: 20090291545
    Abstract: Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films on semiconductor substrates as well as the uniform and precise removal of materials from such substrates. In one embodiment, the process includes, providing a supercritical fluid containing at least one reactant, the supercritical fluid being maintained at above its critical point, exposing at least a portion of the surface of the semiconductor substrate to the supercritical fluid, applying acoustic energy, and reacting the at least one reactant to cause a change in at least a portion of the surface of the semiconductor substrate.
    Type: Application
    Filed: August 6, 2009
    Publication date: November 26, 2009
    Applicant: Micron Technology, Inc.
    Inventors: Theodore M. Taylor, Stephen J. Kramer
  • Patent number: 7615868
    Abstract: There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 sequentially stacked in this order on the semiconductor film 101, characterized in that the first metal film 102 is formed of Al, and the second metal film 103 is formed of at least one metal selected from the group consisting of Nb, W, Fe, Hf, Re, Ta and Zr.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: November 10, 2009
    Assignee: NEC Corporation
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yuji Ando, Takashi Inoue, Yasuhiro Okamoto, Masaaki Kuzuhara
  • Patent number: 7611615
    Abstract: The present invention provides a process for manufacturing a porous metal electrode, wherein the porosity degree is in the range of 30 to 50% and the metal is capable of forming a stable, uniform, oxide layer having a dielectric constant greater than 25 (k?25), preferably selected from the group consisting of tantalum and niobium, comprising a substantially uniform porous layer of deposited said metal particles thereon. The present invention further relates to a stable suspension for electrophoretically homogeneously deposition of said metal.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: November 3, 2009
    Assignee: Cerel (Ceramics Technologies) Ltd.
    Inventors: Nissim Cohen, Israel Schuster, Ludmila Cherniak, Tali Peled
  • Publication number: 20090267232
    Abstract: An integrated circuit (100) is provided that comprises a substrate (140) of silicon and an interconnect (130) in a through-hole extending from the first to the second side of the substrate. The interconnect is coupled to a metallisation layer (120) on the first side of the substrate and is provided on an amorphous silicon layer that is present at a side wall of the through-hole, and particularly at an edge thereof adjacent to the first side of the substrate. The interconnect comprises a metal stack of nickel and silver. A preferred way of forming the amorphous silicon layer is a sputter etching technique.
    Type: Application
    Filed: September 17, 2007
    Publication date: October 29, 2009
    Applicant: NXP, B.V.
    Inventors: Stephane Morel, Arnoldus Den Dekker, Elisabeth C. Rodenburg, Eric C. E. Van Grunsven
  • Patent number: 7608535
    Abstract: An interlayer insulation layer is formed on a semiconductor substrate to cover a lower wiring layer that is also formed on the semiconductor substrate. A contact hole to expose a surface of the lower wiring layer is formed by etching the interlayer insulation film. A wetting layer is formed on an inner wall of the contact hole. An anti-deposition layer is formed around an entrance of the contact hole to prevent an aluminum layer from being deposited around the entrance of the contact hole. The contact hole is filled with the aluminum layer.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: October 27, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyun Phill Kim
  • Patent number: 7601641
    Abstract: Methods are provided for etching during fabrication of a semiconductor device. The method includes initially etching to partially remove a portion of one or more lithographic-aiding layers overlying an oxide layer while etching a first portion of the oxide layer in accordance with a mask formed by the one or more lithographic-aiding layers, and thereafter additionally etching to remove remaining portions of the one or more lithographic-aiding layers while etching a remaining portion of the oxide layer.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: October 13, 2009
    Assignee: Global Foundries, Inc.
    Inventors: Erik Geiss, Christopher Prindle, Sven Beyer
  • Patent number: 7585692
    Abstract: A thin film layer, a heating electrode, a phase change memory including the thin film layer, and methods for forming the same. The method of forming the thin film layer by atomic layer deposition (ALD) may include injecting a titanium (Ti) source, a nitrogen (N) source, and/or an aluminum (Al) source onto a substrate at different flow rates and for different periods of time. The heating electrode may include a Ti1?xAlxN layer, wherein x is about 0.4<x<0.5 at a first portion of the heating electrode contacting a phase change layer and 0<x<0.1 at other portions of the heating electrode. The phase change memory may include the heating electrode including the Ti1?xAlxN layer, an insulating layer formed on the heating electrode and having a contact hole exposing the heating electrode and the phase change layer contacting the first portion of the heating electrode.
    Type: Grant
    Filed: January 4, 2006
    Date of Patent: September 8, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Choong-Man Lee
  • Patent number: 7579051
    Abstract: A method for manufacturing an electron emitter, the method includes discharging a droplet of a function liquid containing a material for forming the conductive film onto a discharge surface of the substrate by a droplet discharge device to adhere a liquid-state object to at least part of an area in which the conductive film is to be formed, drying the liquid-state to form the conductive film, and forming an electron emission section in the conductive film by applying an current between the pair of element electrodes, wherein when accompanied by the drying to form the conductive film, the discharging forms the liquid-state object in a shape having a constricted part for forming a latent image section that has a relatively thin film thickness in a portion for forming the electron emitter.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: August 25, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Makoto Yoshida
  • Patent number: 7575963
    Abstract: First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a semiconductor layer an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: August 18, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyang-Shik Kong, Myung-Koo Hur, Chi-Woo Kim