Substrate Dicing Patents (Class 438/68)
  • Patent number: 6274458
    Abstract: A device is provided for cleaving semiconductor products or the like. The device may be formed of an inlet for receiving pressurized gas, an adjustable slot for directing the gas toward the products, and a movable flow control member. According to one aspect of the invention, the flow control member is located within a housing that also defines the inlet and the adjustable slot. A cover may be located on the front of the housing. The cover may have a lower edge that forms one side of the slot. The other side of the slot may be formed by the movable flow control member. The cleave device may have an uncomplicated, compact construction. The cleave device may be operated with a flexible product handling system. That is, the brittle products may be handled within opposed flexible sheets. The sheets may be used to locate the products over a ledge (a cleaving position) where they are bent to cause cleaving along crystal planes initiated at scribe or score lines.
    Type: Grant
    Filed: July 7, 1999
    Date of Patent: August 14, 2001
    Assignee: Agere Systems Optoelectronics Guardian Corp.
    Inventors: Joseph Michael Freund, George John Przybylek, Dennis Mark Romero
  • Patent number: 6265652
    Abstract: An integrated thin-film solar battery having a plurality of unit elements connected in series includes a substrate, a plurality of spaced apart first electrode layers formed on the substrate; a plurality of semiconductor layers disposed on said plurality of first electrode layers in such a manner that each of the semiconductor layers is formed on two adjacent first electrodes and has a connection opening located on one of the two first electrodes, an electrically conductive layer formed on each of the semiconductor layers except on the region of the connection opening, and a second electrode layer disposed on each of the electrically conductive layers such that the second electrode layer is electrically connected to one of the two adjacent first electrode layers through the connection opening, to form a region interposed between the second electrode layer and the other first electrode layer as the unit element.
    Type: Grant
    Filed: March 3, 1998
    Date of Patent: July 24, 2001
    Assignee: Kanegafuchi Kagaku Kogyo Kabushiki Kabushiki Kaisha
    Inventors: Shinichiro Kurata, Katsuhiko Hayashi, Atsuo Ishikawa, Masataka Kondo
  • Patent number: 6225191
    Abstract: The specification describes wafer fabrication cleaning processes for silicon optical bench technology. The cleaning processes are designed to remove debris in situ after dicing silicon wafers mounted on a tape carrier. They were also developed specifically to avoid staining and residues that often result from using standard dicing approaches in silicon optical bench integrated circuit manufacture.
    Type: Grant
    Filed: April 12, 1996
    Date of Patent: May 1, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Louis Nelson Ahlquist, Mark Anthony Cappuzzo, Louis T. Gomez, Joseph Shmulovich, Judith Martin Szalkowski
  • Patent number: 6203871
    Abstract: An article, specifically an inkjet printhead, having electrical leads in an aqueous environment in which the leads are encapsulated in a thoroughly cured mixture of 88 parts bis-phenol A epoxy oligomer, 11 parts epoxy novolac oligomer, and 1 part triarylsulfonium hexafluoroantimonate salts. No special atmosphere is required during manufacture and the uncured mixture has a long pot life. The cured mixture has excellent resistance to an aqueous environment.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: March 20, 2001
    Assignee: Lexmark International, Inc.
    Inventor: Girish Shivaji Patil
  • Patent number: 6168965
    Abstract: A method for producing a back-illuminated CMOS image sensor including a matrix of pixels (e.g., CMOS APS cells) that are fabricated on a semiconductor substrate. The semiconductor substrate is secured to a protective substrate by an adhesive such that the processed (frontside) surface of the semiconductor substrate faces the protective substrate. With the protective substrate providing structural support, the exposed backside surface of the semiconductor substrate is then subjected to grinding and/or chemical etching, followed by optional chemical/mechanical processing, to thin the semiconductor substrate to a range of 10 to 15 microns. A transparent substrate (e.g., glass) is then secured to the backside surface of the semiconductor substrate, thereby sandwiching the semiconductor substrate between the transparent substrate and the protective substrate.
    Type: Grant
    Filed: August 12, 1999
    Date of Patent: January 2, 2001
    Assignee: Tower Semiconductor Ltd.
    Inventors: Yacov Malinovich, Ephie Koltin
  • Patent number: 6165815
    Abstract: A method for increasing integrated circuit density comprising stacking an upper wafer and a lower wafer, each of which have fabricated circuitry in specific areas on their respective face surfaces. The upper wafer is attached back-to-back with the lower wafer with a layer of adhesive applied over the back side of the lower wafer. The wafers are aligned so as to bring complimentary circuitry on each of the wafers into perpendicular alignment. The adhered wafer pair is then itself attached to an adhesive film to immobilize the wafer during dicing. The adhered wafer pair may be die into individual die pairs or wafer portions containing more than one dice pair. At least one face side of the die pair (attachment side) may have an array of minute solder balls or small pins disposed thereon for attachment and electrical communication of the die to at least one substrate such as a printed circuit board or leadframe.
    Type: Grant
    Filed: April 18, 1997
    Date of Patent: December 26, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Michael B. Ball
  • Patent number: 6165813
    Abstract: Semiconductor chips, such as photosensor arrays for a full-page-width scanner or printhead chips for a full-page-width ink-jet printer, are mounted on a substrate to maintain reasonably consistent spacing among adjacent chips. To remove a defective chip from the array, the substrate is urged evenly against a work surface defining a convex bow. Alternately, back-cuts are provided along abutting edges of the chips, and the silicon around these back-cuts can be sawed away to space defective chips from neighboring good chips.
    Type: Grant
    Filed: April 3, 1995
    Date of Patent: December 26, 2000
    Assignee: Xerox Corporation
    Inventors: Kraig A. Quinn, Brian T. Ormond, Josef E. Jedlicka
  • Patent number: 6107162
    Abstract: A semiconductor device such as a semiconductor layer is formed of a compound semiconductor layer of III-V group such as GaN. In the case where the substrate has not any planes that are easy to cleave which coincides with an easy-to-cleave plane of a semiconductor layer grown on the substrate or the substrate easily succumbs to cleavage, then the semiconductor layer together with the substrate can be broken into chips in an easy-to-cleave plane. The cleaved surface of the semiconductor layer can be positively formed as an optically superior surface. A compound semiconductor layer 2 containing at least one of the elements {Ga, Al, In} and N is formed on the substrate 1. This compound semiconductor layer 2 has a pair of facets of {11-20} plane substantially perpendicular to the substrate 1.
    Type: Grant
    Filed: April 14, 1998
    Date of Patent: August 22, 2000
    Assignee: Sony Corporation
    Inventors: Etsuo Morita, Hiroji Kawai
  • Patent number: 6102267
    Abstract: An apparatus and a method for non-contact cleaving a brittle, non-metallic solid material, such as semiconductor material, glass, quartz, ceramic or like material. A pulsating gas jet directs a jet of gas toward a support structure formed of a non-compliant material. The semiconductor material is positioned on the support structure between a pair of film layers. The semiconductor material is scored in at least one location on the material. A plastic buffer material is adhered to the support structure. The semiconductor material and the film layers are moved along the support structure until the score line is at a ledge of the support structure and underneath the source of gas. The jet of gas applies a sufficient force to cleave the semiconductor material as it passes off the ledge of the support structure, while minimizing vibration and/or turbulence. The buffer provides cushioning and inhibits the formation of fractures during the cleaving process.
    Type: Grant
    Filed: December 10, 1998
    Date of Patent: August 15, 2000
    Assignee: Lucent Technologies, Inc.
    Inventors: Joseph Michael Freund, William Andrew Gault, George John Przybylek, Dennis Mark Romero, John William Stayt, Jr.
  • Patent number: 6048747
    Abstract: A cleaving apparatus for separating a wafer (or bar) bar of optical devices into separate bars (or individual optical devices) comprises a relatively thin wire, preferably tungsten. The wire is forced against the underside of the bar directly underneath the location of a top side scribe mark. The wire, having a highly uniform, well-controlled radius of curvature, induces a known, reproducible stress through the body of the bar and nucleates a cleavage crack under the scribe mark. A force applied to the top surface of the bar will allow the cleaving crack to propagate cleanly along a single crystal surface through the depth of the bar to the location of the wire.
    Type: Grant
    Filed: May 1, 1998
    Date of Patent: April 11, 2000
    Assignee: Lucent Technologies, Inc.
    Inventors: Utpal Kumar Chakrabarti, David Reese Peale
  • Patent number: 6046070
    Abstract: A method of post-processing a solid-state imaging device including a wafer processing step 1 (S1), an assembly step 2 (S2) in which packaging is performed, an inspection step 3 (S3), and an annealing step (S4) in which a solid-state having gone through the inspection step 3 is annealed at a predetermined temperature. The method makes it possible to reduce the level of an image defect that occurs after assembly.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: April 4, 2000
    Assignee: Sony Corporation
    Inventors: Hiroo Shoji, Takayuki Iizuka
  • Patent number: 6027622
    Abstract: A sensor element for an electrochemical sensor that determines the oxygen content of exhaust gases produced by internal combustion engines. The sensor element includes at least one measurement device and at least one heating device associated with the measurement device. The measurement device and the heating device both include individual functional layers laminated one above another. The heating device is covered with a surface layer that covers not only the surface of the outermost layer of the functional layers of the heating device, but also the side surfaces of all the functional layers of the heating device.
    Type: Grant
    Filed: May 18, 1998
    Date of Patent: February 22, 2000
    Assignee: Robert Bosch GmbH
    Inventors: Theodor Graser, Hnas-Joerg Renz
  • Patent number: 6027956
    Abstract: A method is shown for producing a PIN photodiode wherein an intrinsic layer of the photodiode can be made arbitrarily thin. A fabrication substrate is lightly doped to have a first conductivity type in order to form the intrinsic layer of the photodiode. A first active region of the photodiode having the first conductivity type is formed on a first surface of the fabrication substrate. An oxide layer is also formed upon the first surface of the fabrication substrate. A handling substrate is bonded to the first surface of the fabrication substrate. A second surface of the fabrication is then lapped to a obtain a preselected thickness of the intrinsic layer. And a second active region of the photodiode having a second conductivity type is formed on the second surface of the fabrication substrate.
    Type: Grant
    Filed: February 5, 1998
    Date of Patent: February 22, 2000
    Assignee: Integration Associates, Inc.
    Inventor: Pierre Irissou
  • Patent number: 6017804
    Abstract: The invention disclosed is a method and apparatus for cleaving semiconductor material without physical contact. Tick marks are formed in a major surface of the material where cleaving is desired. A fulcrum member is moved with respect to the material until a tick mark is in alignment with the fulcrum member. A gas jet, also aligned with the fulcrum member, is applied to the surface of the material to form the cleave.
    Type: Grant
    Filed: January 9, 1998
    Date of Patent: January 25, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Joseph Michael Freund, George John Przybylek, Dennis Mark Romero, John William Stayt, Jr.
  • Patent number: 6013873
    Abstract: A photovoltaic apparatus includes a first conductive layer, a semiconductor layer and a second conductive layer on a substrate. The first conductive layer is divided into a first electrode layer and into a peripheral first electrode layer by the lower peripheral groove filled up with a first peripheral insulating material. The first upper peripheral groove is provided at the upper portion of the lower peripheral groove, to divide the semiconductor layer and the second conductive layer. The second peripheral insulating material is provided at the outer region of the lower peripheral groove to divide the semiconductor layer. The second upper part peripheral groove is provided at the upper part of the second peripheral insulating material to divide the semiconductor layer and the second conductive layer.
    Type: Grant
    Filed: January 29, 1998
    Date of Patent: January 11, 2000
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Naoki Daito, Toshihiro Nomura, Ryuji Okawa, Koji Katsube, Yoshinobu Takabatake
  • Patent number: 5998234
    Abstract: On a back face of a silicon wafer before dicing, tapered grooves having sloped side walls are formed by anisotropic etching along with thin portions. Strain gauges are formed on each thin portion, thereby forming a sensor chip on the silicon wafer. The back face of the silicon wafer is attached to a self-adhesive seat. Thereafter, the silicon wafer is cut along the grooves by a dicing blade to divide it into each sensor chip. In dicing, the side faces of the dicing blade cut the sloped side walls of the tapered grooves. As a result, the silicon wafer is diced into individual sensor chip having no cracks and chippings.
    Type: Grant
    Filed: March 28, 1997
    Date of Patent: December 7, 1999
    Assignee: Denso Corporation
    Inventors: Minoru Murata, Kenichi Ao, Yasutoshi Suzuki, Seiichiro Ishiou
  • Patent number: 5994762
    Abstract: A semiconductor integrated circuit device is provided in which an interlayer insulation film deposited on a semiconductor chip includes a boron-containing silicon oxide film and a second film deposited on the boron-containing silicon oxide film. A guard ring is disposed adjacent to the periphery of the semiconductor chip, and a slit is disposed between the guard ring and the periphery of the chip. The depth of the slit is selected such that cracks formed on the boundary between the BPSG film and the second film are inhibited by the slit from intruding further along the boundary to the inside of the chip, thereby preventing moisture or obstacles from reaching the inside of the chip through the cracks.
    Type: Grant
    Filed: July 26, 1996
    Date of Patent: November 30, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Naokatsu Suwanai, Yasuhide Fujioka
  • Patent number: 5985687
    Abstract: Optically flat cleaved facet mirrors are fabricated in GaN epitaxial films grown on sapphire by wafer fusing a GaN film with a sapphire substrate to a cubic substrate such as an InP or GaAs substrate. The sapphire substrate may then partially or entirely removed by lapping, dry etching, or wet etching away a sacrificial layer disposed in the interface between the sapphire substrate and the GaN layer. Thereafter, the cubic InP or GaN substrate is cleaved to produce the cubic crystal facet parallel to the GaN layer in which active devices are fabricated for use in lasers, photodetectors, light emitting diodes and other optoelectronic devices.
    Type: Grant
    Filed: April 12, 1996
    Date of Patent: November 16, 1999
    Assignee: The Regents of the University of California
    Inventors: John E. Bowers, R. Kehl Sink, Steven P. Denbaars
  • Patent number: 5985690
    Abstract: A contact image sensor has a plurality of sensor elements on an insulating substrate, the sensor elements having electrodes as common electrodes and other electrodes as individual electrodes. The contact image sensor is manufactured by extending the common electrodes and the individual electrodes out of a document passage region, and forming short-circuiting patterns which electrically connect the common electrodes and the individual electrodes outside of the document passage region through pads which connect ICs for energizing the contact image sensor. After the ICs are connected to the pads, the insulating substrate is cut along the short-circuiting patterns to break the electrical connection between the common electrodes and the individual electrodes.
    Type: Grant
    Filed: January 18, 1996
    Date of Patent: November 16, 1999
    Assignee: NEC Corporation
    Inventor: Katsuyuki Fujikura
  • Patent number: 5972729
    Abstract: A method of manufacturing a light-emitting or a light-receiving diode array chip. A first interlayer dielectric is formed in each of a plurality of chip areas on a substrate of a first conductivity type. Impurity diffusion regions of a second conductivity type are formed in the substrate using the first interlayer dielectric as a diffusion mask. An electrode is formed in contact with each of the impurity diffusion regions. The substrate is separated so that the plurality of chip areas are separated into individual chips. A second interlayer dielectric may be formed on the first interlayer dielectric after forming the impurity diffusion regions. The second interlayer dielectric is formed such that the second interlayer dielectric is absent from a second area along which the substrate is separated into the individual chips, at least in the vicinity of the last one of a plurality of windows.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: October 26, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Takatoku Shimizu, Mitsuhiko Ogihara, Masumi Taninaka, Hiroshi Hamano
  • Patent number: 5963785
    Abstract: In a semiconductor integrated circuit consisting of a plurality of semiconductor chips each having a plurality of islands, two or more bonding wires each having different potential are connected to bonding pads formed on the surface of semiconductor chips. The islands are isolated by a dielectric isolation region comprising polysilicon film and isolation film formed in an isolation groove. The polysilicon film is exposed at a dicing line region around the semiconductor chip and a surface of the polysilicon film is made highly resistive. If two or more bonding wires come into contact with the polysilicon film exposed at a peripheral region of the semiconductor chip to cause short circuit, parasitic conductance does not occur between two or more bonding wires because the peripheral region of the semiconductor chip has high resistivity, whereby variation in characteristics of the semiconductor integrated circuit can be suppressed.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: October 5, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshimitu Katoh, Yoshiaki Aizawa, Hisaya Okumura
  • Patent number: 5932114
    Abstract: An optical module includes support substrate, an optical waveguide on the support substrate, a photoreception device on the support substrate, an optical path conversion part for converting an optical path of an optical beam guided through the optical waveguide from a first optical path to a second optical path that leads to a photodetection area of said photoreception device, wherein the optical path conversion part is provided on the photodetection device as a part thereof, such that the optical beam emitted from the optical waveguide impinges upon the photodetection area of the photoreception device.
    Type: Grant
    Filed: September 12, 1997
    Date of Patent: August 3, 1999
    Assignee: Fujitsu Limited
    Inventor: Masao Makiuchi
  • Patent number: 5897330
    Abstract: A thermoelectric power generation unit comprises a plurality of dissimilar thermoelectric structures (20, 21) laid in alternating layers. Adjacent thermoelectric bodies incorporated in each of the thermoelectric structures are connected together in series. Respective thermoelectric structures are fabricated by the steps of forming a stripe-shaped pattern on a substrate (10) using a photosensitive resin (12), forming a polymer film on the underside of the substrate, forming first thermoelectric bodies (15) and second thermoelectric bodies (17) by plating on an electrode film (11) inside openings of the photosensitive resin, coating the first thermoelectric bodies (15) and second thermoelectric bodies (17) with a thermosetting resin (16), dissolving the substrate (10) and electrode film (11) thereafter.
    Type: Grant
    Filed: November 14, 1996
    Date of Patent: April 27, 1999
    Assignee: Citizen Watch Co., Ltd.
    Inventors: Shigeru Watanabe, Yoichi Nagata
  • Patent number: 5895226
    Abstract: Two kinds of metal patterns 12, 13 are formed on a semiconductor wafer 11 to deposit a surface protective film 14 on the entirety of the surface to implement patterning to the surface protective film 14 so that the surface of the metal pattern 12 at least on dicing lines of the metal patterns 12, 13 is exposed to deposit barrier metal 15 on the entirety of the surface to remove, by etching, at the same time, portions on the dicing lines of the barrier metal 15 and the metal pattern 12 on the dicing lines of the metal patterns 12, 13 to carry out dicing with respect to the semiconductor wafer 11 along the dicing lines from which the metal pattern 12 has been removed to thereby prevent that the end portion of the metal pattern turned up by dicing comes into contact with inner lead or bonding wire so that any failure takes place.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: April 20, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Baba, Maiko Suzaki
  • Patent number: 5874747
    Abstract: A green-blue to ultraviolet light emitting semiconductor laser having a top contact, a Bragg reflector, cladding layer, active layer, cladding layer, buffer, substrate, bottom contact and a passivation layer. The key aspect is a Ga*N material on a base structure comprising a SiC substrate selected from a group consisting of 2H-SiC, 4H-SiC and a-axis oriented 6H-SiC. Furthermore, the cladding layers have larger band gaps than the active layer and are complimentarily doped.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: February 23, 1999
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Joan Redwing, Michael A. Tischler
  • Patent number: 5872386
    Abstract: A wafer layout for a multi-channel device for improving the yield of operative devices comprises a semiconductor wafer and a plurality of semiconductor devices formed in the semiconductor wafer, each device comprising a consecutive series of impurity regions formed in the semiconductor wafer, the impurity regions being arranged consecutively without separation between the respective semiconductor devices, such that each of the semiconductor devices is indistinguishable from the others, without regard to defective devices, and a single semiconductor device comprising a plurality of consecutive impurity regions formed in the semiconductor wafer may be cut from the wafer by cutting therefrom any of the plurality of consecutive impurity regions formed therein. The invention is particularly useful for the fabrication of strip diodes and the like.
    Type: Grant
    Filed: July 16, 1996
    Date of Patent: February 16, 1999
    Assignee: SII R&D Center Inc.
    Inventors: Keiji Sato, Yutaka Saito
  • Patent number: 5827757
    Abstract: A large imaging panel useful for direct radiography is prepared from two or four discrete modules, or tiles, containing arrays of solid state pixels. In preparing the large panels, a protective layer is applied over the array of solid state pixels on each module to protect the modules during subsequent processing steps. One or two edges of each protected module is trimmed and polished to form a polished edge which is within a specified distance from the solid state pixels of the array. The polished edges typically are surface treated (e.g., by etching) to enhance wetting and adherence of applied adhesive material. Protected modules are then assembled on a flat surface to form a two-dimensional mosaic of the modules in a way that each polished edge of each module is placed adjacent to the polished edge of a neighboring module to form a gap and a precise separation between the pixels of neighboring modules which is the same as the separation between adjacent pixels of one of the modules.
    Type: Grant
    Filed: July 16, 1996
    Date of Patent: October 27, 1998
    Assignee: Direct Radiography Corp.
    Inventors: George D. Robinson, Jr., Joseph A. Perrotto, Lothar S. Jeromin, James E. Davis
  • Patent number: 5814532
    Abstract: Disclosed is a method of manufacturing a semiconductor laser. A wafer having a substrate having a semiconductor layer including a light-emitting forming portion epitaxially grown on a surface of the substrate is broken into laser chips having a light-emitting surface at an end face thereof. When breaking the wafer into the chips, the breaking at the light-emitting surface is carried out by first forming street grooves in the substrate and thereafter cleaving the light-emitting layer forming portion. By doing so, there is no necessity of thinning the substrate to a required extent, facilitating handling during the manufacture process. A roughened surface of the street groove is provided in the substrate underlying the light-emitting layer forming portion, which is convenient for irregular reflection of a return light beam often encountered in an optical disc pickup device.
    Type: Grant
    Filed: April 29, 1997
    Date of Patent: September 29, 1998
    Assignee: Rohm Co., Ltd.
    Inventor: Jun Ichihara
  • Patent number: 4833080
    Abstract: Regulation of eucaryotic gene expression is controlled by procaryotic peptides. The peptides recognize specific DNA sequences present in the gene, which may be derived from procaryotic genes, and either activate or repress gene transcription. Hybrid procaryotic peptides may be used containing both repressor and activator peptides.
    Type: Grant
    Filed: December 12, 1985
    Date of Patent: May 23, 1989
    Assignee: President and Fellows of Harvard College
    Inventors: Roger Brent, Mark S. Ptashne