Abstract: A solar cell with buried contacts in recesses (7) on a first surface (2). On a lateral face (4), a metal layer (12) is produced. The metal layer (12) extends into a lateral zone (9) of a second surface (3) opposite the first surface (2). The metal layer serves as a first electrode (14). On the second surface (3) a second electrode (15), electrically separate from the first electrode (14), is produced so that the solar cell is provided with a back connection.

Abstract: A method of aligning a plurality of empty-spaced buried patterns formed in semiconductor monocrystalline substrates is disclosed. In an exemplary embodiment, high-temperature metal marks are formed to include a conductive material having a melting temperature higher than an annealing temperature used to form such empty-spaced buried patterns. The high-temperature metal marks are formed prior to the formation of the empty-spaced buried patterns formed in a monocrystalline substrate, so that the empty-space buried patterns are aligned to the marks. Subsequent semiconductor structures that are formed as part of desired semiconductor devices can be also aligned to the marks.

Abstract: In order to have a thin type semiconductor chips featuring a high yield and a low cost in production, an excellent packaging reliability, and a robust structure against damages, there is provided a method of manufacturing LSI chips, comprising the steps of: pasting on a substrate an adhesive sheet which retains its adhesive strength prior to a processing, then loses it after the processing; bonding non-defective LSI chips on the adhesive sheet, with their device surfaces facing downward; uniformly coating an insulating film on the non-defective LSI chips; uniformly grinding the insulating film to a level of the bottom surfaces of these LSI chips; applying a predetermined process to the adhesive sheet to weaken its adhesive strength thereof so as to peel off a pseudo wafer on which the non-defective LSI chips are bonded; and dicing the LSI chips into a discrete non-defective electronic component by cutting the pseudo wafer.

Abstract: The invention relates to the making of color image sensors for miniature cameras.

Abstract: Methods are provided to improve the adhesive bonding of a semiconductor die to a substrate through an adhesive paste by forming a layer of silicon dioxide on the back surface of the semiconductor die prior to applying the adhesive paste. Contacting the semiconductor die with ozone, in a gas mixture or in a mixture with water provides rapid oxidation of the silicon layer at the back of the semiconductor die to a silicon dioxide layer of at least 10 angstroms thick, which is sufficient to greatly improve bonding to the adhesive. The formation of a silicon dioxide surface layer prior to application of the adhesive is particularly beneficial when combined with rapid, snap curing processes, where the adhesive can be reliably cured by heating the semiconductor die for less than about 1 minute.

Abstract: A method for separating chips from a diamond wafer comprising a substrate, a chemically vapor-deposited diamond layer, and microelectronic elements, with the microelectronic elements protected from thermal damage and degradation caused by the thermally decomposed cuttings produced during the processing steps. (1) Front-side grooves 6 are formed on the chemically vapor-deposited diamond layer 2 by laser processing using a laser such as a YAG, CO2, or excimer laser each having a large output so that the grooves 6 can have a depth 1/100 to 1.5 times the thickness of the diamond layer. (2) The thermally decomposed cuttings produced during the laser processing are removed by using a plasma. (3) Back-side grooves 9 are formed on the substrate 1 by dicing such that the back-side grooves 9 are in alignment with the front-side grooves 6. (4) The diamond wafer 4 is divided into individual chips 10 by applying mechanical stresses.

Abstract: A solid-state image pickup apparatus having hermetic seal portion capable of packaged in a smaller size by a simple construction and fabricated with high precision at wafer level is constructed such that an epoxy-type resin sheet having opening portion only at light-receiving portion is adhered to solid-state image pickup device chip by an adhesive and a transparent member capable of becoming a flat-plate portion is adhered onto the epoxy-type resin sheet by means of an adhesive.

Abstract: A method of manufacturing a semiconductor device includes (a) connecting a first substrate with a second substrate disposed to be stacked on the first substrate and (b) cutting the first substrate and the second substrate in the same process with a cutting tool. The cutting tool includes a plurality of cutters disposed close to each other, having different cut widths and the first substrate and the second substrate are cut with the cutting tool so that the first substrate and the second substrate have different cut widths, in step (b).

Abstract: A method is used for forming sliders for use in a disc drive actuation system. The method comprises providing a wafer formed of a substrate having a base coat and an overcoat. Wafer-level notch lanes having a first width extend across the wafer in a first direction. The overcoat is removed from the wafer-level notch lanes. The wafer is sliced along a portion of the wafer-level lanes through the base coat to form a channel. The wafer is mechanically sliced through the substrate along slice lanes that extend across the wafer in the first direction to differentiate the wafer into bars. The bars are cut in a second direction substantially perpendicular to the first direction to form the sliders.

Abstract: A method of using protective caps (160) applied to a first side of a wafer (150) in the production of microfabricated devices (152), such as micro-electro-mechanical systems (MEMS) devices. One cap (160) covers each microfabricated device or group respectively, such that a gap remains between adjacent protective caps. One or more etches are applied to the gaps between the caps to remove material and separate the wafer into separate units.

Abstract: The present invention relates to a method of manufacturing a semiconductor substrate including the back grind step, the dicing step, the pick up step, and the die bonding step of the wafer; and to a semiconductor substrate jig used in such method. The object of the present invention is to mitigate the effect and to prevent damage caused by the lack of strength in thinned semiconductor substrates. A jig with an outer frame 21, and a rubber film 22 arranged within the outer frame 21 and having increasing and decreasing body size while deforming its shape by supplying air therein are provided. As the volume of the rubber film 22 increases, the wafer-fixing jig 20 deforms the rubber film and allows the tapes 2 and 6 arranged between the wafer 1 and the rubber film 22A to be pushed toward the wafer 1 gradually from the center outward. The attachment step, the back grind step, the tape reapplication step, the pick up step and the die bonding step are conducted using such wafer-fixing jig.

Abstract: The invention provides a method for increasing the usable surface area of a semiconductor wafer having a substantially planar surface and a thickness dimension at right angles to said substantially planar surface, the method including the steps of selecting a strip thickness for division of the wafer into a plurality of strips, selecting a technique for cutting the wafer into the strips at an angle to the substantially planar surface, in which the combined strip thickness and width of wafer removed by the cutting is less than the thickness of the wafer, cutting the wafer into strips using the selected technique and separating the strips from each other.

Abstract: Disclosed is an image sensor module applied to a thin image sensor device. A method of fabricating the image sensor module consists of the steps of forming a bump on a glass, attaching the glass to an image sensor at a wafer level, and firstly and secondly dicing the resulting structure. Therefore, the present invention is advantageous in that fabrication of an inferior image sensor module is reduced, thus improving a quality of the image sensor module, productivity of the image sensor module is improved because the image sensor module is fabricated at the wafer level, and a gold wiper process is omitted, thus reducing fabrication costs of the image sensor module.

Abstract: A method for increasing the yield of image sensor die and packaging is disclosed. The method comprises first forming a plurality of image sensor die having micro-lenses onto a semiconductor wafer. Next, a protective layer is formed over the image sensor die. The wafer is then diced to separate the image sensor die. The image sensor die are then mounted onto an integrated circuit package. Finally, the protective layer is removed from the image sensor die.

Abstract: A micromachine manufacturing method according to this invention includes at least the movable portion formation step of selectively etching a single-crystal silicon layer by using a movable portion formation mask pattern as a mask, thereby forming on the single-crystal silicon layer a movable portion which is coupled to the surrounding single-crystal silicon layer via a coupling portion on a buried oxide, the movable portion protective film formation step of forming a movable portion protective film on the single-crystal silicon layer so as to cover the movable portion while the movable portion is formed on the buried oxide, and the step of forming a buried protective film which covers the movable portion exposed in the substrate opening and movable portion opening, and the single-crystal silicon layer around the movable portion while the movable portion protective film is formed.

Abstract: Devices for manipulating, receiving and dispensing diced semiconductor materials, in which the semiconductor material is diced to provide partially connected dice in linear aggregations.

Abstract: An image sensor package and methods for simultaneously fabricating a plurality of such packages. A layer of barrier material comprising a matrix of raised walls is formed around chip attachment areas located in an array on a carrier substrate to create chip cavities. Image sensor chips are wire bonded within the chip cavities, and a unitary transparent cover is sealed in place over the entire assembly. The resultant image sensor package array is then singulated along lines running between the chip attachment areas and in parallel to the raised walls to provide individual image sensor packages. The layer of barrier material may be formed directly on the carrier substrate by molding methods or by depositing a series of curable layers of liquid or flowable material in a stacked fashion. Alternatively, the layer of barrier material may be preformed as a unitary frame and then secured to the carrier substrate.

Abstract: A plurality of micromirror chips are collectively made from a common substrate. Each of the micromirror chips is formed with a micromirror unit including a frame, a mirror-forming portion separate from the frame via spaces, and torsion bars connecting the mirror-forming portion to the frame. The common substrate is subjected to etching to provide the spaces and make division grooves for dividing the common substrate into the individual micromirror chips. The etching for the spaces and the etching for the division grooves are performed in parallel with each other.

Abstract: A passive mechanism suppresses injection, into any active guard regions interposed between the edge of a photodiode array chip and the outer photodiode pixels or into the outer pixels themselves, of minority carrier current generated in the physically disrupted region at the edge of the semiconductor die created by cleaving, sawing or otherwise separating the chip from the remainder of the wafer on which the die was fabricated. A thin metallic layer covers all or part of the edge region, thereby creating a Schottky barrier. This barrier generates a depletion region in the adjacent semiconductor material. The depletion region inherently creates an energy band distribution which preferentially accelerates minority carriers generated or near the metal-semiconductor interface towards the metal, thereby suppressing collection of these carriers by any active regions of the guard structure or by the photodiode pixels.

Abstract: A structured polarizer (linear polarizing filter) with side-by-side in a plane (lateral) regions having different polarization directions, complete extinction and complete transparency, is presented with two superpositioned planes (polarizers) with a polarizer whose surface can be structured. The polarization properties of a plane is structured in such a way and the planes are mutually oriented in such a way that polarizing regions with different polarization directions and/or polarization properties, such as contrast, polarization-direction-dependent absorption properties as a function of the wavelength, and/or non-polarizing regions, such as transparent or opaque and/or regions having a predefined absorption for specified wavelengths are obtained.

Abstract: An integrally packaged optronic integrated circuit device (310) including an integrated circuit die (322) containing at least one of a radiation emitter and radiation receiver and having top and bottom surfaces formed of electrically insulative and mechanically protective material, at least one of the surfaces (317) being transparent to radiation, and electrically insulative edge surfaces (314) having pads.

Abstract: The invention concerns a method for manufacturing and assembling individual photovoltaic silicon cells on a metal substrate, including the operations of: making a metal plate (25) provided with cut out portions (26, 29) separated from each other by points of attachment (27) and delimiting the bases of a plurality of cells; depositing a stack of silicon layers then a metallization on said plate in order to form a group of individual cells (28a-b-c-d); transferring said group onto an interconnection support (30); and perforating the points of attachment in order to separate the cells from the rest of the plate.

Abstract: An ultrasonic slitting device cuts and seals the edges of photovoltaic cells and modules to encapsulate the photoactive components in an environment substantially impervious to the atmosphere.

Abstract: A multilayer integrated substrate includes breaking grooves arranged in a grid pattern so as to section the main surface of the substrate into a plurality of blocks, and also includes fracture-preventing conductor films arranged so as to cross the breaking grooves. The fracture-preventing conductor films contain a metal component that prevents undesirable fracturing of the multilayer integrated substrate along the breaking grooves.

Abstract: A method for estimating the likely waviness of a wafer after polishing based upon an accurate measurement of the waviness of the wafer in an as-cut condition, before polishing. The method measures the thickness profile of an upper and lower wafer surface to construct a median profile of the wafer in the direction of wiresaw cutting. The median surface is then passed through an appropriate Gaussian filter, such that the warp of the resulting profile estimates whether the wafer will exhibit unacceptable waviness in a post-polished stage.

Abstract: A laser sintering system is provided for sintering a die having a serrate edge. The laser sintering system comprises a laser generator for generating a laser beam and a movable carriage for carrying said die. The laser beam sinters the serrate edge of said die into a smooth edge. A method of sintering a die, the die having a serrate edge, comprises the following steps of providing a die and using a laser beam sintering the serrate edge of said die into a smooth edge. A die has a smooth edge sintered by a laser beam.

Abstract: A method and a system for attaching semiconductor components to a substrate are provided. In the illustrative embodiment the substrate is a leadframe, and the components are semiconductor dice or packages contained on a component substrate such as a wafer. The method includes the steps of holding and dicing the component substrate using a radiation sensitive tape. The method also includes the steps of providing a component attach system having a radiation curing system, and then performing local curing of the dicing tape during a component attach step using the component attach system. The system includes the component attach system which includes a stepper mechanism for stepping the component substrate, and a component attach mechanism having an ejector pin for pushing the components one at a time from the tape and a pick and place mechanism for placing the components on the substrate.

Abstract: The present invention teaches a sawn wafer with ultra clean bonding pads on die which enhance the strength of wire bond and results in higher yield and improved reliability of packaged semiconductor die. Clean wafers ready for dicing are coated with a removable insulating water soluble non-ionic film which enhances clean saw cuts and reduces buildup. The protective film is hardened by heat and resists removal by cooling water used in dicing saws. However, after dicing the protective film is removable in a wafer washer using high pressure warm D.I. water. After removal of the protective film the electrode pads are virtually as clean as before dicing. The film may be used as a protective layer until the sawn wafer is ready for use.

Abstract: A method of aligning a plurality of empty-spaced buried patterns formed in semiconductor monocrystalline substrates is disclosed. In an exemplary embodiment, high-temperature metal marks are formed to include a conductive material having a melting temperature higher than an annealing temperature used to form such empty-spaced buried patterns. The high-temperature metal marks are formed prior to the formation of the empty-spaced buried patterns formed in a monocrystalline substrate, so that the empty-space buried patterns are aligned to the marks. Subsequent semiconductor structures that are formed as part of desired semiconductor devices can be also aligned to the marks.

Abstract: A TFT array is formed on a glass substrate (step P1) A surface protection layer is formed on the glass substrate so as to cover the TFT a-ray (step P2). The glass substrate is divided to form active matrix substrates with the surface protection layer being provided (step P3). The divided active matrix substrate is chamfered along its edges (step P4). The surface protection layer is removed from the active matrix substrate (step P5). An X-ray conductive layer is formed on the TFT array where the surface protection layer has been removed (step P6). By these steps, pollutants produced during the division and chamfering of the glass substrate are prevented from polluting the TFT array and the X-ray conductive layer, and the active element array and the semiconductor layer is prevented from deteriorating in terms of performance in manufacturing process for a two-dimensional image detector.

Abstract: A TFT array is formed on a glass substrate (step P1). A surface protection layer is formed on the glass substrate so as to cover the TFT array (step P2). The glass substrate is divided to form active matrix substrates with the surface protection layer being provided (step P3). The divided active matrix substrate is chamfered along its edges (step P4). The surface protection layer is removed from the active matrix substrate (step P5). An X-ray conductive layer is formed on the TFT array where the surface protection layer has been removed (step P6). By these steps, pollutants produced during the division and chamfering of the glass substrate are prevented from polluting the TFT array and the X-ray conductive layer, and the active element array and the semiconductor layer is prevented from deteriorating in terms of performance in manufacturing process for a two-dimensional image detector.

Abstract: A process for producing a semiconductor device comprising the steps of providing a wafer having a surface furnished with semiconductor circuits and a back; forming grooves of a depth smaller than the thickness of the wafer, said grooves extending from the wafer circuit surface; sticking a surface protective sheet onto the wafer circuit surface; grinding the back of the wafer so that the thickness of the wafer is reduced, resulting in division of the wafer into individual chips with spaces therebetween; sticking a pressure sensitive adhesive sheet onto the ground back of the wafer, pressure sensitive adhesive sheet comprising a base and, superimposed thereon, an energy radiation curable pressure sensitive adhesive layer; exposing the energy radiation curable pressure sensitive adhesive layer to an energy radiation; and peeling the surface protective sheet from the wafer circuit surface.

Abstract: A wafer cap protects micro electromechanical system (“MEMS”) structures during a dicing of a MEMS wafer to produce individual MEMS dies. A MEMS wafer is prepared having a plurality of MEMS structure sites thereon. Upon the MEMS wafer, the wafer cap is mounted to produce a laminated MEMS wafer. The wafer cap is recessed in areas corresponding to locations of the MEMS structure sites on the MEMS wafer. The capped MEMS wafer can be diced into a plurality of MEMS dies without causing damage to or contaminating the MEMS die.

Abstract: A silicon semiconductor substrate has a plurality of active regions having an impurity region and an isolating region which electrically isolates these active regions from each other. The isolating region is formed of a silicon nitride film. A contact hole penetrates an interlayer insulating film and reaches an impurity region. In this semiconductor device, when the contact hole falls across the impurity region and the isolating region, an amount of erosion in the isolating region is reduced.

Abstract: An LED array chip comprises a semiconductor substrate having a front surface and a side surface. The first surface and the front surface come together at an end of the chip to define an end portion of said semiconductor substrate that has an acute angle between the first surface and the front surface. The end of the chip defines an outermost dimension of the chip. The first surface extends further away from the front surface than the diffuison depth of the light emitting elements. A method of manufacturing an LED array chip includes the steps of: forming grooves between adjacent LED arrays of the plurality of LED arrays, each of the grooves having opposing side walls each of which makes an acute angle with the front surface; and dicing the semiconductor wafer except for the opposing side walls of each of the grooves to separate the plurality of LED arrays into individual LED array chips.

Abstract: The present invention is to provide a dicing method of cutting a workpiece along the first streets and the second streets by using a cutting blade having an annular cutting edge provided on the outer peripheral portion on one side surface of a base plate, the workpiece having plural first streets and second streets intersected each other at a predetermined angle. When the second streets are to be cut after the first streets are cut, the cutting blade is so positioned that the side of the base plate faces the side of the unworked region of the workpiece.

Abstract: An image sensor chip for use in configuring a contact-type image sensor, wherein the fabrication of a substrate on which this chip is mounted can be markedly simplified, and the pickup of noise by the analog output can be reduced. The chip is fabricated by integrating a prescribed number of photoelectric conversion elements (28) as photoreceptors, analog switches (29) connected in series to the corresponding photoelectric conversion elements (28), a switch circuit (30) for sequentially switching on the analog switches (29) in accordance with clock signals, output loads (31, 40) jointly connected in series to sets composed of the photoelectric conversion elements (28) and their respective analog switches (29), an amplification circuit (32) for amplifying the potential of the output load components on the side of the photoelectric conversion elements, and, preferably, a gain-adjusting resistor R for this operational amplifier (32).

Abstract: The invention relates to a solar cell arrangement consisting of series-connected solar subcells. Said solar subcells consist of a semiconductor wafer which forms a common base material for all of the solar subcells and wherein a number of recesses are provided for delimiting the individual, series-connected solar subcells. The invention is characterised in that at least some of the recesses extend from the top surface of the semiconductor wafer, through the wafer itself to the bottom surface and in that at most some bridge segments are left in continuation of the recesses as far as the wafer edge, to mechanically interconnect the solar subcells.

Abstract: An integrated thin-film solar battery having a plurality of unit elements connected in series includes a substrate, a plurality of spaced apart first electrode layers formed on the substrate; a plurality of semiconductor layers disposed on said plurality of first electrode layers in such a manner that each of the semiconductor layers is formed on two adjacent first electrodes and has a connection opening located on one of the two first electrodes, an electrically conductive layer formed on each of the semiconductor layers except on the region of the connection opening, and a second electrode layer disposed on each of the electrically conductive layers such that the second electrode layer is electrically connected to one of the two adjacent first electrode layers through the connection opening, to form a region interposed between the second electrode layer and the other first electrode layer as the unit element.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: A process for singulating MOEMS optical devices from a precursor structure, in which the precursor structure comprises device material, having movable optical structures, and handle material, through which optical ports are formed to provide for optical access to the movable optical structures. The process comprises coating a frontside and a backside of the precursor structure with protection material. The precursor structure is then attached to a substrate such as dicing tape and the precursor structure separated into individual optical devices by a process, including die sawing. Thereafter, the optical devices are removed from the tape and the protection material removed from the optical devices.

Abstract: In one aspect, a method is disclosed. The method comprises introducing a plurality of integrated circuits on a substrate, each integrated circuit separated from another by a scribe line area and introducing a masking material over a portion of the scribe line area. Following the introduction of the masking material, the method further includes introducing a material comprising a colorant over a portion of each of the plurality of integrated circuits and singulating the plurality of integrated circuits.

Abstract: Metal layer in a semiconductor device and method for fabricating the same, the semiconductor device having a transistor and a capacitor electrode formed on a region of a semiconductor substrate, the metal layer including a planar protection film on an entire surface of the semiconductor substrate inclusive of the transistor and the capacitor electrode, an absorber layer over the planar protection film inclusive of a region over the transistor, an insulating film on an entire surface, with a width of projection in a relievo form in a region over the absorber layer, a via hole through the planar protection film and the insulating layer, to expose a region of the capacitor electrode, a tungsten plug and a planar stuffed layer in the via hole, a mirror metal layer on the insulating film on both sides of the projection of a relievo form of the insulating film, inclusive of the planar stuffed layer, and an insulating film spacer on the projection of a relievo form of the insulating film and the mirror metal layer i

Abstract: A chip mounted enclosure (“CME”) comprises a base formed by an integrated circuit chip, a transducer element disposed on the integrated circuit chip, a side piece surrounding the transducer element that is coupled to the base, and a top piece coupled to the side piece. A method of making a CME comprises mounting a transducer element to a planar surface of an integrated circuit chip, where the planar surface forms a base of the CME. A side piece is fabricated to surround the transducer element. A top piece of the CME is placed on the side piece. Individual CMEs can be fabricated from a wafer assembly, where transducer elements, each respectively mounted to an integrated circuit wafer having corresponding integrated circuit chips, are individually surrounded by a side piece structure that is bonded to the integrated circuit wafer. Individual CMEs are formed by singulating the wafer assembly.

Abstract: A method of manufacturing an optical element including the steps of: forming a through hole in a semiconductor element which has an optical section and an electrode electrically connected to the optical section; and forming a conductive layer extending from a first surface of the semiconductor element on which the optical section is formed, through an inner wall surface of the through hole, to a second surface opposite to the first surface.

Abstract: A method for increasing integrated circuit density comprising stacking an upper wafer and a lower wafer, each of which have fabricated circuitry in specific areas on their respective face surfaces. The upper wafer is attached back-to-back with the lower wafer with a layer of adhesive applied over the back side of the lower wafer. The wafers are aligned so as to bring complimentary circuitry on each of the wafers into perpendicular alignment. The adhered wafer pair is then itself attached to an adhesive film to immobilize the wafer during dicing. The adhered wafer pair may be diced into individual die pairs or wafer portions containing more than one die pair. At least one face side of the die pair (attachment side) may have an array of minute solder balls or small pins disposed thereon for attachment and electrical communication of the die to at least one substrate such as a printed circuit board or leadframe.

Abstract: A semiconductor device includes a plurality of real chip regions and dicing lines to separate the real chip regions on a semiconductor substrate. A dicing line includes a mark section and a mark forbidden region around the mark section. A dummy wiring pattern is formed to fill the dicing line or a portion of the real chip region to surround the mark section and the mark forbidden region. A dummy wiring pattern may be a single continuous wiring pattern or the single wiring pattern may be divided into segments. Alternatively, a dummy wiring pattern may be composed of a plurality of square portions arranged in a matrix fashion.

Abstract: Edge passivation for a small area silicon cell is provided in a batch process by providing streets between individual cells formed in a silicon substrate and diffusing dopant through the substrate along the streets. Following completion of fabrication of the plurality of cells in the substrate, the substrate is sawed along the streets with the diffused region providing passivation along the edges of the individual die.

Abstract: In a method of manufacturing a semiconductor light-emitting device involving the steps of: forming a first semiconductor layer; forming a light-emitting layer of superlattice structure by laminating a barrier layer being made of InY1Ga1−Y1N (Y1≧0) and a quantum well layer being made of InY2Ga1−Y2N (Y2>Y1 and Y2>0) on the first semiconductor layer; and forming a second semiconductor layer on the light-emitting layer, an uppermost barrier layer, which will become an uppermost layer of the light-emitting layer, is made thicker than the other barrier layers. Further, at the time of forming the second semiconductor layer, an upper surface of such uppermost barrier layer is caused to disappear so that the thickness of the uppermost barrier layer becomes substantially equal to those of the other barrier layers.

Abstract: Bonding pads (3) are arranged on the outer side of an in-chip circuit region (2) of a semiconductor integrated circuit board (1), and a scribed line (4) for chip separation is formed on the outer side thereof. A corner portion (4a) of the scribed line (4) is formed to be wider than a remaining portion (4b) thereof, and a wafer test circuit (5) and test pads (6) are formed in the corner portion (4a).