Substrate Dicing Patents (Class 438/68)
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Publication number: 20090261438Abstract: A semiconductor nanowire-based photosensor includes a substrate, at least a top surface of the substrate being formed of an insulator, two electrodes spaced at a predetermined interval apart from each other on the substrate, metal catalyst layers disposed respectively on the two electrodes, and visible-range semiconductor nanowires grown from the metal catalyst layers on the two electrodes. The semiconductor nanowires grown from one of the metal catalyst layers are in contact with the semiconductor nanowires grown from the other metal catalyst layer, while the semiconductor nanowires grown respectively from the metal catalyst layers on the two electrodes are floated between the two electrodes over the substrate.Type: ApplicationFiled: April 1, 2009Publication date: October 22, 2009Inventors: Kyoung Jin CHOI, Jae Gwan PARK, Dong Wan KIM, Young Jin CHOI, Kyung Soo PARK, Jae Hwan PARK, Jae Chul PYUN
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Publication number: 20090256931Abstract: A camera module, a method of manufacturing the same, and an electronic system having the same are provided. The camera module includes an image sensor chip having an active plane and a backside, a ground wiring extending from a sidewall of the image sensor chip to the backside, a lens structure having a light detector with at least one lens stacked on the active plane, and a conductive housing extending to the ground wiring along with an outer wall of the lens structure excluding the light detector.Type: ApplicationFiled: March 12, 2009Publication date: October 15, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Chung-Sun Lee, Yong-Hwan Kwon, Un-Byoung Kang, Hyuek-Jae Lee, Woon-Seong Kwon, Hyung-Sun Jang
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Publication number: 20090253226Abstract: Example embodiments may provide a camera module including a high-resolution lens member and/or an image sensor chip that may be integrally formed, and a method of fabricating a camera module. Example embodiment camera modules may include a semiconductor package including an image sensor chip. A transparent substrate may include an upper plate portion and/or a supporting portion defined by a cavity under the upper plate portion, and the supporting portion may be attached on the semiconductor package. The upper plate portion may be spaced from the semiconductor package by the supporting portion. A lens member may be attached to the upper plate portion of the transparent substrate. A stop member may be formed on a top side of the transparent substrate and may expose a portion of the lens member.Type: ApplicationFiled: June 8, 2009Publication date: October 8, 2009Inventor: Yung-cheol Kong
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Patent number: 7598154Abstract: Size of a chipping is made small, suppressing blinding of a blade, when performing dicing of a wafer. When cutting a wafer, cutting is performed so that the portion of a V character-shaped shoulder may enter below the front surface of a wafer (depth Z2 from a substrate front surface) using the metal-bond blade which includes the abrasive particle whose fineness number is more than #3000, and whose point is V character form. By processing it in this way, cutting resistance goes up and blinding of a blade can be prevented. Hereby, the size of a chipping can be suppressed small, preventing blinding of a blade.Type: GrantFiled: December 14, 2006Date of Patent: October 6, 2009Assignee: Renesas Technology Corp.Inventor: Naoki Izumi
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Publication number: 20090242032Abstract: To provide a resource-saving photoelectric conversion device with excellent photoelectric conversion characteristics. Thin part of a single crystal semiconductor substrate, typically a single crystal silicon substrate, is detached to structure a photoelectric conversion device using a thin single crystal semiconductor layer, which is the detached thin part of the single crystal semiconductor substrate. The thin part of the single crystal semiconductor substrate is detached by a method in which a substrate is irradiated with ions accelerated by voltage, or a method in which a substrate is irradiated with a laser beam which makes multiphoton absorption occur. A so-called tandem-type photoelectric conversion device is obtained by stacking a unit cell including a non-single-crystal semiconductor layer over the detached thin part of the single crystal semiconductor substrate.Type: ApplicationFiled: March 17, 2009Publication date: October 1, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Akihisa SHIMOMURA
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Publication number: 20090238232Abstract: A method and apparatus are provided for protecting a semiconductor device from damage. The method may include the steps of providing an active semiconductor device on a surface of a semiconductor substrate where the active device is surrounded by an inactive semiconductor area, and providing a soft metallic guard element in the inactive semiconductor area around at least a portion of the periphery of the active device wherein the metallic guard element is connected to ground potential and not to the active device.Type: ApplicationFiled: June 2, 2009Publication date: September 24, 2009Applicant: EMCORE CorporationInventors: Richard Carson, Elaine Taylor, Douglas Collins
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Publication number: 20090239329Abstract: A package structure of optical devices has a chip, a sealant, a cover, a substrate, a plurality of bonding wires, and a transparent encapsulant. The chip has at least an optical device and a plurality of chip connection pads. The sealant is disposed around the optical elements. The cover is disposed on the sealant. The substrate supports the chip and has a plurality of connection pads. The bonding wires are used for electrically connecting the chip connection pads of the chip to the connection pads of the substrate. The transparent encapsulant is formed over the substrate and the cover, and encapsulates the bonding wires.Type: ApplicationFiled: May 25, 2009Publication date: September 24, 2009Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Kuo-Chung Yee
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Patent number: 7592200Abstract: There are provided a semiconductor substrate 101 on which solid-state imaging devices are formed, and a translucent member 201 provided onto a surface of the semiconductor substrate such that spaces are provided to oppose to light receiving areas of the solid-state imaging devices, wherein external connecting terminals are arranged on an opposing surface of the semiconductor substrate 101 to a solid-state imaging device forming surface, and the external connecting terminals are connected to the solid-state imaging devices via through-holes provided in the semiconductor substrate 101.Type: GrantFiled: June 24, 2005Date of Patent: September 22, 2009Assignee: Fujifilm CorporationInventors: Hiroshi Maeda, Kazuhiro Nishida, Yoshihisa Negishi, Shunichi Hosaka
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Patent number: 7592594Abstract: A method includes bonding a first side of a metal shim to a silicon shim, removing metal from the metal shim to form a plurality of cleared metal lanes in accordance with a pattern, bonding a readout integrated circuit having a plurality of saw lanes in accordance with the pattern to a second side of the metal shim to form a wafer assembly wherein the plurality of saw lanes is aligned with the plurality of cleared metal lanes, and dicing the wafer assembly.Type: GrantFiled: November 13, 2006Date of Patent: September 22, 2009Assignee: Raytheon CompanyInventors: Robert P. Ginn, Kenneth A. Gerber
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Publication number: 20090233397Abstract: For forming the separating lines, (5, 6, 7) which are produced in the functional layers (2, 3, 4) deposited on a transparent substrate (1) during manufacture of a photovoltaic module with series-connected cells (C1, C2, . . . ), there are used laser scanners (8) whose laser beam (14) produces in the field (17) scanned thereby a plurality of adjacent separating line sections (18) in the functional layer (2, 3, 4). The laser scanners (8) are then moved relative to the coated substrate (1) in the direction (Y) of the separating lines (5, 6, 7) by a distance corresponding at the most to the length (L) of the scanned field (17) to thereby form continuous separating lines (5, 6, 7) through mutually flush separating line sections (18).Type: ApplicationFiled: March 12, 2009Publication date: September 17, 2009Inventor: Walter Psyk
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Publication number: 20090224161Abstract: The invention relates to dental radiological image sensors for intraoral use. What is described is a method of fabricating an image sensor, comprising steps for the collective production of a structure combining a semiconductor wafer (12), bearing a series of image detection circuits, and a fiber-optic plate (20) fixed to one face of the wafer, the semiconductor wafer being thinned in a step subsequent to the formation of the image detection circuits on the wafer, and external access contact pads (28) are produced on that face of the wafer which is not fixed to the fiber plate, said contact pads being for controlling the circuits and for receiving image signals coming from the sensor, the fiber-optic plate having a thickness such that it provides most of the mechanical integrity of the structure once the wafer has been thinned, and to do so right to the end of the collective fabrication, the assembled structure consisting of the wafer and the plate being subsequently diced into individual chips.Type: ApplicationFiled: June 29, 2006Publication date: September 10, 2009Applicant: E2V SemiconductorsInventors: Lionel Fritsch, Pierre Cambou
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Publication number: 20090217976Abstract: A solar cell package and processes for creating a solar cell package are disclosed. The solar cell includes an electrically insulating and thermally conductive first layer, an electrically conductive second layer attached to the first layer, and a solar cell attached to the second layer. The first layer surface and a solar cell surface have substantially the same surface area.Type: ApplicationFiled: February 6, 2009Publication date: September 3, 2009Inventors: Robert Cart, John A. Herb, Kevin Richard Fine, Jesse Dennis Wolfe
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Patent number: 7582505Abstract: It is an object to provide solid-state imaging device, which can easily be manufactured and has a high reliability, and a method of manufacturing the solid-state imaging device. In the present invention, a manufacturing method comprises the steps of forming a plurality of IT-CCDs on a surface of a semiconductor substrate, bonding a translucent member to the surface of the semiconductor substrate in order to have a gap opposite to each light receiving region of the IT-CCD, and isolating a bonded member obtained at the bonding step for each of the IT-CCDs.Type: GrantFiled: April 17, 2006Date of Patent: September 1, 2009Assignee: Fujifilm CorporationInventors: Hiroshi Maeda, Kazuhiro Nishida, Yoshihisa Negishi, Shunichi Hosaka
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Publication number: 20090183766Abstract: A semiconductor device in which the damage such as cracks, chinks, or dents caused by external stress is reduced is provided. In addition, the yield of a semiconductor device having a small thickness is increased. The semiconductor device includes a light-transmitting substrate having a stepped side surface, the width of which in a portion above the step and closer to one surface is smaller than that in a portion below the step, a semiconductor element layer provided over the other surface of the light-transmitting substrate, and a stack of a first light-transmitting resin layer and a second light-transmitting resin layer, which covers the one surface and part of the side surface of the light-transmitting substrate. One of the first light-transmitting resin layer and the second light-transmitting resin layer has a chromatic color.Type: ApplicationFiled: January 16, 2009Publication date: July 23, 2009Inventors: Hidekazu TAKAHASHI, Daiki YAMADA, Yohei MONMA, Hiroki ADACHI, Shunpei YAMAZAKI
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Patent number: 7563694Abstract: A method and system for utilizing a semiconductor wafer is disclosed. The wafer comprises a plurality of semiconductor die and a plurality of scribe areas interspersed between. The method and system comprises forming bond out pads in the scribe areas such that the bond out pads are disposed on the semiconductor wafer between the plurality of semiconductor die. Additionally, the method and system comprises separating the semiconductor wafer into individual die such that when the semiconductor wafer is separated in a first manner at least one product die is provided. Furthermore, when the semiconductor wafer is separated in a second manner at least one test die is provided.Type: GrantFiled: December 1, 2006Date of Patent: July 21, 2009Assignee: Atmel CorporationInventors: Andrew Burnside, Albert Dye, Hugh Dick
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Publication number: 20090174025Abstract: An image sensor can include a first substrate, an insulating layer, a photodiode, and a via plug. A circuitry including an interconnection can be formed on the first substrate. The insulating layer is formed over the first substrate so that the insulating layer covers the interconnection. The photodiode is formed in a crystalline semiconductor layer and then bonded to the first substrate while contacting the insulating layer. The via plug is provided by removing portions of the photodiode and the insulating layer to expose an upper portion of the interconnection to form a via hole, and filling the via hole with a conductive metal. The via plug electrically connects the photodiode to the interconnection.Type: ApplicationFiled: December 12, 2008Publication date: July 9, 2009Inventor: Joon Hwang
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Patent number: 7547572Abstract: A method and apparatus are provided for protecting a semiconductor device from damage. The method includes the steps of providing a active semiconductor device on a surface of the semiconductor substrate where the active device is surrounded by inactive semiconductor areas and providing a soft metallic guard ring only in the inactive semiconductor areas around the periphery of the active device wherein the metallic guard ring is connected to ground potential and not to the active device.Type: GrantFiled: November 16, 2005Date of Patent: June 16, 2009Assignee: Emcore CorporationInventors: Richard Carson, Elaine Taylor, Douglas Collins
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Patent number: 7521338Abstract: Semiconductor wafer sawing systems and methods are described in which a wafer may be secured in a sawing position having a surface exposed to incur sawing with at least a portion of the exposed wafer surface positioned below the center of gravity of the wafer such that prevailing force of gravity may be used to assist in the removal of contaminants from the wafer.Type: GrantFiled: December 22, 2006Date of Patent: April 21, 2009Assignee: Texas Instruments IncorporatedInventors: Patricio Vergara Ancheta, Jr., Heintje Sardonas Vilaga, Ella Chan Sarmiento
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Patent number: 7504317Abstract: It is an object to provide a manufacturing method of a semiconductor device with high reliability. A plurality of first semiconductor integrated circuits, a plurality of second semiconductor integrated circuits each of which is arranged to be adjacent to one of the first semiconductor integrated circuits, a plurality of third semiconductor integrated circuits each of which is arranged to be adjacent to one of the first semiconductor integrated circuits and one of the second semiconductor integrated circuits, and a plurality of fourth semiconductor integrated circuits each of which is arranged to be adjacent to one of the first semiconductor integrated circuits, one of the second semiconductor integrated circuits, and one of the third semiconductor integrated circuits are formed over a first substrate. The first semiconductor integrated circuits are transferred to a second substrate.Type: GrantFiled: November 16, 2006Date of Patent: March 17, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tomoyuki Aoki, Tomoko Tamura, Takuya Tsurume, Koji Dairiki
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Publication number: 20090065050Abstract: A photovoltaic device and related methods of manufacture. The device has a support substrate having a support surface region. The device has a thickness of crystalline material overlying the support surface region of the support substrate. Preferably, the thickness of material has an upper surface region. The device has a glue layer provided between the support surface region and the thickness of material according to a specific embodiment. In a preferred embodiment, the device has a textured surface region formed overlying from the upper surface region of the thickness of crystalline material. Depending upon the embodiment, the device has a plurality of elevated regions having a first thickness defining a first portion of the textured surface region and a plurality of recessed regions having a second thickness defining a second portion of the textured surface region.Type: ApplicationFiled: September 4, 2008Publication date: March 12, 2009Applicant: Silicon China (HK) LimitedInventors: Nathan W. Cheung, Man Wong
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Method of fabricating leadframe based flash memory cards including singulation by straight line cuts
Patent number: 7488620Abstract: Methods for forming leadframe-based semiconductor packages having curvilinear shapes are disclosed. The leadframes may each include one or more curvilinear slots corresponding to curvilinear edges in the finished and singulated semiconductor package. After encapsulation, the integrated circuit packages on the panel may be singulated by cutting the integrated circuits from the leadframe panel into a plurality of individual integrated circuit packages. The slots in the leadframe advantageously allow each leadframe to be singulated using a saw blade making only straight cuts.Type: GrantFiled: December 29, 2005Date of Patent: February 10, 2009Assignee: SanDisk CorporationInventors: Hem Takiar, Shrikar Bhagath -
Patent number: 7485548Abstract: A system predicts die loss for a semiconductor wafer by using a method referred to as universal in-line metric (UILM). A wafer inspection tool detects defects on the wafer and identifies the defects by various defect types. The UILM method applies to various ways of classification of the defect types and takes into account the impact of each defect type on the die loss.Type: GrantFiled: March 10, 2006Date of Patent: February 3, 2009Assignee: Micron Technology, Inc.Inventors: Purnima Deshmukh, Steven J. Simmons
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Patent number: 7485576Abstract: A method of forming a conductive pattern in which the conductive pattern can be easily formed at a low temperature without a photolithography process by forming the conductive pattern using a laser ablation method and an inkjet method, an organic thin film transistor manufactured using the method, and a method of manufacturing the organic thin film transistor. The method of forming a conductive pattern in a flat panel display device includes preparing a base member, forming a groove having the same shape as the conductive pattern in the base member, and forming the conductive pattern by applying a conductive material into the groove. The base member has one of a structure including a plastic substrate having the groove and a structure including a substrate and an insulating layer which is arranged on the substrate and which has the groove.Type: GrantFiled: December 8, 2005Date of Patent: February 3, 2009Assignees: Samsung SDI Co., Ltd., Samsung SDI Germany GmbHInventors: Min-Chul Suh, Jae-Bon Koo, Taek Ahn, Hye-Dong Kim, Fischer Joerg, Werner Humbs
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Patent number: 7479399Abstract: A system and method is described for providing automated sample preparation for plan view transmission electron microscopy. A sample wafer is microcleaved from a semiconductor wafer and mounted on a first support stub. Then the sample wafer is cut with an automated diamond sawing tool to expose a cross sectional view of the sample wafer. The sample wafer is removed from the first support stub and rotated to orient the sample wafer for plan view imaging. The rotated sample wafer is then remounted on a second support stub and cut with the automated diamond sawing tool to expose a plan view surface of the rotated sample wafer. The remounted sample wafer is subsequently prepared for focused ion beam (FIB) milling and plan view transmission electron microscopy imaging.Type: GrantFiled: May 21, 2007Date of Patent: January 20, 2009Assignee: National Semiconductor CorporationInventors: Mark Alan Johnson, Larry W. Mayes
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Patent number: 7468293Abstract: In a method for the production of window elements which can be soldered into a housing in a hermetically tight manner and of a window element sealing a housing, the object of the invention is to achieve an improved hermetic sealing between window and housing through increased adherence and homogeneity in the metal coating and to prevent penetration of scattered light and unwanted radiation. Optically transparent, flat substrate material whose size is sufficient for a plurality of window elements is provided on at least one surface with an optical coating from which frame-like portions on a coated surface which enclose optically active surfaces of the window elements are subsequently removed, whereupon a metal coating that is used for producing a solder connection to the housing is applied to the generated portions having no coating, and the window elements are separated from the substrate material.Type: GrantFiled: May 25, 2006Date of Patent: December 23, 2008Assignee: Jenoptik Laser, Optik, Systeme GmbHInventors: Thomas Weyh, Elvira Gittler, Wolfgang Brode
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Patent number: 7465592Abstract: The invention provides a reliable way to fabricate a new vertical structure compound semiconductor device with improved light output and a laser lift-off processes for mass production of GaN-based compound semiconductor devices. A theme of the invention is employing direct metal support substrate deposition prior to the LLO by an electro-plating method to form an n-side top vertical structure. In addition, an ITO DBR layer is employed right next to a p-contact layer to enhance the light output by higher reflectivity. A perforated metal wafer carrier is also used for wafer bonding for easy handling and de-bonding. A new fabrication process is more reliable compared to the conventional LLO-based vertical device fabrication. Light output of the new vertical device having n-side up structure is increased 2 or 3 times higher than that of the lateral device fabricated with same GaN/InGaN epitaxial films.Type: GrantFiled: April 27, 2005Date of Patent: December 16, 2008Assignee: Verticle, Inc.Inventor: Myung Cheol Yoo
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Patent number: 7465603Abstract: A wafer level package structure of optical-electronic device and method for making the same are disclosed. The wafer level package structure of optical-electronic device is provided by employing a substrate whose surfaces have several optical sensitive areas and divided into individual package devices. The manufacture steps first involve providing a substrate with several chips whose surfaces have an optical sensitive area and bonding pads, and providing transparent layer whose surfaces have conductive circuits and scribe lines. Then the bonding pads bond to conductive circuits and a protection layer is formed on the chip to expose partly conductive circuits. Forming a conductive film on the protection layer and the conductive film contacts with the extending conductive circuits to form the wafer level package structure of optical-electronic device. At last, the transparent layer is diced according to scribe lines to form the individual package devices.Type: GrantFiled: November 13, 2007Date of Patent: December 16, 2008Assignee: Industrial Technology Research InstituteInventors: Yuan-Chang Huang, Tai-Hung Chen, Yao-Sheng Lin, Su-Tsai Lu
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Patent number: 7452743Abstract: Microelectronic imaging units and methods for manufacturing a plurality of imaging units at the wafer level are disclosed herein. In one embodiment, a method for manufacturing a plurality of imaging units includes providing an imager workpiece having a plurality of imaging dies including integrated circuits, external contacts electrically coupled to the integrated circuits, and image sensors operably coupled to the integrated circuits. The individual image sensors include at least one dark current pixel at a perimeter portion of the image sensor. The method includes depositing a cover layer onto the workpiece and over the image sensors. The method further includes patterning and selectively developing the cover layer to form discrete volumes of cover layer material over corresponding image sensors. The discrete volumes of cover layer material have sidewalls aligned with an inboard edge of the individual dark current pixels such that the dark current pixels are not covered by the discrete volumes.Type: GrantFiled: September 1, 2005Date of Patent: November 18, 2008Assignee: Aptina Imaging CorporationInventors: Steven D. Oliver, Lu Velicky, William Mark Hiatt, David R. Hembree, Mark E. Tuttle, Sidney B. Rigg, James M. Wark, Warren M. Farnworth, Kyle K. Kirby
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Patent number: 7449358Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.Type: GrantFiled: March 29, 2005Date of Patent: November 11, 2008Assignee: Texas Instruments IncorporatedInventors: Satyadev R. Patel, Andrew G. Huibers, Steve S. Chiang
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Patent number: 7439162Abstract: The present invention grinds the rear surface side of a device area to form a recessed portion and an annular reinforcement part on the outer periphery of the recessed portion, removes the annular reinforcement part by grinding or cutting the rear surface of the annular reinforcement part so as to give the wafer a uniform thickness, locates the position of streets in the front surface of the wafer by infrared imaging from the rear surface side of the wafer, and after dividing the wafer into individual devices affixes dicing tape to the rear surface of the wafer divided into devices, supports the rear surface of the wafer on a dicing frame and peels a protective member off the front surface of the wafer, thereby enabling the wafer to be supported using ordinary dicing tape while posing no obstacle to device pick-up after division of the wafer.Type: GrantFiled: November 27, 2006Date of Patent: October 21, 2008Assignee: Disco CorporationInventors: Ryuji Norimoto, Tadato Nagasawa, Takatoshi Masuda
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Publication number: 20080246066Abstract: An optic wafer for assembly with an imager wafer, the optic wafer comprising a plurality of reliefs in a surface thereof coincident with street locations separating mutually adjacent optic element locations. A wafer assembly that includes the optic wafer and an imager wafer and methods of dicing a wafer assembly are also disclosed.Type: ApplicationFiled: April 4, 2007Publication date: October 9, 2008Inventor: Rickie C. Lake
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Publication number: 20080230115Abstract: In accordance with the present invention, the dividing grooves 8 are formed so as not to be parallel to cleavage planes of the semiconductor substrate 1, and the semiconductor substrate 1 is bent along the dividing grooves 8, whereby the semiconductor substrate 1 is fractured along the dividing grooves 8.Type: ApplicationFiled: March 12, 2008Publication date: September 25, 2008Applicant: SANYO ELECTRIC CO., LTD.Inventors: Hiroyuki Kannou, Masaki Shima
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Patent number: 7413965Abstract: A method of manufacturing a thin-film circuit substrate, containing: (a) gouging a surface of a circuit substrate in a depth at least approximately equal to a thickness of a final product of the substrate, to form a section to be formed a penetrating section; (b) providing a protecting adhesive tape to adhere to the gouged surface of the substrate, before a backing surface of the substrate is ground; (c) grinding the backing surface in such a thickness that the gouged section would not penetrate; (d) dry etching entirely the backing surface, while the tape adheres to the substrate, after completion of the grinding for the backing surface; and (e) making the gouged section of the substrate to penetrate, by the dry etching, thereby forming the penetrating structure section; and, a protecting adhesive tape usable in the method.Type: GrantFiled: September 14, 2005Date of Patent: August 19, 2008Assignee: The Furukawa Electric Co., Ltd.Inventors: Shinichi Ishiwata, Masakatsu Inada
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Publication number: 20080179758Abstract: A stacked integrated circuit assembly includes a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC is disposed between the substrate and the SFIC. The stacked integrated circuit assembly includes least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.Type: ApplicationFiled: January 25, 2007Publication date: July 31, 2008Inventors: Tse E. Wong, Samuel D. Tonomura, Stephen E. Sox, Timothy E. Dearden, Clifton Quan, Polwin C. Chan, Mark S. Hauhe
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Patent number: 7405100Abstract: Packages of semiconductor devices with non-opaque covers and methods for making the packages. The invention allows an encapsulant to be used with a non-opaque cover. By ensuring the cover is attached to a die in such a way as to expose bonding pads while sealing in the imaging portion of the die, the die can be electrically connected to a substrate and then encapsulated. Since the imaging portion is sealed, the encapsulant cannot get underneath the glass. By ensuring the encapsulant is not filled beyond the glass, encapsulant cannot get over the glass either.Type: GrantFiled: December 8, 2005Date of Patent: July 29, 2008Assignee: National Semiconductor CorporationInventors: Shahram Mostafazadeh, Joseph O. Smith
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Patent number: 7404248Abstract: A producing method of producing a solid state pickup device is provided. Imaging elements are formed on a wafer in a matrix form. Each of the imaging elements has a light receiving surface and plural contact points. Receiving surface border portions are formed on a glass plate to protrude therefrom in a matrix form by etching. The receiving surface border portions are attached to the wafer to surround the light receiving surface in each of the receiving surface border portions. The light receiving surface is spaced from the glass plate. The glass plate is diced outside respectively the receiving surface border portions, to form shield glass for covering the light receiving surface. The wafer is diced for each of the imaging elements, to obtain the solid state pickup device having the shield glass and one of the imaging elements.Type: GrantFiled: January 11, 2006Date of Patent: July 29, 2008Assignee: Fujifilm CorporationInventors: Takeshi Misawa, Akihisa Yamazaki, Atsushi Misawa
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Patent number: 7405138Abstract: A semiconductor device capable mounting semiconductor elements having different functions without increasing the area of the semiconductor device, and its manufacturing method are presented. A part if wiring 104 is formed al so at the side surface of a semiconducter element 101, and bump electrodes 102 formed so as to be nearly on a same plane as the wiring 104 formed at the side surface of the semiconducter element 101, at least a part of ball electrodes 103 is formed so as to connect electrically to the wiring 104 at the side surface of the semiconductor element, the side surface of the semiconductor element is sealed with resin exposing the wiring 104, and the confronting surface of the circuit forming surface is sealed with resin.Type: GrantFiled: September 27, 2005Date of Patent: July 29, 2008Assignee: Oki Electric Industry Co., Ltd.Inventors: Shinji Ohuchi, Yasushi Shiraishi, Yasuo Tanaka
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Patent number: 7396780Abstract: A method of carrying out the laser processing of a wafer with a laser beam processing machine comprising a chuck table for holding a wafer, a laser beam application means for applying a laser beam to the wafer held on the chuck table and a processing-feed means for processing-feeding the chuck table and the laser beam application means relative to each other, comprising the steps of a wafer affixing step for putting the wafer on the surface of a protective tape mounted on an annular frame, a wafer holding step for holding the wafer put on the protective tape on the chuck table, and a laser beam application step for applying a laser beam having a predetermined wavelength from the laser beam application means to the wafer held on the chuck table and processing-feeding the wafer with the processing-feed means, wherein the protective tape is made of a material which transmits the laser beam having a predetermined wavelength applied from the laser beam application means.Type: GrantFiled: October 31, 2005Date of Patent: July 8, 2008Assignee: Disco CorporationInventors: Hitoshi Hoshino, Ryugo Oba, Kenji Furuta, Noburu Takeda, Nobuyasu Kitahara
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Publication number: 20080160661Abstract: A reusable silicon substrate device for use with layer transfer process. The device has a reusable substrate having a surface region, a cleave region, and a total thickness of material. The total thickness of material is at least N times greater than a first thickness of material to be removed. In a specific embodiment, the first thickness of material to be removed is between the surface region and the cleave region, whereupon N is an integer greater than about ten. The device also has a chuck member adapted to hold a handle substrate member in place. The chuck member is configured to hold the handle substrate in manner to facilitate bonding the handle substrate to the first thickness of material to be removed. In a preferred embodiment, the device has a mechanical pressure device operably coupled to the chuck member. The mechanical pressure device is adapted to provide a force to cause bonding of the handle substrate to the first thickness of material to be removed.Type: ApplicationFiled: April 5, 2007Publication date: July 3, 2008Applicant: Silicon Genesis CorporationInventor: Francois J. Henley
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Patent number: 7393770Abstract: A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a circuit side, a backside, and a substrate contact on the circuit side. The method also includes the steps of forming a substrate opening from the backside to the substrate contact, and then bonding the conductive interconnect to an inner surface of the substrate contact. A system for performing the method includes the semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching system for forming the substrate opening, and a bonding system for bonding the conductive interconnect to the substrate contact. The semiconductor component can be used to form module components, underfilled components, stacked components, and image sensor semiconductor components.Type: GrantFiled: May 19, 2005Date of Patent: July 1, 2008Assignee: Micron Technology, Inc.Inventors: Alan G. Wood, William M. Hiatt, David R. Hembree
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Patent number: 7390688Abstract: A semiconductor device includes a semiconductor substrate which has an integrated circuit formed on a front surface thereof, and a rough surface with a height difference of 1 to 5 ?m on a rear surface thereof. A protective film is provided on the rear surface of the semiconductor substrate.Type: GrantFiled: February 8, 2006Date of Patent: June 24, 2008Assignee: Casio Computer Co.,Ltd.Inventors: Takeshi Wakabayashi, Ichiro Mihara
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Patent number: 7387951Abstract: The invention relates to a semiconductor wafer dicing method of dicing a semiconductor wafer along parting lines into chips. The semiconductor wafer in which parting lines along which the semiconductor wafer is diced into chips are formed is held by an adhesive tape. By radially drawing the adhesive tape in a state where the chips in the semiconductor wafer are not parted from each other, the chips are parted from each other and clearances among the chips are extended.Type: GrantFiled: March 21, 2005Date of Patent: June 17, 2008Assignee: Nitto Denko CorporationInventors: Masayuki Yamamoto, Saburo Miyamoto
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Patent number: 7387260Abstract: A RF MOS- or nonlinear device-based surveillance and/or identification tag, and methods for its manufacture and use. The tag generally includes (a) an inductor, (b) a first capacitor plate coupled to the inductor, (c) a dielectric film on the first capacitor plate, (d) a semiconductor component on the dielectric film, and (e) a conductor that provides electrical communication between the semiconductor component and the inductor. The method of manufacture generally includes (1) depositing a semiconductor material (or precursor) on a dielectric film; (2) forming a semiconductor component from the semiconductor material/precursor; (3) forming a conductive structure at least partly on the semiconductor component; and (4) etching the electrically functional substrate to form (i) an inductor and/or (ii) a second capacitor plate.Type: GrantFiled: November 6, 2006Date of Patent: June 17, 2008Assignee: Kovio, Inc.Inventors: J. Devin MacKenzie, James Montague Cleeves, Vik Pavate, Christopher Gudeman, Fabio Zurcher, Max Davis, Dan Good, Joerg Rockenberger
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Publication number: 20080121784Abstract: A lens array block comprises a plurality of lens barrels joined to one another form a three-dimensional unitary structure. Each lens barrel comprises a stepped cylindrical chamber having a through hole with an internal profile having first and second steps that are spaced apart through the height of the through hole, the second step being radially inward of the first step. An image capturing unit comprising the lens block array, and methods of fabrication and assembly are also described.Type: ApplicationFiled: October 26, 2007Publication date: May 29, 2008Inventors: Chao-Chi CHANG, Yung-I Chen, Jean-Pierre Lusinchi, Raymond Chih-Chung Hsiao
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Publication number: 20080099869Abstract: The present invention provides a two-dimensional image detecting apparatus including a mold structure which apparatus can be applied to mammography, and a manufacturing method thereof. The manufacturing method includes: a conversion layer formation step of forming a conversion layer (3) on an active matrix substrate (2); a counter substrate formation step of disposing a spacer material (5) and disposing the counter substrate (6) so as to be opposite to the active matrix substrate (2) via the spacer material (5); a mold resin layer formation step of forming a mold structure layer (8) in a space surrounded by the conversion layer (3), the spacer material (5), and the counter substrate (6); and a cutting step of cutting at least the active matrix substrate (2) so that cut surfaces of the constituent members are flush with each other; and a sealing step of securing a sealing material (7) to the cut surface.Type: ApplicationFiled: October 18, 2005Publication date: May 1, 2008Inventor: Yoshihiro Izumi
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Patent number: 7354801Abstract: In the case where an integrated circuit formed of a thin film is formed over a substrate and peeled from the substrate, a fissure (also referred to as crack) is generated in the integrated circuit in some cases. The present invention is to restrain the generation of a fissure by fixing the proceeding direction of etching in one direction to make a peeled layer warp in one direction in accordance with the proceeding of etching. For example, the proceeding of etching can be controlled by utilizing the fact that a portion where a substrate is in contact with a base insulating layer is not etched in the case of patterning a peeling layer provided over the substrate, then forming the base insulating layer, and then fixing a peeled layer by the portion where the substrate is in contact with the base insulating layer.Type: GrantFiled: September 20, 2005Date of Patent: April 8, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Eiji Sugiyama, Kyosuke Ito
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Patent number: 7354790Abstract: A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw.Type: GrantFiled: May 18, 2005Date of Patent: April 8, 2008Assignee: LSI Logic CorporationInventors: Parthasarathy Rajagopalan, Zafer Kutlu, Emery O. Sugasawara, Charles E. Vonderach, Dilip P. Vijay, Yogendra Ranade, Jeff Hall, Dwight Manning
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Patent number: 7354786Abstract: A micromechanical sensor element and a method for the production of a micromechanical sensor element that is suitable, for example in a micromechanical component, for detecting a physical quantity. Provision is made for the sensor element to include a substrate, an access hole and a buried cavity, at least one of the access holes and the cavity being produced in the substrate by a trench etching and/or, in particular, an isotropic etching process. The trench etching process includes different trenching (trench etching) steps which may be divided into a first phase and a second phase. Thus, in the first phase, at least one first trenching step is carried out in which, in a predeterminable first time period, material is etched out of the substrate and a depression is produced. In that trenching step, a typical concavity is produced in the wall of the depression.Type: GrantFiled: September 8, 2005Date of Patent: April 8, 2008Assignee: Robert Bosch GmbHInventors: Hubert Benzel, Stefan Finkbeiner, Matthias Illing, Frank Schaefer, Simon Armbruster, Gerhard Lammel, Christoph Schelling, Joerg Brasas
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Patent number: 7348193Abstract: The invention is directed to a hermetically sealed device and a method for making such device. The device includes optical, micro-electromechanical, electronic and opto-electronic devices, having a substrate with one or a plurality of optical, opto-electronic, electronic or micro-electromechanical (“MEMS”) elements either singly or in combination that are located on a substrate; a covering having a top part and an extension extending a distance from the top part from the top part, an adhesive that is used to bond the extension portion of the covering to the substrate; and a sealing agent for hermetically sealing the area where the covering extension is bonded to the substrate. In the method of the invention the sealing agent is applied using atomic layer deposition techniques.Type: GrantFiled: May 2, 2006Date of Patent: March 25, 2008Assignee: Corning IncorporatedInventor: Mike Xu Ouyang
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Patent number: 7348199Abstract: A wafer processing method of dividing a wafer having function elements formed in areas sectioned by dividing lines formed on the front surface in a lattice pattern, into individual chips along the dividing lines, which comprises a deteriorated layer forming step for forming a deteriorated layer in the inside of the wafer along the dividing lines; a wafer supporting step for putting the back surface of the wafer on an extensible support tape mounted on an annular frame; and a dividing step for dividing the wafer along the dividing lines by expanding the support tape affixed to the wafer, wherein the dividing step comprises first dividing the wafer along dividing lines extending in a predetermined direction and subsequently, along dividing lines extending in a direction intersecting with the predetermined direction by expanding the support tape such that tensile force acting in a direction perpendicular to the dividing lines extending in the predetermined direction becomes larger than tensile force acting in aType: GrantFiled: June 28, 2005Date of Patent: March 25, 2008Assignee: Disco CorporationInventors: Yusuke Nagai, Masaru Nakamura