Abstract: A method for manufacturing a ball grid array package includes the steps of providing a substrate strip having a plurality of sub-substrate strips wherein each has an upper surface and a lower surface, disposing a plurality of chips on the upper surfaces of the sub-substrate strips, forming a plurality of encapsulation bodies for encapsulating the chips on the upper surfaces respectively, and forming a plurality of ribs between the encapsulation bodies.

Abstract: A method of wafer segmenting is provided. Initially, a wafer having a plurality of devices on a top surface thereof is provided. A passivation layer is formed on the top surface of the wafer to cover the devices. A bottom surface of the first bonding layer is attached to a lower surface of the wafer. In addition, a carrier wafer is provided. A second bonding layer is attached to the first bonding layer to bond the wafer to the support wafer. A segment process is performed to form a plurality of dies. Each die is maintained at the same distance between each other as the distance between the dies before the segment process. The passivation layer is removed and the devices are exposed. A wafer-level testing is performed upon the devices. The second bonding layer and the carrier wafer are removed thereafter.

Abstract: A semiconductor device comprises a semiconductor element and a support body made of a stack of ceramic layers having a recess in which electrical conductors are electrically connected with the semiconductor element, wherein at least a part of a top face of a recess side wall is covered by a resin, thereby providing a light emitting device.

Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal techniques. Trenches that define the boundaries of the individual devices are formed through the semiconductor layers and into the insulating substrate, beneficially by inductive coupled plasma reactive ion etching. A first support structure is attached to the semiconductor layers. The hard substrate is then removed, beneficially by laser lift off. A second supporting structure, preferably conductive, is substituted for the hard substrate and the first supporting structure is removed. Individual devices are then diced, beneficially by etching through the second supporting structure. A protective photo-resist layer can protect the semiconductor layers from the attachment of the first support structure.

Abstract: In a method for producing a cover for a region of a substrate, first a frame structure is produced in the region of the substrate, and then a cap structure is attached to the frame structure so that the region under the cap structure is covered. Thus, sensitive devices may be protected easily and at low cost from external influences and particularly from a casting material for casting the entire packaged device, which results when a diced chip is cast.

Abstract: Microelectronic imaging devices and associated methods for attaching transmissive elements are disclosed. A manufacturing method in accordance with one embodiment of the invention includes providing an imager workpiece having multiple image sensor dies configured to detect energy over a target frequency. The image sensor dies can include an image sensor and a corresponding lens device positioned proximate to the image sensor. The method can further include positioning standoffs adjacent to the lens devices while the image sensor dies are connected to each other via the imager workpiece. At least one transmissive element can be attached to the workpiece at least proximate to the standoffs so the lens devices are positioned between the corresponding image sensors and the at least one transmissive element. Accordingly, the at least one transmissive element can protect the image sensors while the image sensor dies are still connected.

Abstract: A solid-state imaging device includes: a planar substrate; an imaging element fixed onto the substrate; a rib provided on the substrate so as to surround the imaging element; a transparent plate fixed to a top face of the rib; a plurality of wirings for conducting electricity from inside of a package to outside of the same, the package being composed of the substrate, the rib and the transparent plate; and thin metal wires for connecting electrodes of the imaging element with the respective wirings. Each of the wirings includes: an internal electrode disposed on a surface with the imaging element mounted thereon; an external electrode disposed on a rear surface of the imaging-element mounted surface and at a position corresponding to the internal electrode and an end face electrode disposed on an end face of the substrate, for connecting the internal electrode and the external electrode.

Abstract: A method of manufacturing a micro-element package which can reduce a manufacturing cost and improve productivity by simplifying its structure and manufacturing process, and also can make contributions to miniaturization and thinness, and the micro-element package are provided. The method of the micro-element package including: providing a substrate having a micro-element on its top surface and a transparent cover having a groove on its bottom surface; attaching the transparent cover on the substrate, wherein the bottom surface of the transparent cover where the groove is formed faces the micro-element; exposing the groove by selectively eliminating the transparent cover; and dicing the substrate along the exposed groove.

Abstract: A method including forming a chemically soluble coating on a plurality exposed contacts on a surface of a circuit substrate; scribing the surface of the substrate along scribe areas; and after scribing, removing a portion of the coating. A method including forming a circuit structure comprises a plurality of exposed contacts on a surface, a location of the exposed contacts defined by a plurality of scribe streets; forming a coating comprising a chemically soluble material on the exposed contacts; scribing the surface of the substrate along the scribe streets; and after scribing, removing the coating. A method including coating a surface of a circuit substrate comprising a plurality of exposed contacts with a chemically soluble material; scribing the surface of the substrate along scribe areas; removing the coating; and sawing the substrate in the scribe areas.

Abstract: The present invention relates to a method for dividing a substrate into a number of individual chip parts, comprising the steps of: forming a number of chip parts in the substrate, comprising, for each chip part, of arranging recesses in the substrate for containing fluid; arranging one or more breaking grooves in the substrate along individual chip parts; applying mechanical force to the substrate to break the substrate along the breaking grooves. The invention also relates to a substrate as well as a chip part.

Abstract: A system and method is described for providing automated sample preparation for plan view transmission electron microscopy. A sample wafer is microcleaved from a semiconductor wafer and mounted on a first support stub. Then the sample wafer is cut with an automated diamond sawing tool to expose a cross sectional view of the sample wafer. The sample wafer is removed from the first support stub and rotated to orient the sample wafer for plan view imaging. The rotated sample wafer is then remounted on a second support stub and cut with the automated diamond sawing tool to expose a plan view surface of the rotated sample wafer. The remounted sample wafer is subsequently prepared for focused ion beam (FIB) milling and plan view transmission electron microscopy imaging.

Abstract: Semiconductor devices,-semiconductor wafers, and semiconductor modules are provided: wherein the semiconductor device has a small warp; damages at chip edge and cracks in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility. The semiconductor device 17 comprising: a semiconductor chip 64; a porous stress relaxing layer 3 provided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layer 2 provided on the stress relaxing layer and connected to the electrodes; and external terminals 10 provided on the circuit layer; wherein an organic protecting film 7 is formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chip 6, and the protecting film 7 are exposed outside on a same plane.

Abstract: A light-emitting diode with no fluctuations in optical properties and good sealing properties, and a simple production method for producing this light-emitting diode. The light-emitting diode has a base comprising a cup part on which the light-emitting diode is placed, a resin material introduced into cup part, and a lens member placed on top of a cup for focusing light emitted by a light-emitting diode chip. A layer of fluorescent material, which converts the wavelength of at least some of the light from the light-emitting diode chip, is applied to the inner convex face of the lens member. When the lens member is attached to the base, the inner convex face deforms the resin material and air and excess resin material can be pushed to the outside.

Abstract: A pre-process before cutting a wafer is described. The wafer includes a plurality of scribe lines and a plurality of dies defined by the scribe lines, and a material layer covers the wafer. A pre-processing step is performed to remove the material layer on the scribe lines close to the corner regions of the dies. Removing the material layer at the corner regions before cutting the wafer is able to preserve the integrity of the corner regions of the cut dies.

Abstract: A method for fabricating a chip-scale package includes securing a device substrate that carries at least two adjacent semiconductor devices to a sacrificial substrate. The sacrificial substrate may include conductive elements on a surface thereof, which are located so as to align along a street between each adjacent pair of semiconductor devices on the device substrate. The device substrate is then severed along each street and the newly formed peripheral edge of each semiconductor device coated with dielectric material. If the sacrificial substrate includes conductive elements, they may be exposed between adjacent semiconductor devices and subsequently serve as lower sections of contacts. Peripheral sections of contacts are formed on the peripheral edge. Upper sections of the contacts may also be formed over the active surfaces of the semiconductor devices. Once the contacts are formed, the sacrificial substrate is substantially removed from the back sides of the semiconductor devices.

Abstract: Semiconductor chip assemblies incorporating flexible, sheet-like elements having terminals thereon overlying the front or rear face of the chip to provide a compact unit. The terminals on the sheet-like element are movable with respect to the chip, so as to compensate for thermal expansion. A resilient element such as a compliant layer interposed between the chip and terminals permits independent movement of the individual terminals toward the chip driving engagement with a test probe assembly so as to permit reliable engagement despite tolerances.

Abstract: A method of stacking semiconductor chips includes providing four semiconductor chips that each include a top surface with central bond pads. Each of the bond pads is electrically coupled to second bond pads located in a peripheral portion of the semiconductor chip through a conductive layer. The first and the second semiconductor chips are arranged alongside one another on a carrier substrate. The second bond pads from the first and second semiconductor chips are bonded to corresponding landing pads on the substrate. The third semiconductor chip is then stacked over the first semiconductor chip and the fourth semiconductor chip over the second semiconductor chip. The second bond pads of the third and fourth semiconductor chips can then be bonded to contact pads of the substrate. The substrate can then be separated into a first stack that includes the first and third semiconductor chips and a second stack that includes the second and fourth semiconductor chips.

Abstract: A plurality of Group III nitride compound semiconductor layers are formed on a substrate for performing the formation of elements and the formation of electrodes. The Group III nitride compound semiconductor layers on parting lines are removed by etching or dicing due to a dicer so that only an electrode-forming layer on a side near the substrate remains or no Group III nitride compound semiconductor layer remains on the parting lines. A protective film is formed on the whole front surface. Separation grooves are formed in the front surface of the substrate by laser beam irradiation. The protective film is removed together with reaction products produced by the laser beam irradiation. The rear surface of the substrate 1s is polished to reduce the thickness of the substrate. Then, rear grooves corresponding to the latticed frame-shaped parting lines are formed in the rear surface of the substrate. The substrate is divided into individual elements along the parting lines.

Abstract: A laser beam processing method for processing a wafer by applying a laser beam to a predetermined area, comprising the steps of forming a resin film which absorbs a laser beam, on the surface to be processed of the wafer; applying a laser beam to the surface to be processed of the wafer through the resin film; and removing the resin film after the laser beam application step.

Abstract: A semiconductor substrate having an integrated circuit die area surrounded by a scribe lane is provided. Within the integrated circuit die area, a first trench isolation region and a second trench isolation region are formed on the semiconductor substrate, wherein the first trench isolation region isolates a first active device region from a second active device region, and the second trench isolation region comprises a plurality of trench dummy features for reducing loading effect. A first gate electrode is formed on the first active device region and a second gate electrode on the second active device region. The first active device region is masked, while the second active device region and the trench dummy features are exposed. An ion implantation process is then performed to implant dopant species into the second active device region.

Abstract: A first objective of the present invention is to provide a more productive method of manufacturing optical devices that minimizes processing distortion, maintains optical characteristics satisfactorily, and promotes smallness. A second objective thereof is to provide a method of manufacturing optical devices that prevents the occurrence of fine dust and maintains the optical characteristics satisfactorily. A third objective thereof is to provide a method of manufacturing optical devices of a multi-layer configuration that are obtained by applying a scribing/cutting method.

Abstract: A RF MOS- or nonlinear device-based surveillance and/or identification tag, and methods for its manufacture and use. The tag generally includes (a) an inductor, (b) a first capacitor plate coupled to the inductor, (c) a dielectric film on the first capacitor plate, (d) a semiconductor component on the dielectric film, and (e) a conductor that provides electrical communication between the semiconductor component and the inductor. The method of manufacture generally includes (1) depositing a semiconductor material (or precursor) on a dielectric film; (2) forming a semiconductor component from the semiconductor material/precursor; (3) forming a conductive structure at least partly on the semiconductor component; and (4) etching the electrically functional substrate to form (i) an inductor and/or (ii) a second capacitor plate.

Abstract: A method which can divide a semiconductor wafer sufficiently precisely along a street by use of a laser beam, while fully avoiding or suppressing contamination of circuits formed in rectangular regions on the face of the semiconductor water, and without causing chipping to the rectangular regions on the face. A laser beam is applied from beside one of the back and the face of a semiconductor substrate and focused onto the other of the back and the face of the semiconductor substrate, or the vicinity thereof, to partially deteriorate at least a zone ranging from the other of the back and the face of the semiconductor substrate to a predetermined depth.

Abstract: A method of bonding a common cover plate over a plurality of OLED devices formed on a device substrate includes providing an unpatterned or a patterned layer of a pressure-sensitive adhesive (PSA) material over a surface of the cover plate; bonding the cover plate over the OLED devices; and singulating individual OLED devices having a bonded cover plate and permitting electrical access to electrical interconnects associated with each OLED device for attaching electrical leads thereto.

Abstract: A producing method of producing a solid state pickup device is provided. Imaging elements are formed on a wafer in a matrix form. Each of the imaging elements has a light receiving surface and plural contact points. Receiving surface border portions are formed on a glass plate to protrude therefrom in a matrix form by etching. The receiving surface border portions are attached to the wafer to surround the light receiving surface in each of the receiving surface border portions. The light receiving surface is spaced from the glass plate. The glass plate is diced outside respectively the receiving surface border portions, to form shield glass for covering the light receiving surface. The wafer is diced for each of the imaging elements, to obtain the solid state pickup device having the shield glass and one of the imaging elements.

Abstract: A stacked chip package includes a substrate having an upper surface and a lower surface, a first semiconductor chip having an upper surface and a lower surface, wherein the lower surface of the first semiconductor chip is attached to the upper surface of the substrate and the upper surface of the first semiconductor chip includes a plurality of first electrode pads, and a second semiconductor chip having an upper surface and a lower surface. The lower surface of the second semiconductor chip is attached to the upper surface of the first semiconductor chip, and the lower surface of the second semiconductor chip includes trenches that correspond to the locations of the first electrode pads on the upper surface of the first semiconductor chip.

Abstract: Disclosed are a vertical GaN light emitting diode and a method for manufacturing the same. The vertical GaN light emitting diode comprises a first conductive GaN clad layer with an upper surface provided with a first contact formed thereon, an active layer formed on a lower surface of the first conductive GaN clad layer, a second conductive GaN clad layer formed on a lower surface of the active layer, a conductive adhesive layer formed on the second conductive GaN clad layer, and a conductive substrate, with a lower surface provided with a second contact formed thereon, formed on a lower surface of the conductive adhesive layer. The method for manufacturing the vertical GaN light emitting diodes comprises the step of removing the sapphire substrate from the light emitting structure so as to prevent the damages on a GaN single crystal plane of the structure.

Abstract: Structures and methods for semiconductor integrated circuits with respect to heat dissipation are provided. The structure comprises a die having a first surface and a second surface. The first surface has an opening in it, and the second surface has a contact pad formed on it. The first surface is opposite to the second surface. A conductive layer is formed over the first surface, covering a surface of the opening.

Abstract: A component includes a chip having a first chip face and a second chip face, where the first chip face includes component structures and connector metallizations associated with the component structures. The component also includes a frame structure on the first chip face and adjacent to the component structures, and a cover over the frame structure. The cover has a first cover face and a second cover face. The first cover face is closer to the chip than the second cover face. A back metallization is on the second chip face, on sides of the frame structure, and on sides of the cover. A contact is on the second cover face. There is a connection through the cover, which electrically connects the component structures and the contact. The connection is metallized and sealed.

Abstract: A method is provided for forming microelectronic devices. This may include providing a wafer device having metallization layers, a plurality of integrated circuits and a channel area provided around each of the integrated circuits. Materials from within each channel area may be removed by etching or by laser to form an air gap around a perimeter of each integrated circuit. Each air gap may prevent cracking and/or delamination problems caused by a subsequent dicing of the wafer device by a wafer saw into a plurality of devices.

Abstract: In a light emitting package fabrication process, a plurality of light emitting chips (10) are attached on a sub-mount wafer (14). The attached light emitting chips (10) are encapsulated. Fracture-initiating trenches (30, 32) are laser cut into the sub-mount wafer (14) between the attached light emitting chips (10) using a laser. The sub-mount wafer (14) is fractured along the fracture initiating trenches (30, 32).

Abstract: An array of grooves (23) is formed in a first side (12) of a wafer (10) during a wafer processing method. A back grinding tape (16) is adhered to the first side. An amount of material is removed from the second side (20) of the wafer. An adhesive layer (30) is applied to the second side. Dicing tape (24) is applied to the adhesive layer to create a first wafer assembly (32). The first wafer assembly is supported on a support surface (34) with the dicing tape facing the support surface and the back grinding tape exposed. The back grinding tape is removed and the adhesive layer is severed through the array of grooves to create individually removable die (28).

Abstract: The present invention provides a method for fabricating semiconductor circuit modules having the following steps: application of a patterned connection layer to a transfer substrate, application of active circuit devices and/or passive circuit devices with contact areas pointing toward the patterned connection layer, connection of the circuit devices to one another by means of a filler at least between the circuit devices, removal of the transfer substrate, and application of electrical connection devices for selective contact connection of the contact area of the circuit devices to one another.

Abstract: It is an object to provide solid-state imaging device, which can easily be manufactured and has a high reliability, and a method of manufacturing the solid-state imaging device. In the present invention, a manufacturing method comprises the steps of forming a plurality of IT-CCDs on a surface of a semiconductor substrate, bonding a translucent member to the surface of the semiconductor substrate in order to have a gap opposite to each light receiving region of the IT-CCD, and isolating a bonded member obtained at the bonding step for each of the IT-CCDs.

Abstract: A method for dicing semiconductor chips and a corresponding semiconductor chip system are described. The met-hod includes the steps: provision of a substrate having an upper substrate level, a middle substrate level and a lower substrate level; a plurality of empty spaces or porous areas being provided in the middle substrate level, the empty spaces or porous areas being enclosed by a substrate frame area; the empty spaces or porous areas being situated under a particular semiconductor chip area which is delimited by a semiconductor chip peripheral area in such a way that a particular substrate frame area is distanced from a vertical extension of the particular corresponding semiconductor peripheral area by a lateral intermediate space. In the case of the empty spaces, at least one substrate support element is provided to bond the lower substrate level to a particular semiconductor chip area in the upper substrate level.

Abstract: An architecture and manufacturing method for photosensitive chips, such as used in office equipment and digital cameras, involves creating grooves between chip areas in a wafer, and then placing a light-transmissive planar layer over the main surface of the wafer. The planar layer, which may be acrylic-based, creates a substantially planar surface over both the photosites in the chip areas and the grooves. The planar layer in turn supports one or more light-transmissive filtering layers. The arrangement avoids damage to the filtering layers when the wafer is diced along the grooves.

Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.

Abstract: A semiconductor device, which is obtained by sticking an adhesive sheet 1 comprising a base material 2, an adhesive agent layer 3 formed on the base material 2 and conductor bodies 4 buried in the adhesive agent layer 3 to a semiconductor wafer, and removing the base material from the adhesive agent layer of the adhesive sheet 1. The adhesive agent layer 3 and a substrate are then aligned and the semiconductor wafer and the substrate are adhered via the adhesive agent layer 3 to avoid defects caused by fluidity of an under filling material.

Abstract: A semiconductor chip has a substrate that is in the form of a parallelepiped whose side surfaces are shaped as tilted parallelograms. Such a semiconductor chip has a high output efficiency and a homogeneous thermal load due to having at least two side surfaces that are provided with an acute angle and are in the form of parallelograms.

Abstract: A method of manufacturing a semiconductor integrated circuit includes providing a fabricated integrated circuit on a wafer. A test fixture is connected to unencapsulated pads on the integrated circuit to monitor an operating parameter for the circuit and to determine a unique identifier for the die. The parameter is analyzed in post processing.

Abstract: A first semiconductor laminated structure including a first active layer for oscillating a first laser beam having a first wavelength band is provided on a front-side region of a substrate. A second semiconductor laminated structure including a second active layer for oscillating a second laser beam having a second wavelength band is provided on a rear-side region of the substrate. An emission direction of the first laser beam and an emission direction of the second laser beam are same.

Abstract: Two types of solar cell modules having an equal output voltage and different sizes are used, and a plurality of solar cell modules of these two types are installed so that they are connected in parallel. The size of a solar cell module having two solar cell sub-modules is two times larger than the size of a solar cell module including one solar cell sub-module. By connecting two power generating regions of each of the solar cell sub-modules of the former solar cell module in parallel, connecting adjacent two solar cell sub-modules in series and connecting two power generating regions of the solar cell sub-module of the latter solar cell module in series, an equal output voltage is obtained from both of the solar cell modules.

Abstract: A method of making semiconductor device packages includes the steps of attaching a wafer to a dielectric layer, testing semiconductor devices in the wafer, and then dicing the layered assembly. The dielectric layer may be, for example, a flexible tape. The semiconductor devices may be chips containing integrated circuits or memory devices. The dicing operation may be performed by a circular saw or by another suitable apparatus. The chips may be connected to input/output devices, such as ball grid arrays, on the dielectric layer, before the testing and dicing steps. Full wafer testing may be-conducted through the ball grid arrays. A relatively stiff metal sheet may be included in the layered assembly before the testing and dicing steps. The metal material may be used as heat spreaders and/or as electrical ground planes. The chips may be connected to the ball grid arrays by wire bonds or flip chip bumps and vias through the dielectric layer.

Abstract: A lead frame has an array of mounting portions connected by joint bars, and each of the mounting portions has an island serving as an external connection terminal and a plurality of lead terminals extending from the island and serving as external connection terminals for a semiconductor chip to be mounted on an adjacent island along the array. An electrically conductive paste is applied to the island, and a semiconductor chip is mounted on the island. Then, the semiconductor chip is electrically connected to the lead terminals by wires. A resin layer is deposited over the semiconductor chip, a principal surface of the island, and principle surfaces the lead terminals, while leaving opposite surfaces of the island and the lead terminals exposed. A region surrounding the island and the lead terminals electrically connected to the island is cut off into a package.

Abstract: In a method to singulate a semiconductor wafer (100) into chips, trench streets (107) of predetermined depth (105a) are formed across the first, active wafer surface (102) to define the outline of the chips (101). Thereafter, the fabrication of the active first wafer surface is completed and protected. Then, the wafer is flipped to expose the second wafer surface (103), and the wafer is subjected to a cutting saw. The saw is aligned with the trenches in the first surface so that the saw cuts the second surface along streets (106), which extend the trenches through the wafer. The saw is stopped cutting at a depth (105b), when the saw streets just coalesce with the trench streets, respectively, whereby the chips are completely singulated.

Abstract: The ceramic sensor body, held inside a housing by a sealing packing, is provided with a circumferential coating of an electrically insulating material in the region of the sealing packing, so that the sensor body remains potential-free with respect to the housing, even when a sealing packing is used that is made of a material having poor electrical insulating qualities. In this manner, a glass putty is used for the sealing packing, which, while having comparatively poor insulating characteristics, provides a good sealing effect at high loading capacity.

Abstract: A plurality of micromirror chips are collectively made from a common substrate. Each of the micromirror chips is formed with a micromirror unit including a frame, a mirror-forming portion separate from the frame via spaces, and torsion bars connecting the mirror-forming portion to the frame. The common substrate is subjected to etching to provide the spaces and make division grooves for dividing the common substrate into the individual micromirror chips. The etching for the spaces and the etching for the division grooves are performed in parallel with each other.

Abstract: A die thinning method includes providing a wafer (10) and depositing a substrate bonding material on the wafer. The die thinning method places a plurality of die (12) on the wafer (10), cures the substrate bonding material to secure the individual ICs to the base wafer (10), and covers the substrate (10) and the die (12) with a mask material. The substrate bonding material is BCB. The mask material is a photoresist (14). The method further back grinds the wafer to remove the wafer and to reduce the original die thickness from 26 mils to 5 mils. A UV transfer tape (22) is applied to the die (12) on a film frame (20). The mask material and back grinding tape (18) are then removed. The plurality of die (12), UV transfer tape (22), and film frame (20) are placed face down in a UV cure station. The UV transfer tape (22) is UV irradiated and the plurality of die (12) are removed from the UV transfer tape (22).

Abstract: A photovoltaic cell comprising a supporting substrate, a front contact layer on the substrate, a layer or layers of semiconductor material and a back contact layer comprising a metal, the back contact having areas without metal thereby permitting the passage of light through the cell.

Abstract: A semiconductor device is disclosed which includes a semiconductor chip having a plurality of electrode pads on its upper surface; terminals such as copper posts formed on the upper surface of the semiconductor chip, and electrically connected to each of the electrode pads; a resin deposited on the upper surface of the semiconductor chip, encapsulating the terminals but exposing at least some of them to a predetermined height; and electroconductor members such as solder balls connected to the terminals. There is also disclosed a method of fabricating such a semiconductor device.