Abstract: A portion of a conductive layer (310, 910) provides a capacitor electrode (310.0, 910.0). Dielectric trenches (410, 414, 510) are formed in the conductive layer to insulate the capacitor electrode from those portions of the conductive layer which are used for conductive paths passing through the electrode but insulated from the electrode. Capacitor dielectric (320) can be formed by anodizing tantalum while a nickel layer (314) protects an underlying copper (310) from the anodizing solution. This protection allows the tantalum layer to be made thin to obtain large capacitance. Chemical mechanical polishing of a layer (610) is made faster, and hence possibly less expensive, by first patterning the layer photolithographically to form, and/or increase in height, upward protrusions of this layer.

Abstract: A method for polishing a substrate having a metal film thereon is described. The substrate has metal interconnects formed from part of the metal film. The polishing method includes performing a first polishing process of removing the metal film, after the first polishing process, performing a second polishing process of removing the barrier film, after the second polishing process, performing a third polishing process of polishing the insulating film. During the second polishing process and the third polishing process, a polishing state of the substrate is monitored with an eddy current sensor, and the third polishing process is terminated when an output signal of the eddy current sensor reaches a predetermined threshold.

Abstract: Affords a III-V compound semiconductor substrate manufacturing method that enables enhancement of the substrate PL intensity. In such a III-V compound semiconductor substrate manufacturing method, first, the surface 3a of a wafer 3 is polished (polishing step). Second, the surface 3a of the wafer 3 is cleaned (first cleaning step S7). Next, the surface 3a of the wafer 3 is subjected to first dry-etching, employing a halogen-containing gas, while first bias voltage is applied to a chuck 24 for carrying the wafer 3. Subsequently, the surface 3a of the wafer 3 is subjected to second dry-etching, employing the halogen-containing gas (second dry-etching step S11), while second bias power lower than the first bias power is applied to the chuck 24.

Abstract: Methods for wafer-scale fabrication of needle arrays can include mechanically modifying a wafer to produce a plurality of vertically-extending columns. The columns are etched to round and reshape the columns into substantially uniformly shaped needles. Needle arrays having needle width non-uniformity of less than about 3% and length non-uniformity of less than about 2% can be produced.

Abstract: The method comprises the step polishing the surface of a film-to-be-polished formed over a semiconductor substrate 10 with a polishing pad while a polishing slurry containing abrasive grains, and an additive of a surfactant is being supplied onto the polishing pad 104 to thereby planarize the surface of the film-to-be-polished, and the step of further polishing the surface of the film-to-be-polished with the polishing pad while the polishing slurry and water are being supplied onto the polishing pad, after the surface of the film-to-be-polished has been planarized.

Abstract: Even for the case where a CVD oxide film is interposed at a bonding interface, as a pre-processing of bonding a first wafer and a second wafer, at least the surface roughness of the CVD oxide film of the first wafer is made small after removing organic substances. Therefore, it is possible to prevent void occurrence which is caused by the organic substances existing at and the roughness of the bonding interface of the two wafers.

Abstract: A trench structure and an integrated circuit comprising sub-lithographic trench structures in a substrate. In one embodiment the trench structure is created by forming sets of trenches with a lithographic mask and filling the sets of trenches with sets of step spacer blocks comprising two alternating spacer materials which are separately removable from each other. In one embodiment, the trench structures formed are one-nth the thickness of the lithographic mask's feature size. The size of the trench structures being dependent on the thickness and number of spacer material layers used to form the set of step spacer blocks. The number of spacer material layers being n/2 and the thickness of each spacer material layer being one-nth of the lithographic mask's feature size.

Abstract: A method for fabricating a microelectronic structure provides for forming a backfilling material layer at least laterally adjacent, and preferably laterally adjoining, a resist layer located over a substrate. Preferably, the resist layer comprises a surface treated resist layer. Optionally, the backfilling material layer may be surface treated similarly to the surface treated resist layer. Under such circumstances: (1) surface portions of the backfilling material layer and resist layer; and (2) remaining portions of the backfilling material layer and resist layer, may be sequentially stripped using a two step etch method, such as a two step plasma etch method. Alternatively, a surface portion of the surface treated resist layer only may be stripped while using a first etch method, and the remaining portions of the resist layer and backfilling material layer may be planarized prior to being simultaneously stripped while using a second etch method.

Abstract: A Chemical Mechanical Planarization (CMP) Pad. The CMP pad may be hydrophobic due to the incorporation of metal complexing agents. The CMP pad substantially retaining planarization characteristics throughout planarization applications. Shearing, hardness, wearing, water absorption and electrical characteristics of the CMP pad remain substantially constant during CMP applications.

Abstract: A method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor including wafer having a topside semiconductor surface, a bevel semiconductor surface, and a backside semiconductor surface. A gate dielectric layer is formed on at least the topside semiconductor surface. A metal including gate electrode material including at least a first metal is deposited on the gate dielectric layer on the topside semiconductor surface and on at least a portion of the bevel semiconductor surface and at least a portion of the backside semiconductor surface. The metal including gate electrode material on the bevel semiconductor surface and the backside semiconductor surface are selectively removed to form substantially first metal free bevel and backside surfaces while protecting the metal gate electrode material on the topside semiconductor surface.

Abstract: In a method of manufacturing semiconductor chips by dicing individual semiconductor devices from a semiconductor wafer, masks formed for plasma dicing in which a semiconductor wafer is divided by conducting plasma etching are removed by mechanical grinding using a grinding head. Accordingly, by removing the masks for plasma dicing using mechanical grinding, generation of reaction products is prevented when removing the masks, so that the dicing can be conducted without causing quality deterioration due to the accumulated particles.

Abstract: A method for thinning a substrate and a method for manufacturing a circuit device which make it possible to prevent the pattern of penetrating holes of a supporting plate from being transferred to the surface of the substrate and prevent non-uniform grinding of the surface of the substrate from occurring. The supporting plate and the substrate are joined by using an adhesive layer, and a sheet is attached to the supporting plate. The surface of the supporting plate to which the sheet has been attached is mounted and fixed by attraction onto an attracting head. The surface of the semiconductor wafer on which no circuit device is formed is ground by a grinder in this state.

Abstract: A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the refractory-metal-containing layer as a continuous action to expose the interlevel dielectric. In one embodiment, the metal element can include copper, nickel, or a noble metal. In another embodiment, polishing can be performed using a selectivity agent to reduce the amount of the interlevel dielectric removed.

Abstract: A method of forming a semiconductor device. A first dielectric layer is deposited on and in direct mechanical contact with the substrate. A first hard mask is deposited on the first dielectric layer. A first and second trench is formed within the first dielectric layer and the first hard mask. The second trench is wider than the first trench. A first conformal liner is deposited over the first hard mask and within the first and second trenches, a portion of which is removed, leaving a remaining portion of the first conformal liner in direct physical contact with the substrate, the first dielectric layer, and the first hard mask, and not on the first hard mask. Copper is deposited over the first conformal liner to overfill fill the first and second trenches and is planarized to remove an excess thereof to form a planar surface of the copper.

Abstract: A peeling prevention layer for preventing an insulation film and a protection layer from peeling is formed in corner portions of a semiconductor device. The peeling prevention layer can increase its peeling prevention effect more when formed in a vacant space of the semiconductor device other than the corner portions, for example, between ball-shaped conductive terminals. In a cross section of the semiconductor device, the peeling prevention layer is formed on the insulation film on the back surface of the semiconductor substrate, and the protection layer formed of a solder resist or the like is formed covering the insulation film and the peeling prevention layer. The peeling prevention layer has a lamination structure of a barrier seed layer and a copper layer formed thereon when formed by an electrolytic plating method.

Abstract: A passivation film having a predetermined width from an outer peripheral end portion toward an inner side and extending along the outer peripheral end portion is formed on a front surface of a semiconductor substrate. An outer peripheral end surface orthogonal to the front surface and a rear surface is formed by grinding the outer peripheral end portion of the semiconductor substrate. A thickness of the semiconductor substrate is reduced to a predetermined thickness by grinding the rear surface. The ground rear surface is etched by discharging a mixed acid onto the rear surface while rotating the semiconductor substrate with the rear surface facing upward, to remove a fracture layer. Thereby, chipping or cracking of the semiconductor substrate is suppressed.

Abstract: A metal-polishing composition includes colloidal silica particles, which has a ratio of minor axis/major axis of 0.2 to 0.8 and a surface at least partially covered with aluminum atoms, comprises in an amount of 50% or more with respect to total abrasives. The metal-polishing composition preferably includes an oxidizing agent, an organic acid or the like. The colloidal silica constituting the colloidal silica particles is preferably formed by hydrolysis of alkoxysilane. The major axis of the colloidal silica particles is preferably in a range of 20 nm to 100 nm.

Abstract: Example embodiments are directed to a wafer dividing apparatus and method thereof. The wafer dividing apparatus includes a chuck unit having upper and lower chucks, a cutting wire that is provided in a space between the upper and lower chucks to cut a wafer and driven by a first driving unit, and an etchant supplying nozzle supplying etchant to a groove of the wafer, which is formed by the cutting wire.

Abstract: A polished semiconductor wafer of high flatness is produced by the following ordered steps: slicing a semiconductor wafer from a rod composed of semiconductor material, material-removal processing of at least one side of the semiconductor wafer, and polishing of at least one side of the semiconductor wafer, wherein the semiconductor wafer has, after the material-removing processing and before the polishing on at least one side to be polished, along its margin, a ring-shaped local elevation having a maximum height of at least 0.1 ?m, wherein the local elevation reaches its maximum height within a 10 mm wide ring lying at the edge of the semiconductor wafer.

Abstract: A group III nitride substrate in one embodiment has a surface layer. The surface layer contains 3 at. % to 25 at. % of carbon and 5×1010 atoms/cm2 to 200×1010 atoms/cm2 of a p-type metal element. The group III nitride substrate has a stable surface.

Abstract: A laser-marked semiconductor wafer having a good flatness in the vicinity of laser mark-printed sites is produced by a method comprising a slicing step; a planarization step; a laser mark printing step; a grinding step; an etching step; and a polishing step.

Abstract: The present invention provides a method for planarizing a metal layer, and a method for manufacturing a micro pixel array. The method for planarizing the metal layer, without limitation, may include the steps of forming a metal layer over a photoresist layer, and then planarizing the metal layer using a chemical mechanical planarization process.

Abstract: A polishing composition contains at least one water soluble polymer selected from the group consisting of polyvinylpyrrolidone and poly(N-vinylformamide), and an alkali, and preferably further contains at least one of a chelating agent and an abrasive grain. The water soluble polymer preferably has a weight average molecular weight of 6,000 to 4,000,000. The polishing composition is mainly used in polishing of the surfaces of semiconductor wafers such as silicon wafers, especially used in preliminary polishing of the surfaces of such wafers.

Abstract: In a replacement gate approach, the dielectric cap layers of the gate electrode structures are removed in a separate removal process, such as a plasma assisted etch process, in order to provide superior process conditions during the subsequent planarization of the interlayer dielectric material for exposing the sacrificial gate material. Due to the superior process conditions, the selective removal of the sacrificial gate material may be accomplished with enhanced uniformity, thereby also contributing to superior stability of transistor characteristics.

Abstract: Diamond clusters are used as a polishing material of free abrading particles, each being a combination of artificial diamond particles having primary particle diameters of 20 nm or less and impurities that are attached around these diamond particles. The density of non-diamond carbon contained in the impurities is in the range of 95% or more and 99% or less, and the density of chlorine contained in other than non-diamond carbon in the impurities is 0.5% or more and preferably 3.5% or less. The diameters of these diamond clusters are in the range of 30 nm or more and 500 nm or less, and their average diameter is in the range of 30 nm or more and 200 nm or less. Such polishing material is produced first by an explosion shock method to obtain diamond clusters and then removing the impurities such that density of non-diamond carbon contained in the impurities and density of chlorine contained in other than non-diamond carbon in the impurities become adjusted.

Abstract: An additive composition for a slurry contains a first salt of polymeric acid including a first polymeric acid having a first weight average molecular weight and a first base material, and a second salt of polymeric acid including a second polymeric acid having a second weight average molecular weight and a second base material. A slurry composition is prepared by mixing the additive composition, a polishing particle composition, and water. When implementing a chemical mechanical polishing using the slurry composition, a favorable polishing selectivity is realized.

Abstract: A wafer of integrated circuits may be bonded to a carrier wafer using a layer of bonding material. The thickness of the wafer of integrated circuits may then be reduced using a series of grinding operations. After grinding, backside processing operations may be performed to form scribe channels that separate the die from each other and to form through-wafer vias. The scribe channels may be formed by dry etching and may have rectangular shapes, circular shapes, or other shapes. A pick and place tool may have a heated head. The bonding layer material may be based on a thermoplastic or other material that can be released by application of heat by the heated head of the pick and place tool. The pick and place tool may individually debond each of the integrated circuits from the carrier wafer and may mount the debonded circuits in packages.

Abstract: The invention provides a chemical-mechanical polishing composition comprising a cationic abrasive, a cationic polymer, a carboxylic acid, and water. The invention further provides a method of chemically-mechanically polishing a substrate with the aforementioned polishing composition. The polishing composition exhibits selectivity for removal of silicon nitride over removal of silicon oxide.

Abstract: The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material.

Abstract: The present invention discloses a method of manufacturing an integrated circuit on a semiconductor substrate having a semiconductor device provided thereon, including the steps of forming a copper layer having an overburden of a desired thickness, forming a layer of inert metal on the copper layer, annealing the copper layer and removing the layer of inert metal.

Abstract: The spacing between an abrasive type surface polishing tool and the surface of the work piece that is being polished is controlled dynamically so that variations in the area of the abrasive pad in contact with the surface of the work piece compensated, thereby eliminating size variations in this contact area and the accompanying variations in material removal that produce surface height fluctuations.

Abstract: A method of planarizing a semiconductor device is provided. The semiconductor device includes a substrate, first and second components provided on the surface of the substrate, and a first material provided between and above the first and second components. The first component has a height greater than a height of the second component. The method includes performing a first polishing step on the semiconductor device to remove the first material above a top surface of the first component, to remove the first material above a top surface of the second component, and to level the top surface of the first component. The method also includes performing a second polishing step on the semiconductor device to planarize the top surfaces of the first and second components.

Abstract: Provided is a method of preparing an SOI substrate having a backside roughened which the SOI substrate has a reduced number of defects in a silicon layer at the front surface in spite of sandblasting having been applied to the backside of the SOI substrate. Specifically provided is the method comprising the steps of: etching 10 nm or more of a surface of a silicon film of an SOI substrate; sandblasting a backside of the SOI substrate with protective tape attached to the etched surface of the silicon film, the back side being the other side of the SOI substrate from the etched surface; removing the protective tape after the sandblasting; and polishing and cleaning a silicon film surface from which the protective tape has been removed.

Abstract: A method for manufacturing a memory device including a ferroelectric memory array region and a logic circuit region is provided. The method includes the steps of: forming, above a base substrate, a plurality of ferroelectric capacitors in the ferroelectric memory array region; forming a wiring layer above the base substrate in the logic circuit region; forming an interlayer dielectric layer that covers the ferroelectric capacitors and the wiring layer; etching the interlayer dielectric layer formed at least in the ferroelectric memory array region to form a concave section; polishing the interlayer dielectric layer by a CMP (chemical mechanical polishing) method; etching the interlayer dielectric layer above the ferroelectric capacitors and the wiring layer to form contact holes; and forming contact sections in the contact holes.

Abstract: A donor wafer, for example of silicon, has an irregular surface following cleaving of a lamina from the surface, for example by exfoliation following implant of hydrogen and/or helium ions to define a cleave plane. Pinholes in the lamina leave column asperities at the exfoliated surface of the donor wafer, and the beveled edge may leave an edge asperity which fails to exfoliate. To prepare the surface of the donor wafer for reuse, mechanical grinding removes the column and edge asperities, and minimal additional thickness. Following cleaning, growth and removal of an oxide layer at the surface rounds remaining peaks. The smoothed surface is well adapted to bonding to a receiver element and exfoliation of a new lamina. A variety of devices may be fabricated from the lamina, for example a photovoltaic cell.

Abstract: The present invention provides a water and a method for strengthening, homogenization and construction thereof. The concave and convex portions are processed by laser or etching, and then formed at intervals on the grinding surface of the wafer. The concave and convex portions are round or polygonal shapes. With the alternated arrangement of the concave and convex portions, a mesh structure of consistent construction is formed on the grinding surface of the wafer, making it possible to cut down greatly the interference and influence generated by the texture of grinding surface, and improve substantially the structural strength of the grinding surface for a consistent quality of wafer with better applicability and industrial benefits.

Abstract: A mold with a protruding pattern is provided that is pressed into a thin polymer film via an imprinting process. Controlled connections between nanowires and microwires and other lithographically-made elements of electronic circuitry are provided. An imprint stamp is configured to form arrays of approximately parallel nanowires which have (1) micro dimensions in the X direction, (2) nano dimensions and nano spacing in the Y direction, and three or more distinct heights in the Z direction. The stamp thus formed can be used to connect specific individual nanowires to specific microscopic regions of microscopic wires or pads. The protruding pattern in the mold creates recesses in the thin polymer film, so the polymer layer acquires the reverse of the pattern on the mold. After the mold is removed, the film is processed such that the polymer pattern can be transferred on a metal/semiconductor pattern on the substrate.

Abstract: The invention provides a method of chemically-mechanically polishing a substrate. A substrate is contacted with a polishing pad and a polishing composition comprising an abrasive consisting of (A) particles consisting of titanium dioxide having a rutile structure and (B) particles consisting of titanium dioxide having an anatase structure, wherein an x-ray diffraction pattern of the particles has a ratio of X/Y of about 0.5 or more, wherein X is an intensity of a peak in an x-ray diffraction curve representing a d-spacing of about 3.24 ?, and Y is an intensity of a peak in an x-ray diffraction curve representing a d-spacing of about 3.51 ?, and water. The polishing component is moved relative to the substrate, and at least a portion of the substrate is abraded to polish the substrate.

Abstract: A method and apparatus for performing first and second polishings on a workpiece wherein the first and second polishings are performed using different operating parameters.

Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material.

Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region.

Abstract: An aqueous solution is useful for selective removal in the presence of a low-k dielectric. The aqueous solution comprises by weight percent 0 to 25 oxidizer; 0.00002 to 5 multi-component surfactant, the multi-component surfactant having a hydrophobic tail, a nonionic hydrophilic portion and an anionic hydrophilic portion, the hydrophobic tail having 6 to 30 carbon atoms and the nonionic hydrophilic portion having 10 to 300 carbon atoms; 0 to 15 inhibitor for a nonferrous metal; 0 to 50 abrasive; 0 to 20 complexing agent for a nonferrous metal; and water.

Abstract: The aqueous slurry is useful for chemical mechanical polishing semiconductor substrates having copper interconnects. The aqueous slurry includes by weight percent, 0.01 to 25 oxidizing agent, 0.1 to 50 abrasive particles, 0.001 to 3 polyvinyl pyrrolidone, 0.01 to 10 inhibitor for decreasing static etch of the copper interconnects, 0.001 to 5 phosphorus-containing compound for increasing removal rate of the copper interconnects, 0.001 to 10 complexing agent formed during polishing and balance water; and the aqueous slurry has a pH of at least 8.

Abstract: The method of manufacturing an inkjet head, includes: an opening section forming step of forming, with respect to a SOI substrate having a first silicon layer, a second silicon layer and a first thermal oxide film between the first silicon layer and the second silicon layer, nozzle opening sections passing through the second silicon layer and the first thermal oxide film and reaching the first silicon layer; after the opening section forming step, a first silicon layer removing step of removing the first silicon layer; and after the first silicon layer removal step, a liquid-repellent film forming step of forming a liquid-repellent film on a surface of the first thermal oxide film that has been exposed in the first silicon layer removal step.

Abstract: A method for manufacturing a semiconductor device is provided, which includes feeding a coating liquid comprising a silicon-containing compound dissolved in a solvent onto a semiconductor substrate, revolving the semiconductor substrate to form a coated film containing the silicon-containing compound, feeding a rinsing liquid at least partially comprising ?-pinene onto the underside of the semiconductor substrate to perform back-rinsing and washing of the underside of the semiconductor substrate, drying the semiconductor substrate that has been back-rinsed to remove the rinsing liquid, and heat-treating the semiconductor substrate to remove the solvent from the coated film to obtain an insulating film containing the silicon-containing compound.

Abstract: The invention provides a chemical-mechanical polishing system for polishing a substrate comprising (a) a polishing component selected from an abrasive, a polishing pad, or both an abrasive and a polishing pad, (b) an aqueous carrier, and (c) the halogen adduct resulting from the reaction of (1) an oxidizing agent selected from the group consisting of iodine, bromine, and a combination thereof, and (2) a carbon acid having a pKa of about 3 to about 14, wherein the halogen adduct is present in a concentration of about 0.01 mM or more in the aqueous carrier. The invention also provides a method of polishing a substrate comprising (i) providing the aforementioned chemical-mechanical polishing system, (ii) contacting the substrate with the polishing system, and (iii) abrading at least a portion of the surface of the substrate with the polishing system to polish the substrate.

Abstract: A method and apparatus for ultra thin wafer backside processing are disclosed. The apparatus includes an outer ring holding a high temperature grinding and/or dicing tape to form a support structure. An ultra thin wafer or diced wafer is adhered to the tape within the ring for wafer backside processing. The wafer backside processing includes ion implantation, annealing, etching, sputtering and evaporation while the wafer is in the support structure. Alternative uses of the support structure are also disclosed including the fabrication of dies having metalized side walls.

Abstract: A method of manufacturing a semiconductor device by thinning a substrate by grinding, and performing ion implantation. In a diode in which a P anode layer and an anode electrode are formed at a side of a right face of an N? drift layer, and an N+ cathode layer and a cathode electrode are formed at a side of a back face of the N? drift layer, an N cathode buffer layer is formed thick compared with the N+-type cathode layer between the N?-type drift layer and the N+ cathode layer, the buffer layer being high in concentration compared with the N? drift layer, and low compared with the N+ cathode layer. When a reverse bias voltage is applied, a depletion layer is stopped in the middle of the N cathode buffer layer, and thus prevented from reaching the N+ cathode layer, so that the leakage current is suppressed.

Abstract: A method of cleaning for removing metal compounds attached to a surface of a substrate, wherein the cleaning is conducted by supplying a supercritical fluid of carbon dioxide comprising at least one of triallylamine and tris(3-aminopropyl)amine to the surface of the substrate and a process for producing a semiconductor device using the method of cleaning are provided. In accordance with the method of cleaning and the method for producing a semiconductor device using the method, etching residues or polishing residues containing metal compounds are efficiently removed selectively from the electroconductive material forming the electroconductive layer. When the electroconductive layer is a wiring, an increase in resistance due to residual metal compounds can be suppressed, and an increase in the leak current due to diffusion of the metal from the metal compounds to the insulating film can be prevented. Therefore, reliability on the wiring is improved, and the yield of the semiconductor device can be increased.

Abstract: Methods of forming electrical interconnects include the steps of forming a first electrically conductive layer on a semiconductor substrate and then forming a first electrically insulating layer on the first electrically conductive layer. A second electrically insulating layer is then formed on the first electrically insulating layer. The second electrically insulating layer is then etched to expose the first electrically insulating layer and then a third electrically insulating layer is formed on the first electrically insulating layer. The first and third electrically insulating layers are then etched to define a contact hole therein which exposes a portion of the first electrically conductive layer. A barrier metal layer is then formed. The barrier metal layer is preferably formed to extend on the third electrically insulating layer and on the exposed portion of the first electrically conductive layer.