Abstract: Methods and apparatus for etching substrates such as silicon wafers are provided. In one specific approach, a surface of the substrate assembly is covered with a resist that is patterned to define features to be etched. In this approach, the surface is then exposed to a plasma in a plasma etcher so that surface areas not covered with the resist are etched, while the thickness of the resist increases or etches at a rate that is at least ten times slower than that of the exposed areas of the surface. This etching process can be followed with a conventional plasma etch. By combining the etching that increases the resist thickness with the conventional etching of resist in which the resist thins during etching, features having high-aspect-ratios can be etched.

Abstract: A method of etching is disclosed using a photoresist etch barrier formed by an exposure with a light source of which wavelength is in the range of 157 nm to 193 nm, such as an argon fluoride(ArF) laser or fluorine laser(F2 laser), the method includes the steps of coating a photoresist layer on a etch target layer; forming photoresist pattern by developing the photoresist layer after exposing the photoresist layer with a light source of which wavelength is in the range of 157 nm to 193 nm; forming a polymer layer and etching a portion of the etch target layer simultaneously with a mixture of fluorine-based gas, an Ar gas and an O2 gas, wherein the fluorine-based gas is CxFy or CaHbFc, and wherein x, y, a, b and c range from 1 to 10, respectively; and etching the etch target layer using the polymer layer and the photoresist pattern as the etch mask.

Abstract: A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the substrate. In conjunction with the material layer deposition, the etch species selectively remove portions of the deposited material layer adjacent to high aspect ratio feature openings, filling such features in a void-free and/or seam-free manner. The material layer may be deposited on the substrate using physical vapor deposition (PVD) and/or chemical vapor deposition (CVD) techniques.

Abstract: The present invention provides a method for producing a Group III nitride compound semiconductor, which method permits only minimal reaction of the semiconductor with a hetero-substrate during epitaxial growth and induces no cracks in the Group III nitride compound semiconductor even when the semiconductor is cooled to room temperature. The method includes a buffer layer formation step for forming a gas-etchable buffer layer on the hetero-substrate, and a semiconductor formation step for epitaxially growing the Group III nitride compound semiconductor on the buffer layer through a vapor phase growth method, wherein at least a portion of the buffer layer is gas-etched during or after the semiconductor formation step.

Abstract: A capacitor structure which has a generally pyramidal or stepped profile to prevent or reduce dielectric layer breakdown is disclosed. The capacitor structure includes a first conductive layer, at least one dielectric layer having a first area provided on the first conductive layer and a second conductive layer provided on the at least one dielectric layer. The second conductive layer has a second area which is less than the first area of the at least one dielectric layer. A method of fabricating a capacitor structure is also disclosed.

Abstract: A thermal cleaning of a substrate that has been subjected to wet cleaning is carried out under a high vacuum atmosphere to remove an oxide film remaining on the substrate. Thereafter, a thermal cleaning is carried out under a hydrogen atmosphere to remove contamination such as carbon or the like. At this time, the oxide film has already been removed and therefore contamination is effectively removed by a relatively low temperature and short duration thermal cleaning. Thus, problems such as the degradation of the profile of the impurity concentration in the impurity diffusion layer which has been formed over the substrate are prevented.

Abstract: A semiconductor device including a gate stack located over a substrate and a spacer located over the substrate and adjacent the gate stack. The spacer includes a plurality of layers, wherein at least one of the plurality of layers is a batch layer and at least one of the plurality of layers is a non-batch layer.

Abstract: The invention provides an aqueous dispersion for chemical mechanical polishing that can limit scratches of a specific size to a specific number, even with interlayer insulating films with small elastic moduli (silsesquioxane, fluorine-containing SiO2, polyimide-based resins, and the like.). When using the aqueous dispersion for chemical mechanical polishing of an interlayer insulating film with an elastic modulus of no greater than 20 GPa as measured by the nanoindentation method, the number of scratches with a maximum length of 1 ?m or greater is an average of no more than 5 per unit area of 0.01 mm2 of the polishing surface. An aqueous dispersion for CMP or an aqueous dispersion for interlayer insulating film CMP according to another aspect of the invention contains a scratch inhibitor agent and an abrasive. The scratch inhibitor may be biphenol, bipyridyl, 2-vinylpyridine, salicylaldoxime, o-phenylenediamine, catechol, 7-hydroxy-5-methyl-1,3,4-triazaindolizine, and the like.

Abstract: A system for dished metal redevelopment by providing a metal deposition solution at an interface between a moving semiconductor wafer and a moving polishing pad, which deposits metal onto dished metal in trenches in a layer of an interlayer dielectric; and by polishing the wafer with a relatively reduced polishing pressure to polish metal being deposited. A polishing fluid is disclosed for use in a CMP polishing system, the polishing fluid being a metal deposition solution for dished metal redevelopment.

Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

Abstract: Self-aligned trench MOSFETs and methods for manufacturing the same are disclosed. By having a self-aligned structure, the number of MOSFETS per unit area—the cell density—is increased, making the MOSFETs cheaper to produce. The self-aligned structure for the MOSFET is provided by making the sidewall of the overlying isolation dielectric layer substantially aligned with the sidewall of the gate conductor. Such an alignment can be made through any number of methods such as using a dual dielectric process, using a selective dielectric oxidation process, using a selective dielectric deposition process, or a spin-on-glass dielectric process.

Abstract: We have developed an uncomplicated method of plasma etching deeply recessed features such as deep trenches, of at least 5 ?m in depth, in a silicon-containing substrate, in a manner which generates smooth sidewalls, having a roughness of less than about 1 ?m, typically less than about 500 nm, and even more typically between about 100 nm and 20 nm. Features having a sidewall taper angle, relative to an underlying substrate, typically ranges from about 85° to about 92° and exhibiting the smooth sidewalls are produced by the method. In one embodiment, a stabilizing etchant species is used constantly during the plasma etch process, while at least one other etchant species and at least one polymer depositing species are applied intermittently, typically periodically, relative to each other. In another embodiment, the stabilizing etchant species is used constantly and a mixture of the other etchant species and polymer depositing species is used intermittently.

Abstract: A process enables plasma etching of materials that do not contain silicon. The process is particularly suitable for the side wall passivation of chromium layers in masks for fabricating semiconductor components. The plasma contains oxygen and/or nitrogen, and at least one silicon-donating compound is introduced into the plasma. This allows efficient passivation of side walls.

Abstract: A method and apparatus are disclosed for depositing a dielectric film in a gap having an aspect ratio at least as large as 6:1. By cycling the gas chemistry of a high-density-plasma chemical-vapor-deposition system between deposition and etching conditions, the gap may be substantially 100% filled. Such filling is achieved by adjusting the flow rates of the precursor gases such that the deposition to sputtering ratio during the deposition phases is within certain predetermined limits.

Abstract: Disclosed is a method of manufacturing a semiconductor device. The method includes the steps of forming gates on a substrate, forming junction areas on a surface of the substrate, forming a first BPSG layer on a resultant structure of the substrate, performing a first CVD process for the first BPSG layer, forming a second BPSG layer on the first BPSG layer, forming a landing plug contact, depositing a polysilicon layer on a resultant structure of the substrate, and performing a second CMP process for the polysilicon layer, the second BPSG layer and the nitride hard mask. The CMP processes are carried by using acid slurry having a high polishing selectivity with respect to the nitride layer, so a step difference between the cell region and the peripheral region is removed, thereby simplifying the semiconductor manufacturing process and removing a dishing phenomenon.

Abstract: A semiconductor device manufacture method has the steps of: (a) forming a polishing stopper layer over a semiconductor substrate; (b) etching the semiconductor substrate to form a trench; (c) forming a first liner insulating layer of silicon oxide over the surface of the trench; (d) forming a second liner insulating layer of silicon nitride over the first liner insulating layer, the second liner insulating layer having a thickness of at least 20 nm or at most 8 nm; (e1) depositing a third liner insulating layer of silicon oxide over the second liner insulating layer by plasma CVD at a first bias; and (e2) depositing an isolation layer of silicon oxide by plasma CVD at a second bias higher than the first bias, the isolation layer burying a recess defined by the third liner insulating layer.

Abstract: An etching solution includes an anticorrosive for copper or a benzotriazole based anticorrosive in a hydrofluoric acid aqueous solution. An etching method makes use of the etching solution set out above. Moreover, a method for manufacturing a semiconductor device which should include the step of removing copper by the etching method. The method includes the steps of forming copper through a barrier layer made of a metal or metal compound, which is greater in ionization tendency than copper, so as to bury a wiring groove formed in an insulating film with the copper, followed by polishing additional copper and barrier layer formed on the insulating film, and etching a surface layer of the insulating film by use of the etching solution to remove an insulating defective layer made mainly of the barrier layer on the insulating film along with the surface layer of the insulating film.

Abstract: A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity.

Abstract: A manufacturing method of a semiconductor substrate provided with a through hole electrode is proposed. In accordance with the methods, it is possible to effectively form a through hole electrode in a semiconductor substrate in which a device and a wiring pattern have been already fabricated. This manufacturing method includes the steps of forming a first silicon oxide film 12 on a principal surface of the semiconductor substrate 11, forming a small hole 13 through the semiconductor substrate 11 from the opposite the step to reach to the first silicon oxide film 12, covering the inside of the small hole 13 with the second silicon oxide film 14, forming a first thin metal film 15 and a second thin metal film 16 on the first silicon oxide film 12, partially removing the first silicon oxide film 12 corresponding to the end of the small hole 13, and filling the small hole 13 with the conductive material to form a through hole electrode 17.

Abstract: A method for controlling a removal of photoresist material from a semiconductor substrate is provided. The method includes providing the semiconductor substrate having a photoresist mask formed thereon. The method also includes forming a conformal layer of polymer over the photoresist mask and a portion of the semiconductor substrate not covered by the photoresist mask while concurrently removing a portion of the conformal layer of polymer. The thickness of the conformal layer of polymer on each region of the semiconductor substrate is set to vary depending on a removal rate of the conformal layer of polymer in each region of the semiconductor substrate.

Abstract: An Iridium barrier layer is between a contact plug and a bottom electrode of a capacitor. Etching is performed to pattern the bottom electrode and barrier layer using a fluorine-based recipe resulting in the formation of a first fence clinging to the sidewalls. Next the remaining barrier layer is etched using a CO-based recipe. A second fence is formed clinging to and structurally supported by the first fence. At the same time, the CO-based recipe etches away a substantial portion of the first fence to remove the structural support provided to the second fence. The second fence is therefore lifted-off from the sidewalls leaving the sidewalls substantially free of clinging fences. The etched barrier layer has a sidewall transition. The sidewalls have a relatively low taper angle above the sidewall transition and a relatively steep taper angle below the sidewall transition.

Abstract: A method for integrated processing of a high Voltage MOSFET device and a split gate MOSFET device whereby a novel method is provided to form the split gate device and the high voltage MOSFET device in parallel processing steps including an oxide formation step whereby an oxide spacer layer in a split gate device is formed using about the same overall thermal budget while forming in parallel a thick gate oxide for a an embedded high voltage MOSFET device.

Abstract: A new method is provided that allows for the application of electropolish for removal of copper and that is independent of pattern density of the removed copper. Electropolish of the copper is first accomplished by reversing current in the H2SO4 or H3PO4 solution. After identifying the endpoint of the electropolish, chemical etching of the copper in a H2SO4 or H3PO4 solution is continued, in this manner avoiding effects of high current density introduced by pattern density.

Abstract: Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.

Abstract: In a semiconductor device including a plurality of element regions and an element isolation region based on STI (shallow trench isolation) which electrically isolates the element regions from each other, each of the element regions includes; a channel region; source/drain regions formed to sandwich the channel region in a horizontal direction; a gate insulation film which is formed on the channel region and in which an angle of a bird's beak is 1 degree or smaller, the bird's beak being formed from a side of the element isolation region on a surface opposite a surface facing the channel region in a horizontal direction substantially perpendicular to the direction in which the source/drain region sandwich the channel region; and a gate electrode layer formed on the gate insulation film.

Abstract: An improved method for determining endpoint of a time division multiplexed process by monitoring an identified region of a spectral emission of the process at a characteristic process frequency. The region is identified based upon the expected emission spectra of materials used during the time division multiplexed process. The characteristic process frequency is determined based upon the duration of the steps in the time division multiplexed process. Changes in the magnitude of the monitored spectra indicate the endpoint of processes in the time division multiplexed process and transitions between layers of materials.

Abstract: A method of fabricating substrates, e.g., bulk wafers, silicon on insulator wafers, silicon on saphire, optoelectronic substrates. The method includes providing a substrate (e.g., silicon, gallium arsenide, gallium nitride, quartz). The substrate has a film characterized by a non-uniform surface, which includes a plurality of defects. At least some of the defects are of a size ranging from about 100 Angstroms and greater. The method also includes applying a combination of a deposition species for deposition of a deposition material and an etching species for etching etchable material. The combination of the deposition species and the etching species contact the non-uniform surface in a thermal setting to reduce a level of non-uniformity of the non-uniform surface by filling a portion of the defects to smooth the film of material. The smoothed film of material is substantially free from the defects and is characterized by a surface roughness of a predetermined value.

Abstract: A method for forming a multilayer interconnect includes: a first step of forming a lower layer interconnect in an upper portion of a first insulating film and then forming a second insulating film and a third insulating film in this order on the first insulating film including the lower layer interconnect; a second step of forming an aperture in part of the third insulating film located above the lower layer interconnect; a third step of forming an interconnect groove in an upper portion of the third insulating film so that an upper portion of the aperture is part of the interconnect groove while reducing the thickness of part of the second insulating film located under the aperture without having the lower layer interconnect exposed; a fourth step of removing part of the second insulating film located under the aperture to expose the lower layer interconnect; and a fifth step of filling a conductive film in the aperture and the interconnect groove and thereby forming an upper layer interconnect and a connect

Abstract: Nanotip arrays are formed by exposing a substrate to a process gas mixture that simultaneously forms nanomasks on the substrate surface and etches exposed portions of the substrate surface to form the nanotip array. Components of the process gas mixture form nanocrystallites on the surface of the substrate, thereby masking portions of the substrate from other components of the process gas mixture, which etch exposed portions of the substrate. Accordingly, nanotip arrays formed using this technique can have nanocrytallite endpoints.

Abstract: The integrated optical circuit of the present invention includes a substrate with a first cladding layer. A first core layer having one or more waveguiding elements is formed on the first cladding layer. A second cladding layer surrounds the waveguiding elements of the first core layer; the refractive index of the first and second cladding layers are selected to be less than the refractive index of the waveguiding element(s). Through simultaneous cladding material deposition and cladding material removal, the second cladding layer as deposited is substantially self-planarized, enabling further layers to be positioned on the second cladding layer without necessitating intermediate planarization. Further, the present invention permits planar waveguide cores having submicron core spacings to be covered by a subsequently-deposited cladding layer without cladding gaps, seams or other deleterious cladding defects.

Abstract: A chemical mechanical polishing (CMP) apparatus and method for sequentially polishing multiple semiconductor wafers on a single polishing pad utilizes multiple slurry delivery lines to supply one or more types of polishing solutions to the surface of the polishing pad. The slurry delivery lines are positioned to direct the polishing solution or solutions to different polishing positions of the polishing pad. The use of multiple slurry delivery lines allows the CMP apparatus to polish the semiconductor wafers at different polishing positions of the polishing pad using different types of polishing solutions.

Abstract: Method of etching a ferroelectric layer includes etching an upper electrode and partially through a ferroelectric layer. A dielectric material is subsequently deposited upon the upper electrode and the partially etched ferroelectric layer. A second etch step completely etches through the remaining portion of the ferroelectric layer and also etches lower electrodes. A random access memory apparatus is constructed that includes a first conductive layer, a dielectric layer disposed upon the first conductive layer, a second conductive layer disposed upon the dielectric layer, where such layers form a stack having a sidewall. Further, the sidewall has a protective dielectric film disposed thereon and extending from the second layer down to the dielectric layer.

Abstract: A method for forming a photoresist pattern with minimally reduced transformations through the use of ArF photolithography, including the steps of: forming an organic anti-reflective coating layer on a an etch-target layer already formed on a substrate; coating a photoresist for ArF on the organic anti-reflective coating layer; exposing the photoresist with ArF laser; forming a first photoresist pattern by developing the photoresist, wherein portions of the organic anti-reflective coating layer are revealed; etching the organic anti-reflective coating layer with the first photoresist pattern as an etch mask and forming a second photoresist pattern by attaching polymer to the first photoresist pattern, wherein the polymer is generated during etching the organic anti-reflection coating layer with an etchant including O2 plasma; and etching the etch-target layer by using the second photoresist pattern as an etch mask.

Abstract: A copper-containing layer suitable for an electrical interconnect in a device such as an integrated circuit is created by a procedure in which a trench (104) is formed through a dielectric layer (102) down to a substrate (100). A diffusion barrier (106) is provided over the dielectric layer and into the trench. Copper (108) is deposited over the diffusion barrier and into the trench. Chemical mechanical polishing is utilized to remove the copper outside the trench down substantially to the diffusion-barrier material overlying the dielectric layer. A sputter etch, typically of the reactive type, is then performed to substantially remove the diffusion-barrier material overlying the dielectric layer. The sputter etch typically removes copper above and/or in the trench at approximately the same rate as the diffusion-barrier material so as to substantially avoid the undesirable dishing phenomenon.

Abstract: A three-step polymer removal process that reverses the conventional sequence in which polymer is removed. In the preferred embodiment of the present invention the polymer is first removed from the Gas Deposition Table, after this the polymer is stripped from the inner surface of the created contact hole.

Abstract: A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 ? can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH2Cl2) as the main reactive agent.

Abstract: Optical gratings are fabricated on a scale that may be smaller than the resolution of the lithographic system used to generate the grating pattern. Parallel ridges are formed using lithographic techniques. A conformal deposition and anisotropic etch are then used to form sidewalls on the sides of the ridges. After removing the ridges, the remaining sidewalls are used as a mask to etch the substrate. Removing the sidewalls leaves the desired grating pattern, with a pitch spacing of one-half that of the original ridges.

Abstract: A polishing method of the present invention is a polishing method for planarizing a film to be polished that is deposited on a wafer, and includes a step (a) of establishing a polishing rate distribution of the film to be polished that is deposited on the wafer and a target film thickness distribution after polishing of the film to be polished, a step (b) of measuring a film thickness distribution before polishing of the film to be polished, a step (c) of calculating a predicted film thickness distribution after polishing of the film to be polished from the film thickness distribution before polishing and the polishing rate distribution, a step (d) of calculating a pressure against a polishing pad for each of a plurality of regions of the film to be polished and a polishing time from the predicted film thickness distribution and the target film thickness distribution, and a step (e) of polishing while applying the pressure against the film to be polished during the polishing time.

Abstract: A method for preventing electrical short circuits in a multi-layer magnetic film stack comprises providing a film stack that includes a layer of magnetic material having an exposed surface. A protective layer is deposited on the exposed surface of the magnetic layer. The protective layer may comprise, for example, a fluorocarbon or a hydrofluorocarbon. The film stack is etched and the protective layer protects the exposed surface from a conductive residue produced while etching the film stack. The method may be used in film stacks to form a magneto-resistive random access memory (MRAM) device.

Abstract: A three-step polymer removal process that reverses the conventional sequence in which polymer is removed. In the preferred embodiment of the present invention the polymer is first removed from the Gas Deposition Table, after this the polymer is stripped from the inner surface of the created contact hole.

Abstract: In one aspect, the invention encompasses a semiconductor processing method of forming a material over an uneven surface topology. A substrate having an uneven surface topology is provided. The uneven surface topology comprises a valley between a pair of outwardly projecting features. A layer of material is formed over the uneven surface topology. The layer comprises outwardly projecting portions over the outwardly projecting features of the surface topology and has a gap over the valley. The layer is etched, and the etching forms protective material within the gap while removing an outermost surface of the layer. The etching substantially does not remove the material from the bottom of the gap. In another aspect, the invention encompasses a semiconductor processing method of forming a material over metal-comprising lines. A first insulative material substrate is provided. A pair of spaced metal-comprising lines are formed over the substrate.

Abstract: A dual depth trench isolation structure formed between active devices and conductive well regions of same conductivity type which comprises a first inter-well isolation structure having a first isolation trench depth, a second inter-well isolation structure having a second isolation trench depth which combine to form a dual depth trench containing the dual depth trench isolation structure comprising the first inter-well isolation structure and the second inter-well isolation structure, with the dual depth trench isolation interposed at the boundary of an n-well conductive region and a p-well conductive region, a first intra-well isolation structure having a first isolation trench depth, the first intra-well isolation structure interposed between a pair of p-channel transistors residing in the n-well region, and a second intra-well isolation structure having a second isolation trench depth, the second intra-well isolation structure interposed between a pair of n-channel transistors residing in the p-well regio

Abstract: A continuous in situ process of deposition, etching, and deposition is provided for forming a film on a substrate using a plasma process. The etch-back may be performed without separate plasma activation of the etchant gas. The sequence of deposition, etching, and deposition permits features with high aspect ratios to be filled, while the continuity of the process results in improved uniformity.

Abstract: A method for fabricating a semiconductor device and forming an insulating film used therein, includes forming an isolation insulating film on a semiconductor wafer and forming gates, separated by gaps having a predetermined distance, on an active region. Next, a first interlayer dielectric film is deposited to a predetermined thickness on the semiconductor wafer having the gates, so that the gaps between the gates are not completely filled. Then, a sputtering etch is performed entirely on a surface of the first interlayer dielectric film. Thereafter, the first interlayer dielectric film is partially removed through isotropic etching. Next, a second interlayer dielectric film is deposited on the first interlayer dielectric film so that the gaps between the gates are completely filled.

Abstract: A three-step polymer removal process that reverses the conventional sequence in which polymer is removed. In the preferred embodiment of the present invention the polymer is first removed from the Gas Deposition Table, after this the polymer is stripped from the inner surface of the created contact hole.

Abstract: A polishing method able to easily flatten unevenness formed on the surface of a film to be polished and able to efficiently polish the film flat while suppressing damage to an interlayer insulating film below the film, comprising, when polishing an object having a film such as an interconnection layer formed burying interconnection grooves formed in an insulating film of a substrate, supplying a polishing solution over the surface to be polished at least substantially parallel to the surface to preferentially remove by polishing the projecting portions of the film and flatten the surface by the shear stress of the processing solution or arranging a cathode member facing the surface and supplying an electrolytic solution containing a chelating agent between the surface and cathode member while supplying voltage between the film and the cathode member to preferentially remove by polishing the projecting portions of the film and flatten the surface by the shear stress of the electrolytic solution, and a polishin

Abstract: A method for fabricating a gate structure having a polysilicon electrode using an oxygen-free chemistry to etch the polysilicon. In one embodiment, the chemistry further includes nitrogen.

Abstract: A method for removing photoresist is described. A substrate having a photoresist to be removed thereon is provided, and then an ashing process is performed to remove most of the photoresist. The substrate is irradiated with UV light, and the remaining photoresist and polymer are stripped with stripping solvents after UV irradiation.

Abstract: A method of making a semiconductor structure includes determining a polish time which is sufficient to planarize a layer on a semiconductor substrate. The layer is polished for the polish time to planarize the layer, and then the layer is polished to a predetermined thickness. The semiconductor structures can be used to make a semiconductor device.

Abstract: A process of using a-C:H layer as a hardmask material with tunable etch resistivity in a RIE process that alleviates the addition of a layer forming gas to the etchant when making a semiconductor device, comprising: a) providing a semiconductor substrate; b) forming a hardmask of amorphous carbon-hydrogen (a-C:H) layer by plasma enhancement over the semiconductor substrate; c) forming an opening in the hardmask layer to form an exposed surface portion of the hardmask layer; and d) etching the exposed surface portion of the hardmask layer without the addition of a layer forming gas using RIE to form a trench feature with sufficient masking and side wall protection.