Abstract: The present invention provides a method and an apparatus for etching a photolithographic substrate. The photolithographic substrate is placed on a support member in a vacuum chamber. A processing gas for etching a material from the photolithographic substrate is introduced into the vacuum chamber, and a plasma is generated. An RF bias is supplied to the support member in the vacuum chamber through an RF bias frequency generator at or below the ion transit frequency. Exposed material is etched from the photolithographic substrate with improved CD Etch Linearity and CD Etch Bias since the low frequency bias allows the developed charge on the photolithographic substrate, generated by the plasma, to dissipate.

Abstract: A plasma etch method for forming a patterned target layer within a microelectrcnic product forms an etch residue layer adjoining a patterned mask layer formed upon a blanket target layer. After removing the patterned mask layer, the etch residue layer is laterally increased to form a laterally increased etch residue layer. The laterally increased etch residue layer is employed as an etch mask for forming the patterned target layer from the blanket target layer. The method is particularly useful for forming gate electrodes within semiconductor products.

Abstract: A method for treating a semiconductor processing component, including: exposing the component to a halogen gas at an elevated temperature, oxidizing the component to form an oxide layer, and removing the oxide layer.

Abstract: A wafer having heterostructure therein is formed using a substrate with recesses formed within a dielectric layer. A magnetized magnetic layer or a polarized electret material is formed at the bottom of each recess. The magnetized magnetic layer or a polarized electret material provides a predetermined magnetic or electrical field pattern. A plurality of heterostructures is formed from on an epitaxial wafer wherein each heterostructure has formed thereon a non-magnetized magnetic layer that is attracted to the magnetized magnetic layer formed at the bottom of each recess or dielectric layer that is attracted to the polarized electret material formed at the bottom of each recess. The plurality of heterostructures is etched from the epitaxial wafer to form a plurality of heterostructure pills.

Abstract: A process for selectively forming a metal barrier layer on a surface of an interconnect of a wiring substrate comprising the steps of abrading the substrate and simultaneously feeding onto the substrate a plating solution having said metal dissolved therein. The abrading step comprises contacting the substrate against an abrasive surface and causing relative linear and/or rotary motion between the abrasive surface and the substrate while the substrate is in contact with the abrasive surface. Growth of the metal barrier layer on a portion of the wiring substrate other than the interconnect layer is suppressed and the metal barrier layer thus formed is thinner, exhibits improved uniformity and superior prevention against Cu diffusion.

Abstract: A method of depositing a silicon oxide layer over a substrate having a trench formed between adjacent raised surfaces. In one embodiment the silicon oxide layer is formed in a multistep process that includes depositing a first portion of layer over the substrate and within the trench by forming a high density plasma process that has simultaneous deposition and sputtering components from a first process gas comprising a silicon source, an oxygen source and helium and/or molecular hydrogen with high D/S ratio, for example, 10-20 and, thereafter, depositing a second portion of the silicon oxide layer over the substrate and within the trench by forming a high density plasma process that has simultaneous deposition and sputtering components from a second process gas comprising a silicon source, an oxygen source and molecular hydrogen with a lower D/S ratio of, for example, 3-10.

Abstract: One aspect of the invention relates to a method of removing a hard mask from a surface, especially a silicon surface. The hard mask is removed by first applying a sacrificial coating and then plasma etching. The sacrificial material fills pattern gaps formed using the hard mask and protects insulators, such as oxides, within those pattern gaps. The sacrificial material is removed together with the hard mask by the plasma etching. The invention provides a process for removing hard masks from silicon layers without significantly damaging either the silicon layer or any exposed oxides and can be applied in a variety of integrated circuit device manufacturing processes, such as patterning the floating gate layer of a flash memory device.

Abstract: A silicon substrate is immersed in potassium hydroxide solution. Then, a main surface of the silicon substrate, which is immersed in the potassium hydroxide solution, is anodized by applying an electrical potential to the silicon substrate while the silicon substrate is used as an anode, so that an oxide film is formed in the main surface of the silicon substrate. Then, a main surface side of the silicon substrate is etched in the potassium hydroxide solution.

Abstract: An apparatus for processing a semiconductor wafer or similar article includes a reactor having a processing chamber formed by upper and lower rotors. The wafer is supported between the rotors. The rotors are rotated by a spin motor. A processing fluid is introduced onto the top or bottom surface of the wafer, or onto both surfaces, at a central location. The fluid flows outwardly uniformly and in all directions. A wafer support automatically lifts the wafer, so that it can be removed from the reactor by a robot, when the rotors separate from each other after processing.

Abstract: (PROBLEM) To improve the productivity and the yield of a product, and to grind a semiconductor substrate so that it has almost uniform thickness. (MEANS TO SOLVE THE PROBLEM) A protrusion 40 is formed on a semiconductor substrate 10 having a first area 20 and a second area 30 surrounding the first area 20, the protrusion 40 protruding above first area 20. A support 60 is disposed on a surface on which the protrusion 40 is formed, of the semiconductor substrate 10 so that a through hole 61 of the support 60 overlaps with the first area 20. The semiconductor substrate 10is grinded from a surface opposite to the surface on which the protrusion 40 is formed.

Abstract: An embodiment of the invention is a method to reduce the corrosion of copper interconnects 90 by forming a thiol ligand coating 130 on the surface of the copper interconnects 90.

Abstract: In a first aspect, a method is provided that includes (1) forming a first barrier layer over the sidewalls and bottom of a via using atomic layer deposition within an atomic layer deposition (ALD) chamber; (2) removing at least a portion of the first barrier layer from the bottom of the via by sputter etching; and (3) depositing a second barrier layer on the sidewalls and bottom of the via within the ALD chamber. Numerous other embodiments are provided, as are systems, methods and computer program products in accordance with these and other aspects.

Abstract: A multi-step HDP deposition and sputtering process for void-free filling of high aspect ratio trenches having stepped cross-sectional profiles. The method is particularly applicable to filling trenches formed in triply layered substrates comprising a silicon first layer, an oxide second layer and a nitride third layer, wherein the nitride layer is pulled back from the edge of the trench opening and forms a step. The method allows the void-free filling of such a trench without dam aging the nitride layer in the process. Briefly, the essence of the method is the formation of deposited layers on the side walls of the trench wherein the first layer is deposited with a high deposition to sputtering ratio and low bias power to form a layer with an overhang at the upper surface of the trench. This deposition if followed by a sputtering process to form an enlarged opening in that overhang.

Abstract: The invention relates to a method for trench etching, in particular a method for anisotropic deep trench (DT) etching in an Si substrate by plasma dry etching, such as reactive ion etching (RIE), magnetically enhanced RIE or inductively coupled plasma etching (ICP), and sidewall passivation of the etched trenches in the Si substrate, the Si substrate being provided with an etching mask before the beginning of the etching operation. The invention is intended to provide a method for depth etching which, with a low outlay, makes it possible to achieve a significantly larger etching depth at higher speed and which enables a further reduction of the structure widths without any difficulty.

Abstract: A method for removing chamber deposits in between process operations in a semiconductor process chamber is provided. The method initiates with depositing a fluorine containing polymer layer over an inner surface of a semiconductor process chamber where the semiconductor chamber is empty. Then, a wafer is introduced into the semiconductor process chamber after depositing the fluorine containing polymer layer. Next, a process operation is performed on the wafer. The process operation deposits a residue on the fluorine containing polymer layer covering the inner surface of the semiconductor process chamber. Then, the wafer is removed from the semiconductor process chamber. Next, an oxygen based cleaning operation is performed. The oxygen based cleaning operation liberates fluorine from the fluorine containing polymer layer to remove a silicon based residue. An apparatus configured to remove chamber deposits between process operations is also provided.

Abstract: A method of treating a silicon surface of a substrate that includes heating the substrate in a process chamber to a temperature, exposing a first area adjacent to the silicon surface to a first gas mixture comprising an etchant, a silicon source gas, and a carrier, exposing a second area adjacent to the silicon surface to a second gas mixture, wherein the second gas mixture is different from the first gas mixture.

Abstract: An exemplary system and method for providing a microwave regime, frequency-agile device is disclosed as comprising inter alia: a low-loss, insulating substrate (200); a layer of SiO2 (210) over the surface of said substrate; and a layer of BST (220) deposited over the SiO2 layer (210). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize frequency response or other material characteristics. Exemplary embodiments of the present invention representatively provide for integrated high-efficiency, low-loss microwave components that may be readily incorporated with existing technologies for the improvement of frequency response, device package form factors, weights and/or other manufacturing, device or material performance metrics.

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a dielectric layer. The dielectric layer is patterned so as to expose the metal conductor. A liner layer is then deposited into the pattern. The liner layer is then argon sputter etched to remove the liner layer and expose the metal conductor. In the process of argon sputter etching, the liner layer is redeposited onto the sidewall of the pattern. Lastly, an additional layer is deposited into the pattern and covers the redeposited liner layer.

Abstract: The present invention relates to etching for removing a carbon thin film formed on a surface of a sample, to prevent a damage on a sample and eliminate the necessity of providing a special device (such as vacuum pump) as is required in plasma etching. A sealed reaction chamber 100A in which a sample 500 formed with a carbon thin film 510 on its surface is to be set, a gas feed means 200A for feeding argon gas which is an inert gas Ar into which a predetermined proportion of oxygen gas O2 has been mixed from one end to the interior of the reaction chamber 100A, an exhaust means 300A for discharging carbon dioxide gas CO2 from the downstream side of the inert gas Ar fed from the gas feed means 200A, and a heating means 400A for heating the sample 500 to 550° C. or higher are provided.

Abstract: A method of etching a deep, high aspect ratio opening in a silicon substrate includes etching the substrate with a first plasma formed using a first gaseous mixture including a bromine containing gas, an oxygen containing gas and a first fluorine containing gas. The etching process with the first gaseous mixture produces a sidewall passivating deposit, which builds up near the opening entrance. To reduce this buildup, and to increase the average etching rate, the sidewall passivating deposit is periodically thinned by forming a second plasma using a mixture containing silane and a second fluorine containing gas. The substrate remains in the same plasma reactor chamber during the entire process and the plasma is continuously maintained during the thinning step. Holes of a depth greater than 40 times the width may be produced using repeated cycles of etching and thinning.

Abstract: A method for forming atomic-scale contacts and atomic-scale gaps between two electrodes is disclosed. The method provides for applying a voltage between two electrodes in a circuit with a resistor. The applied voltage etches metal ions off one electrode and deposits the metal ions onto the second electrode. The metal ions are deposited on the sharpest point of the second electrode, causing the second electrode to grow towards the first electrode until an atomic-scale contact is formed. By increasing the magnitude of the resistor, the etching and deposition process will terminate prior to contact, forming an atomic-scale gap. The atomic-scale contacts and gaps formed according to this method are useful as a variety of nanosensors including chemical sensors, biosensors, hydrogen ion sensors, heavy metal ion sensors, magnetoresistive sensors, and molecular switches.

Abstract: A method of forming a copper wiring in a semiconductor device. The method can prevent an increase of a dielectric constant of a low dielectric constant film and making bad deposition of a copper anti-diffusion film, due to infiltration of an organic solvent, an etch gas, etc. into the low dielectric constant film exposed at the side of a damascene pattern during a wet cleaning process for removing polymer generating when a portion of the low dielectric constant film is etched to form the damascene pattern or during a photoresist pattern strip process. In order accomplish these purpose, a CFXHY polymer layer is changed to a SiCH film using SiH4 plasma without removing the polymer layer formed at the side of the damascene pattern. Therefore, infiltration of an organic solvent or an etch gas can be prevented due to the SiCH film having a condensed film quality and a good mechanical strength.

Abstract: A method for forming silicon quantum dots and a method for fabricating a nonvolatile memory device using the same, suitable for high speed and high packing density. The method for forming silicon quantum dots includes the steps of forming a first insulating film on a semiconductor substrate, forming a plurality of nano-crystalline silicons on the first insulating film, forming a second insulating film on the first insulating film including the nano-crystalline silicons, partially etching the second insulating film and the nano-crystalline silicons, and oxidizing surfaces of the nano-crystalline silicons.

Abstract: A method to redistribute solid copper deposited by PVD on a wafer topography. The deposited copper is solubilized in a fluid for redistribution. The copper redistribution prevents inherent nonuniformity of the deposited copper film thickness by improving the uniformity of thickness of the copper film on the covered surfaces, such as vertical and bottom surfaces. The method provides the advantages of good adhesion and good grain growth and orientation that are achieved with copper deposited by PVD, and also provides the good step coverage as achieved with copper deposited by CVD.

Abstract: Structure and method for filling an opening in a semiconductor structure that is less susceptible to the formation of voids. A first layer of a first material is formed over the layer in which the opening is to be formed, and a faceted opening is formed in the first layer. The opening in the underlying layer is subsequently formed, and the material that is to fill the opening is deposited over the faceted opening and into the opening of the underlying layer.

Abstract: A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the substrate. In conjunction with the material layer deposition, the etch species selectively remove portions of the deposited material layer adjacent to high aspect ratio feature openings, filling such features in a void-free and/or seam-free manner. The material layer may be deposited on the substrate using physical vapor deposition (PVD) and/or chemical vapor deposition (CVD) techniques.

Abstract: A method for forming atomic-scale contacts and atomic-scale gaps between two electrodes is disclosed. The method provides for applying a voltage between two electrodes in a circuit with a resistor. The applied voltage etches metal ions off one electrode and deposits the metal ions onto the second electrode. The metal ions are deposited on the sharpest point of the second electrode, causing the second electrode to grow towards the first electrode until an atomic-scale contact is formed. By increasing the magnitude of the resistor, the etching and deposition process will terminate prior to contact, forming an atomic-scale gap. The atomic-scale contacts and gaps formed according to this method are useful as a variety of nanosensors including chemical sensors, biosensors, hydrogen ion sensors, heavy metal ion sensors, magnetoresistive sensors, and molecular switches.

Abstract: A method of etching a semiconductor substrate is described, the method comprising the steps of applying a paste containing an etchant to the substrate, and carrying out a thermal processing step to etch a part or a layer of the substrate where the paste has been applied. The etchant paste is preferably a caustic etching paste. The etchant paste may be applied selectively to a major surface of the substrate to form a pattern of applied paste. For example, the paste may be applied by a printing method, such as screen-printing. The method may be used to produce solar cells.

Abstract: Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.

Abstract: A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.

Abstract: In forming an opening or space in a substrate, a layer of photoresist is provided on the substrate, and the photoresist is patterned to provide photoresist bodies having respective adjacent sidewalls. A polymer layer is provided on the resulting structure through a low temperature conformal CVD process. The polymer layer is anisotropically etched to form spacers on the respective adjacent sidewalls of the photoresist bodies. The substrate is then etched using the spacers as a mask.

Abstract: A cross-section is obtained in which a sample shape is clearly delineated by forming a covering layer of a material different from that of the sample surface on the sample surface, forming a protective layer on the covering layer forming a hole in the protective and covering layers and the sample surface to expose the cross-section, and tilting the sample and scanning the cross-section with a focused ion beam so as to obtain a microscopic image of the cross-section. By forming the covering layer of a material different from that of the sample surface, the shape of the sample can be clearly viewed in the obtained image.

Abstract: A cleaning agent which comprises 0.1 to 60% by weight of an oxidizing agent and 0.0001 to 5% by weight of a chelating agent. In the process for producing semiconductor integrated circuits, a pattern layer of a photoresist used as an etching mask and residues formed from the photoresist by dry etching can be easily removed with the cleaning agent. In the process for producing substrates for liquid crystal display panels, residues derived from a conductive thin film formed by dry etching can also be easily removed. In the cleaning processes using the cleaning agent, wiring materials or insulating materials in thin film circuit devices or other materials used for producing substrates of semiconductor integrated circuits and liquid crystal panels are not corroded.

Abstract: A first insulating film is formed on an underlying substrate, the first insulating film being made of a first insulating material. A second insulating film is formed on the first insulating film, the second insulating film being made of a second insulating material different from the first insulating material. A trench is formed through the second and first insulating film, the trench reaching at least an intermediate depth of the first insulating film. A wiring layer made of a conductive material is deposited on the second insulating film, the wiring layer burying the trench. The wiring layer is polished to leave the wiring layer in the trench. The wiring layer and second insulating film are polished until the first insulating film is exposed. Irregularity such as dishing and erosion can be suppressed from being formed.

Abstract: A method of removing photoresist material from a semiconductor substrate includes providing a semiconductor substrate having a patterned photoresist mask. A layer comprised of polymer material is formed over the patterned photoresist mask. The layer comprised of polymer material and a portion of the patterned photoresist mask are then removed. The layer comprised of polymer material is preferably formed by introducing a process gas into a plasma environment and is preferably formed with less thickness in a low aspect ratio area relative to a high aspect ratio area.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy and epitaxial growth of single crystal silicon onto single crystal oxide materials. Monocrystalline substrates having a hydrogen ion implant are cleaved along the hydrogen ion implant, and an insulating substrate is bonded to the monocrystalline oxide.

Abstract: The invention relates to a process for treating semiconductor substrates in which metal layers are exposed by removing one or more layers of the surface of a semiconductor substrate which have been applied to the metal layer, in which exposure takes place in a time sequence to a first part of the layer by a dry etching step and to a second part of the layer by a wet etching step.

Abstract: First, a pattern of electrodes or interconnects is formed on a semiconductor substrate. Next, a first insulating film, which will be dry-etched at a relatively high rate and exhibit relatively high planarity, is deposited over the substrate as well as over the pattern. Subsequently, a second insulating film, which will be dry-etched at a relatively low rate and exhibit relatively low planarity, is deposited over the first insulating film. Thereafter, a multilayer structure, including a ferroelectric film, is formed on the second insulating film and then dry-etched and patterned, thereby forming an electronic device out of the multilayer structure.

Abstract: The present invention pertains to a method for depositing built-up structures on the surface of patterned masking material used for semiconductor device fabrication. Such built-up structures are useful in achieving critical dimensions in the fabricated device. The composition of the built-up structure to be fabricated is dependant upon the plasma etchants used during etching of underlying substrates and on the composition of the substrate material directly underlying the masking material.

Abstract: A process for manufacturing a semiconductor substrate, comprising the step of preparing a first substrate which has a surface layer portion subjected to hydrogen annealing, the separation-layer formation step of implanting ions of hydrogen or the like into the first substrate from the side of the surface layer portion, thereby to form a separation layer, the adhesion step of bonding the first substrate and a second substrate to each other so that the surface layer portion may lie inside, thereby to form a multilayer structure, and the transfer step of separating the multilayer structure by utilizing the separation layer, thereby to transfer the less-defective layer of the surface layer portion onto the second substrate. The less-defective layer is a single-crystal silicon layer in which defects inherent in a bulk wafer, such as COPs and FPDs, are decreased.

Abstract: A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic circuit region of the semiconductor device, the deep trench isolation being filled with an insulative material. The deep trench isolation thereby prevents the propagation of crystal defects generated in the logic circuit region from propagating into the memory storage region.

Abstract: semiconductor chip. The method comprises etching a backside of the semiconductor chip, the frontside including a first well with a first type of doping and a second well with a second type of doping; monitoring a backside of the semiconductor chip during etching; and determining when a first portion of the backside over one of the first and second wells differs from a second portion of the backside over the other of the first and second wells. A method for etch endpoint detection includes etching a backside of a semiconductor chip, the semiconductor chip having at least one doped well formed proximate a frontside of the semiconductor chip; monitoring the backside of the semiconductor chip during etching until at least one doped well becomes visible; and stopping etching after the doped well becoming visible.

Abstract: A method for forming a wirebond connection to an integrated circuit structure includes forming an insulative structure overlaying a corrosion susceptible metal wiring within the integrated circuit structure, defining a via through the insulative structure above a portion of the corrosion susceptible metal without exposing the portion of the corrosion susceptible metal, and attaching a wirebond material to the portion of the corrosion susceptible metal. The attaching process includes a preliminary process of exposing the portion of the corrosion susceptible metal. The attaching completely covers the portion of the corrosion susceptible metal.

Abstract: A two-step method of etching an organic coating layer, in particular, an organic antireflection coating (ARC) layer, is disclosed. During the main etch step, the organic coating layer is etched using a plasma generated from a first source gas which includes a fluorocarbon and a non-carbon-containing, halogen-comprising gas. Etching is performed using a first substrate bias power. During the overetch step, residual organic coating material remaining after the main etch step is removed by exposing the substrate to a plasma generated from a second source gas which includes a chlorine-containing gas and an oxygen-containing gas, and which does not include a polymer-forming gas. The overetch step is performed using a second substrate bias power which is less than the first substrate bias power.

Abstract: A method and system for fabricating an array of electronic devices, typically a display or sensor is described. In the method, a droplet source ejects droplets of a masking material for deposit on a thin film or substrate surface to mask an element of the array of electronic devices. The temperature of the thin-film or substrate surface is controlled such that the droplets rapidly freeze upon contact with the thin-film or substrate surface. The thin-film or substrate is then etched. After etching the masking material is removed.

Abstract: Layers of boron-doped silicon having reduced out-of-plane curvature are disclosed. The layers have substantially equal concentrations of boron near the top and bottom surfaces. Since the opposing concentrations are substantially equal, the compressive stresses on the layers are substantially balanced, thereby resulting in layers with reduced out-of-plane curvature.

Abstract: A method for defining plural windows with different etching depths simultaneously is disclosed. The method includes steps of (a) forming a photoresist on a substrate having a multiple film structure thereon, (b) exposing a first region of the photoresist to a first exposure dose and a second region of the photoresist to a second exposure dose, (c) obtaining different remaining thickenesses of the photoresist on the first region and the second region by a development, and (d) etching the first region and the second region of the photoresist for forming the plural windows with different etching depths of the multiple film structure.

Abstract: A dual depth trench isolation structure formed between active devices and conductive well regions of same conductivity type which comprises a first inter-well isolation structure having a first isolation trench depth, a second inter-well isolation structure having a second isolation trench depth which combine to form a dual depth trench containing the dual depth trench isolation structure comprising the first inter-well isolation structure and the second inter-well isolation structure, with the dual depth trench isolation interposed at the boundary of an n-well conductive region and a p-well conductive region, a first intra-well isolation structure having a first isolation trench depth, the first intra-well isolation structure interposed between a pair of p-channel transistors residing in the n-well region, and a second intra-well isolation structure having a second isolation trench depth, the second intra-well isolation structure interposed between a pair of n-channel transistors residing in the p-well regio

Abstract: A method for fabricating a semiconductor device capable of maintaining contact hole of fine size when the contact hole for bit line formation is defined.

Abstract: A process for selectively etching silicon from a workpiece without etching silicon oxide or silicon nitride. The principal etchant gas is molecular fluorine gas (F2) that is not excited to a plasma state.