Abstract: When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, pronounced loss of the interlayer dielectric material may be avoided by inserting at least one surface modification process, for instance in the form of a nitridation process. In this manner, leakage paths caused by metal residues formed in the interlayer dielectric material may be significantly reduced.

Abstract: According to one embodiment, a method for chemical planarization includes: preparing a treatment liquid containing a hydrosilicofluoric acid aqueous solution containing silicon dioxide dissolved therein at a saturated concentration; and decreasing height of irregularity of a silicon dioxide film. In the decreasing, dissolution rate of convex portions is made larger than dissolution rate of concave portion of the irregularity while changing equilibrium state of the treatment liquid at areas being in contact with the convex portions of the irregularity, in a state in which the silicon dioxide film having the irregularity is brought into contact with the treatment liquid.

Abstract: The invention provides a method for manufacturing a transistor which includes: providing a substrate having a plurality of transistors formed thereon, wherein each transistor includes a gate; forming a stressed layer and a first oxide layer on the transistors and on the substrate successively; forming a sacrificial layer on the first oxide layer; patterning the sacrificial layer to remove a part of the sacrificial layer which covers on the gates of the transistors; forming a second oxide layer on the residual sacrificial layer and on a part of the first oxide layer which is exposed after the part of the sacrificial layer is removed; performing a first planarization process to remove a part of the second oxide layer located on the gates of the transistors; performing a second planarization process to remove the residual second oxide layer; and performing a third planarization process to remove the stressed layer.

Abstract: Low-temperature in-situ techniques are provided for the removal of oxide from a silicon surface during CMOS epitaxial processing. Oxide is removed from a semiconductor wafer having a silicon surface, by depositing a SiGe layer on the silicon surface; etching the SiGe layer from the silicon surface at a temperature below 700 C (and above, for example, approximately 450 C); and repeating the depositing and etching steps a number of times until a contaminant is substantially removed from the silicon surface. In one variation, the deposited layer comprises a group IV semiconductor material and/or an alloy thereof.

Abstract: In a semiconductor device and a method of forming the same, the semiconductor device comprises: a first insulating layer on an underlying contact region of the semiconductor device, the first insulating layer having an upper surface; a first conductive pattern in a first opening through the first insulating layer, an upper portion of the first conductive pattern being of a first width, an upper surface of the first conductive pattern being recessed relative to the upper surface of the first insulating layer so that the upper surface of the first conductive pattern has a height relative to the underlying contact region that is less than a height of the upper surface of the first insulating layer relative to the underlying contact region; and a second conductive pattern contacting the upper surface of the first conductive pattern, a lower portion of the second conductive pattern being of a second width that is less than the first width.

Abstract: A method for obtaining a layout design for an existing integrated circuit, in which, an integrated circuit die is polished with a tilt angle to form an inclined polished surface and one or more images of the inclined polished surface are obtained. The images may be overlapped directly, or the image or the images may be utilized to provide information to obtain a layout design comprising at least one repeating unit structure of the layout structure.

Abstract: Adaptive imprint planarization provides a surface having desired shape characteristics. Generally, topography of a first surface is mapped to provide a density map. The density map is evaluated to provide a drop pattern for dispensing polymerizable material on the first surface. The polymerizable material is solidified and etched to provide a second surface having the desired shape characteristics. Additionally, adaptive imprint planarization compensates for parasitic effects of the imprinting process.

Abstract: A semiconductor device which has a semiconductor substrate, an isolation insulating film formed in the semiconductor substrate, a conductive pattern formed over the semiconductor substrate and the isolation insulating film, so that a side face of the conductive pattern is formed over the isolation insulating film, and an insulating film is formed over the isolation insulating film, the conductive pattern and the side face of the conductive pattern, and the side face of the conductive pattern comprises a notch.

Abstract: A method for integrating a replacement gate in a semiconductor device is disclosed.

Abstract: Provided is a method of planarizing a semiconductor device. The method includes providing a substrate. The method includes forming a first layer over the substrate. The method includes forming a second layer over the first layer. The first and second layers have different material compositions. The method includes forming a third layer over the second layer. The method includes performing a polishing process on the third layer until the third layer is substantially removed. The method includes performing an etch back process to remove the second layer and a portion of the first layer. Wherein an etching selectivity of the etch back process with respect to the first and second layers is approximately 1:1.

Abstract: A contact for memory cells and integrated circuits having a conductive layer supported by the sidewall of a dielectric mesa, memory cells incorporating such a contact, and methods of forming such structures.

Abstract: There is provided a peeling method capable of preventing a damage to a layer to be peeled. Thus, not only a layer to be peeled having a small area but also a layer to be peeled having a large area can be peeled over the entire surface at a high yield. Processing for partially reducing contact property between a first material layer (11) and a second material layer (12) (laser light irradiation, pressure application, or the like) is performed before peeling, and then peeling is conducted by physical means. Therefore, sufficient separation can be easily conducted in an inner portion of the second material layer (12) or an interface thereof.

Abstract: Processes for forming high density gap-filling silicon oxide on a patterned substrate are described. The processes increase the density of gap-filling silicon oxide particularly in narrow trenches. The density may also be increased in wide trenches and recessed open areas. The densities of the gap-filling silicon oxide in the narrow and wide trenches/open areas become more similar following the treatment which allows the etch rates to match more closely. This effect may also be described as a reduction in the pattern loading effect. The process involves forming then planarizing silicon oxide. Planarization exposes a new dielectric interface disposed closer to the narrow trenches. The newly exposed interface facilitates a densification treatment by annealing and/or exposing the planarized surface to a plasma.

Abstract: The Invention relates to a method for producing a solid support coated by a metal Layer to which an SiOx layer provided with a uniform and stable thickness is applied, wherein said solid support makes it possible to determine the pretense of a compound on the surface thereof by means of Surface Plasmon Resonance (?SPR ?).

Abstract: A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device.

Abstract: There is provided an anode for an organic electronic device. The anode is a conducting inorganic material having an oxidized surface layer. The surface layer is non-conductive and hole-transporting.

Abstract: Reliability and yield of MTJ devices is improved by reducing surface roughness in the MTJ layers of the MTJ devices. Surface roughness is reduced by reducing surface roughness of layers below the MTJ layers such as the bottom electrode layer. Planarizing the bottom electrode layer through chemical mechanical polishing or etch back of spin-on material before depositing the MTJ layers decreases surface roughness of the bottom electrode layer and the MTJ layers. Alternatively, a capping layer may be planarized before deposition of the bottom electrode layer and MTJ layers to reduce surface roughness in the capping layer, the bottom electrode layer, and the MTJ layers.

Abstract: The present invention provides a method of fabricating a semiconductor device including forming stop layers (32) that include silicon oxy-nitride films above a semiconductor substrate, forming a cover film (34) between and on the stop layers, in which a top surface of the cover film above a region between the stop layers is higher than top surfaces of the stop layers, and polishing the cover film to the stop layers by using ceria slurry, and also provides a semiconductor device including metal layers (30) provided above a semiconductor substrate, silicon oxy-nitride films (32) provided on the metal layers, and an embedded layer (36) provided between the metal layers to have a top surface substantially coplanar with top surfaces of the silicon oxy-nitride films. According to the present invention, it is possible to provide a semiconductor device having a film of excellent planarization on a surface thereof and fabrication method therefor.

Abstract: Provided are a nonvolatile memory device, a method of manufacturing the nonvolatile memory device, and a method of manufacturing a flat panel display device provided therein with the nonvolatile memory device. According to an embodiment, an amorphous silicon layer is formed on a substrate, and then annealed by using an Excimer laser to form a crystallized silicon layer. A nitrogen plasma treatment is performed for the crystallized silicon layer to planarize an upper surface of the crystallized silicon layer. An ONO layer is formed on the nitrogen plasma-treated crystallized silicon layer. A metal layer is formed on the ONO layer. The metal layer, the ONO layer and the nitrogen plasma-treated crystallized silicon layer are patterned.

Abstract: A patterning method has a mask layer and undoped patterns sequentially formed on a target layer. A doping process is performed to surfaces of the undoped patterns to form doped patterns from the surfaces of the undoped patterns. A material is filled in the gaps between the doped patterns. A portion of the doped patterns are then removed to expose the top surfaces of the remaining undoped patterns. The material and the exposed undoped patterns are removed. A portion of the mask layer is removed using the remaining doped patterns as a mask to form a first pattern on the mask layer. A portion of the target layer is removed using the mask layer having the first pattern thereon as a mask so as to form on the target layer a second pattern complementary to the first pattern.

Abstract: A manufacturing method of a device is provided. In the manufacturing method, a substrate is provided. The substrate has a plurality of patterns and a plurality of openings formed thereon, and the openings are located among the patterns. A first liquid supporting layer is formed on the patterns, and the openings are filled with the first liquid supporting layer. The first liquid supporting layer is transformed into a first solid supporting layer. The first solid supporting layer includes a plurality of supporting elements formed in the openings, and the supporting elements are formed among the patterns. A treatment process is performed on the patterns. The first solid supporting layer that includes the supporting elements is transformed into a second liquid supporting layer. The second liquid supporting layer is removed.

Abstract: A method for fabricating an integrated circuit device is disclosed. The method includes providing a substrate; forming a semiconductor feature over the substrate; forming a first photoresist layer over the substrate; performing a lithography process on the first photoresist layer, such the first photoresist layer includes an opening therein that exposes the semiconductor feature; performing a stabilization process on the first photoresist layer; forming a second photoresist layer over the first photoresist layer, wherein the second photoresist layer fills the opening; and etching back the first and second photoresist layers until the semiconductor feature is exposed.

Abstract: A method for manufacturing an interconnection wiring structure of a semiconductor device includes forming an isolation region, which arranges active regions in a diagonal direction, in a semiconductor substrate; forming first damascene trenches, which open upper portions of a bit line contacts, by selectively etching a second interlayer insulation layer; forming bit lines which fill the first damascene trenches; forming second damascene trenches, which expose portions of the active region, by selectively etching the portion of a second interlayer insulation layer between the bit lines and the portion of the first interlayer insulation layer thereunder; attaching trench spacer on side walls of the second damascene trench; forming storage node contact lines which fill the second damascene trenches.

Abstract: The invention relates generally to preparation of a substrate for use in a photovoltaic device by application of a filling material and subsequent planarization of the top surface; optionally, a barrier layer is added.

Abstract: A semiconductor device, comprising a silicon layer, an n-type field-effect transistor (NFET) disposed in and on a silicon layer, and a p-type field-effect transistor (PFET) disposed in and on the silicon layer, wherein the PFET includes a boron-doped silicon-germanium layer disposed on the silicon layer. Also, a method for manufacturing a semiconductor device, comprising forming a first conductive layer over a p-well of a silicon layer, forming a second conductive layer over an n-well of the silicon layer, implanting fluorine ions into both the p-well and the n-well, exposing both the p-well and the n-well to ammonium hydroxide and peroxide, and epitaxially growing a boron-doped silicon-germanium layer on the silicon layer.

Abstract: Planarization methods include depositing a mask material on top of an overburden layer on a semiconductor wafer. The mask material is planarized to remove the mask material from up areas of the overburden layer to expose the overburden layer without removing the mask material from down areas. The exposed overburden layer is wet etched and leaves a thickness remaining over an underlying layer. Remaining portions of the mask layer and the exposed portions of the overburden layer are planarized to expose the underlying layer.

Abstract: A method for manufacturing a semiconductor device comprises performing a CMP process using an oxide film as an etching barrier film to maintain a polysilicon layer having a large open area. A word line pattern, a DSL pattern, and a SSL pattern that are formed by a first patterning process are not additionally blocked, and the oxide film is used as an etching barrier to obtain an accurate overlay between patterns and improve CD uniformity, thereby improving a characteristic of the device.

Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.

Abstract: Embodiments provide methods for etching and depositing silicon materials on a substrate. In one example, the method includes heating a substrate containing a silicon-containing material to a temperature of about 800° C. or less and removing a portion of the silicon-containing material and a contaminant to reveal an exposed surface of the silicon-containing material during an etching process and depositing a silicon-containing layer on the exposed surface of the silicon-containing material during a deposition process. The method further provides conducting the etching and deposition processes in the same chamber and utilizing chlorine gas and a silicon source gas during the etching and deposition processes. In some examples, the silicon-containing material is removed at a rate within a range from about 2 ? per minute to about 20 ? per minute during the etching process.

Abstract: A method of manufacturing a flash memory device having an enhanced gate coupling ratio includes steps of forming a first semiconductor layer on a substrate and forming a semiconductor spacer layer on top of the first semiconductor layer. The semiconductor spacer layer includes a plurality of recesses. The method provides a semiconductor spacer structure which functions to increase the contact area between a floating gate and a control gate of the flash memory device.

Abstract: A semiconductor device includes a first conductive structure and a second conductive structure. The first conductive structure is formed in a first region of a substrate, and includes a first polysilicon layer pattern, a first conductive layer pattern having a resistance smaller than that of the first polysilicon layer pattern, and a first hard mask. The second conductive structure is formed in a second region of the substrate and has a thickness substantially the same as that of the first conductive structure. The second conductive structure includes a second polysilicon layer pattern, a second conductive layer pattern having a resistance smaller than that of the second polysilicon layer pattern and having a thickness different from that of the first conductive layer pattern, and a second hard mask.

Abstract: The invention discloses a planarization method for a wafer having a surface layer with a recess, comprises: forming an etching-resist layer on the surface layer to fill the entire recess; etching the etching-resist layer and the surface layer, till the surface layer outside the recess is flush to or lower than the bottom of the recess, the etching speed of the surface layer being higher than that of the etching-resist layer; removing the etching-resist layer; and etching the surface layer to a predetermined depth. The method can avoid concentric ring recesses on the surface of the wafer resulted from a chemical mechanical polishing (CMP) process in the prior art, and can be used to obtain a wafer surface suitable for optical applications.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. Self-aligned assist pattern (SAP) is derived from original design layout in an automated manner using geometric Boolean operations based on some predefined design rules, and are included in the mask layout for efficient self-alignment of various sub-layouts of the target pattern during a multiple patterning lithography process. SAP can be of any shape and size, and can have continuous features (e.g., a ring), or discontinuous (e.g., bars not connected to each other) features. An end-to-end multiple patterning lithography using spacer and SAP may use positive tone lithography, and/or negative tone lithography for line and/or space printing.

Abstract: Methods are provided for etching and/or depositing an epitaxial layer on a silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer has a cleaved surface defining an outer surface of the structure. The cleaved surface of wafer is then etched while controlling a temperature of the reactor such that the etching reaction is kinetically limited. An epitaxial layer is then deposited on the wafer while controlling the temperature of the reactor such that a rate of deposition on the cleaved surface is kinetically limited.

Abstract: A method for fabricating an integrated circuit device is disclosed. The method includes providing a substrate; forming a semiconductor feature over the substrate; forming a first photoresist layer over the substrate; performing a lithography process on the first photoresist layer, such the first photoresist layer includes an opening therein that exposes the semiconductor feature; performing a stabilization process on the first photoresist layer; forming a second photoresist layer over the first photoresist layer, wherein the second photoresist layer fills the opening; and etching back the first and second photoresist layers until the semiconductor feature is exposed.

Abstract: The invention discloses a planarization method for a wafer having a surface layer with a recess, comprises: forming an etching-resist layer on the surface layer to fill the entire recess; etching the etching-resist layer and the surface layer, till the surface layer outside the recess is flush to or lower than the bottom of the recess, the etching speed of the surface layer being higher than that of the etching-resist layer; removing the etching-resist layer; and etching the surface layer to a predetermined depth. The method can avoid concentric ring recesses on the surface of the wafer resulted from a chemical mechanical polishing (CMP) process in the prior art, and can be used to obtain a wafer surface suitable for optical applications.

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features.

Abstract: A method of designing a semiconductor integrated circuit, includes dividing a layout area in which a wiring pattern is disposed, into a plurality of division areas, determining a dummy pattern disposition area provided in each of the plurality of division areas, adding a dummy pattern to the dummy pattern disposition area of each of the plurality of division areas, and combining division areas to which the dummy pattern is added. The dummy pattern disposition area is arranged away from at least one of boundaries between a corresponding division area of the plurality of division areas and adjacent division areas.

Abstract: A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.

Abstract: A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device.

Abstract: A method of forming a plurality of nanotubes is disclosed. Particularly, a substrate may be provided and a plurality of recesses may be formed therein. Further, a plurality of nanotubes may be formed generally within each of the plurality of recesses and the plurality of nanotubes may be substantially surrounded with a supporting material. Additionally, at least some of the plurality of nanotubes may be selectively shortened and at least a portion of the at least some of the plurality of nanotubes may be functionalized. Methods for forming semiconductor structures intermediate structures, and semiconductor devices are disclosed. An intermediate structure, intermediate semiconductor structure, and a system including nanotube structures are also disclosed.

Abstract: A method for forming a memory device includes forming a hard mask over a substrate, where the hard mask includes a first mask layer and a second mask layer formed over the first mask layer. The substrate is etched to form a trench. The trench is filled with a field oxide material. The second mask layer is stripped from the memory device using a first etching technique and the first mask layer is stripped from the memory device using a second etching technique, where the second etching technique is different than the first etching technique.

Abstract: A method for fabricating semiconductor device includes forming a nitride pattern and a hard mask pattern over a substrate, forming a trench by etching the substrate using the hard mask pattern as an etch barrier, forming an oxide layer filling the trench, performing a planarization process on the oxide layer until the nitride pattern is exposed, and removing the nitride pattern though a dry strip process using a plasma.

Abstract: Disclosed is a method for smoothing the surface of at least one side of a wafer which is obtained by slicing a semiconductor ingot. In this method, a fluid is applied according to projections of the wafer surface, thereby reducing the projections. Alternatively, a fluid is applied over the wafer surface, thereby smoothing the entire surface of the wafer while reducing the projections in the wafer surface.

Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.

Abstract: A method of manufacturing a semiconductor is provided. A fist metal layer can be formed on a lower structural layer, and an interlayer metal dielectric (IMD) layer can be formed on the first metal layer. A sacrificial oxide layer can be formed on the IMD layer, and a planarization process can be performed on the sacrificial oxide layer and the IMD layer to substantially eliminate a height difference of the IMD layer.

Abstract: A method of manufacturing a semiconductor device is provided. A pattern layer is formed on a substrate defined to include a main pattern region and a dummy pattern region. A preliminary main pattern and a preliminary dummy pattern may be formed by patterning the pattern layer so that an upper surface area of the preliminary dummy pattern facing away from a surface of the substrate is less than an entire area of the dummy pattern region that is be subjected to subsequent planarization. The preliminary main pattern and the preliminary dummy pattern are partially etched to form a main pattern and a dummy pattern.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of etch mask patterns over an etch target layer, each of the etch mask patterns including a first hard mask, a first pad layer, and a second pad layer, forming spacers on both sidewalls of the etch mask patterns, the spacers including a material substantially the same as that of the first pad layer, forming a second hard mask over the resulting substrate structure until gaps between the etch mask patterns are filled, the second hard mask including a material different from that of the first hard mask but substantially the same as that of the second pad layer, planarizing the second hard mask until the first pad layer is exposed, removing the first pad layer and the spacers, and etching the etch target layer using the remaining first and second hard masks as an etch barrier layer.

Abstract: Processes for forming high density gap-filling silicon oxide on a patterned substrate are described. The processes increase the density of gap-filling silicon oxide particularly in narrow trenches. The density may also be increased in wide trenches and recessed open areas. The densities of the gap-filling silicon oxide in the narrow and wide trenches/open areas become more similar following the treatment which allows the etch rates to match more closely. This effect may also be described as a reduction in the pattern loading effect. The process involves forming then planarizing silicon oxide. Planarization exposes a new dielectric interface disposed closer to the narrow trenches. The newly exposed interface facilitates a densification treatment by annealing and/or exposing the planarized surface to a plasma.

Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.