Abstract: According to the present invention, a dummy wafer is formed by forming a masking film on a rear surface of a silicon wafer; spray coating aluminum and depositing an aluminum film on a front surface of the silicon wafer; spray coating ceramics or carbon and depositing a ceramic film or carbon film on the aluminum film so that the aluminum film may be completely covered; and removing the masking film formed on the rear surface. Also, a dummy wafer can be formed by using an aluminum wafer as a wafer substrate and subjecting it to anodic oxidation to form a film of aluminum oxide.

Abstract: A deep trench self-alignment process for an active area of a partial vertical cell. A semiconductor substrate with two deep trenches is provided. A deep trench capacitor is formed in each deep trench, and an isolating layer is formed thereon. Each trench is filled with a mask layer. A photoresist layer is formed on the semiconductor substrate between the deep trenches, and the photoresist layer partially covers the mask layer. The semiconductor substrate is etched lower than the isolating layer using the photoresist layer and the mask layer as masks. The photoresist layer and the mask layer are removed, such that the pillar semiconductor substrate between the deep trenches functions as an active area.

Abstract: Disclosed is a method of manufacturing a semiconductor device. The method includes the steps of forming gates on a substrate, forming junction areas on a surface of the substrate, forming a first BPSG layer on a resultant structure of the substrate, performing a first CVD process for the first BPSG layer, forming a second BPSG layer on the first BPSG layer, forming a landing plug contact, depositing a polysilicon layer on a resultant structure of the substrate, and performing a second CMP process for the polysilicon layer, the second BPSG layer and the nitride hard mask. The CMP processes are carried by using acid slurry having a high polishing selectivity with respect to the nitride layer, so a step difference between the cell region and the peripheral region is removed, thereby simplifying the semiconductor manufacturing process and removing a dishing phenomenon.

Abstract: A method, composition, and computer readable medium for planarizing a substrate. In one aspect, the composition includes one or more chelating agents and ions of at least one transition metal, one or more surfactants, one or more oxidizers, one or more corrosion inhibitors, and deionized water. The composition may further comprise one or more agents to adjust the pH and/or abrasive particles. The method comprises planarizing a substrate using a composition including one or more chelating agents and ions of at least one transition metal.

Abstract: A method of forming a gate structure of a semiconductor device includes forming a gate insulation film and a polysilicon film on a semiconductor substrate where an active region and a field region are defined, followed by forming a buffer layer on the polysilicon film to minimize damage to the polysilicon film during a subsequent ion implantation process. The polysilicon film is made electrically conductive by the implanting of impurities into the polysilicon film. Gate patterns are then formed by etching the conductive polysilicon film and the gate insulation film. Defects, such as active pitting, associated with dual electrodes are effectively prevented because the polysilicon film is protected during the ion implanting process.

Abstract: A structure applied to a photolithographic process is provided. The structure comprises at least a film layer, an optical isolation layer, an anti-reflection coating and a photoresist layer sequentially formed over a substrate. In the photolithographic process, the optical isolation layer stops light from penetrating down to the film layer. Since the optical isolation layer is set up underneath the photoresist layer, light emitted from a light source during photo-exposure is prevented from reflecting from the substrate surface after passing through the film layer. Thus, the critical dimensions of the photolithographic process are unaffected by any change in the thickness of the film layer.

Abstract: A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116?) and then annealing the substrate so as to cause the regions of the lower portion (140?) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).

Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the water, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edges of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.

Abstract: A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

Abstract: A method for monitoring polishing process parameters for an integrated circuit structure on a substrate. A first metrology site is constructed on the substrate. The first metrology site represents a design extreme of a high density integrated circuit structure. The first metrology site is formed by placing a relatively small horizontal surface area trench within a relatively large surface area field of a polish stop material. A second metrology site is also constructed on the substrate. The second metrology site represents a design extreme of a low density integrated circuit structure. The second metrology site is formed by placing a relatively large horizontal surface area trench within a relatively small surface area field of a polish stop material. The substrate is covered with a layer of an insulating material, thereby at least filling the trenches.

Abstract: The integrated optical circuit of the present invention includes a substrate with a first cladding layer. A first core layer having one or more waveguiding elements is formed on the first cladding layer. A second cladding layer surrounds the waveguiding elements of the first core layer; the refractive index of the first and second cladding layers are selected to be less than the refractive index of the waveguiding element(s). Through simultaneous cladding material deposition and cladding material removal, the second cladding layer as deposited is substantially self-planarized, enabling further layers to be positioned on the second cladding layer without necessitating intermediate planarization. Further, the present invention permits planar waveguide cores having submicron core spacings to be covered by a subsequently-deposited cladding layer without cladding gaps, seams or other deleterious cladding defects.

Abstract: A method of manufacturing a semiconductor device having self-aligned contact structure with side wall spacers and offset nitride films. The method includes forming the side wall spacers as having lower side wall spacers that are composed of silicon oxide films and that are in contact with lower sides of gate electrode side walls, and as having upper side wall spacers that are composed of silicon nitride films and that are in contact with upper sides of the gate electrodes side walls. A distance is thus formed between the device substrate and an interface between the silicon nitride film and the silicon oxide film. This suppresses the hot carrier phenomenon and the occurence of poor contact.

Abstract: A method for reducing wafer surface scratching in a metal CMP process including providing a semiconductor wafer having a process surface comprising a blanket deposited metal layer; dry etching in an etchback process comprising a fluorine containing etching chemistry to remove at least a portion of the metal layer forming a metal and fluorine containing etching residue at the process surface; cleaning the process surface with a hydrofluoric acid (HF) containing cleaning solution; and carrying out a subsequent metal chemical mechanical polishing (CMP) process.

Abstract: A method for planarizing metal interconnects of a semiconductor wafer includes the steps of polishing the semiconductor wafer with a polishing solution and a polishing pad to planarize the metal interconnects. The polishing solution has by weight percent, 0.15 to 5 benzotriazole, 0 to 1 abrasive, 0 to 10 polymeric particles, 0 to 5 polymer-coated particles and balance water at a pH of less than 5 and a removal rate-pressure sensitivity (dr/dp) of at least 750 (?/min/psi). The polishing simultaneously accelerates removal of projecting metal from the metal interconnects with the polishing pad providing a first pressure that increases removal rate of the projecting metal; and it inhibits removal of recessed metal from the metal interconnects with the polishing pad providing a second pressure that decreases removal of the recessed metal.

Abstract: A copper-containing layer suitable for an electrical interconnect in a device such as an integrated circuit is created by a procedure in which a trench (104) is formed through a dielectric layer (102) down to a substrate (100). A diffusion barrier (106) is provided over the dielectric layer and into the trench. Copper (108) is deposited over the diffusion barrier and into the trench. Chemical mechanical polishing is utilized to remove the copper outside the trench down substantially to the diffusion-barrier material overlying the dielectric layer. A sputter etch, typically of the reactive type, is then performed to substantially remove the diffusion-barrier material overlying the dielectric layer. The sputter etch typically removes copper above and/or in the trench at approximately the same rate as the diffusion-barrier material so as to substantially avoid the undesirable dishing phenomenon.

Abstract: A new method and structure is provided for the polishing of the surface of a layer of low-k dielectric material. Low-k dielectric material of low density and relatively high porosity is combined with low-k dielectric material of high density and low porosity whereby the latter high density layer is, prior to polishing of the combined layers, deposited over the former low density layer. Polishing of the combined layers removes flaking of the polished low-k layers of dielectric. This method can further be extended by forming conductive interconnects through the layers of dielectric, prior to the layer of dielectric.

Abstract: A split gate FET wordline electrode structure and method for forming the same including an improved polysilicon etching process including providing a semiconductor wafer process surface comprising first exposed polysilicon portions and adjacent oxide portions; forming a first oxide layer on the exposed polysilicon portions; blanket depositing a polysilicon layer on the first exposed polysilicon portions and adjacent oxide portions; forming a hardmask layer on the polysilicon layer; carrying out a multi-step reactive ion etching (RIE) process to etch through the hardmask layer and etch through a thickness portion of the polysilicon layer to form second polysilicon portions adjacent the oxide portions having upward protruding outer polysilicon fence portions; contacting the semiconductor wafer process surface with an aqueous HF solution; and, carrying out a downstream plasma etching process to remove polysilicon fence portions.

Abstract: A semiconductor device manufacturing method that enables accurate recognition of an alignment mark and optimal formation of a buried wiring. The method includes depositing an insulation film above a semiconductor device, and then etching the insulation film to form a buried wiring hole and an alignment mark pit in the insulation film. Subsequently, a conductive film is deposited on the surface of the insulation film that includes the buried wiring hole and the alignment mark pit. The conductive film is deposited so that it is less than the depth of the alignment mark pit and less than half of a minimum opening width of the alignment mark pit.

Abstract: Ta—Al—N is formed on a semiconductor device structure, such as a wiring line, to prevent interdiffusion between surrounding layers. The Ta—Al—N material may serve as a diffusion between two conductor layers, a semiconductor layer and a conductor layer, an insulator layer and a conductor layer, an insulator layer and a semiconductor layer, or two semiconductor layers. Another use is to promote adhesion of adjacent layers, such as between two conductor layers, a conductor layer and an insulator layer, a semiconductor layer and a conductor layer, or two semiconductor layers. The Ta—Al—N material also may be used to form a contact or electrode.

Abstract: A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 ? can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH2Cl2) as the main reactive agent.

Abstract: A polishing method of the present invention is a polishing method for planarizing a film to be polished that is deposited on a wafer, and includes a step (a) of establishing a polishing rate distribution of the film to be polished that is deposited on the wafer and a target film thickness distribution after polishing of the film to be polished, a step (b) of measuring a film thickness distribution before polishing of the film to be polished, a step (c) of calculating a predicted film thickness distribution after polishing of the film to be polished from the film thickness distribution before polishing and the polishing rate distribution, a step (d) of calculating a pressure against a polishing pad for each of a plurality of regions of the film to be polished and a polishing time from the predicted film thickness distribution and the target film thickness distribution, and a step (e) of polishing while applying the pressure against the film to be polished during the polishing time.

Abstract: Concentration of electric current due to an additive (particularly, a brightener) remaining or precipitated in a high concentration at grain boundary triple points and wiring groove portions in the surface layer of a copper plating film is obviated, whereby precedent dissolution and/or abnormal dissolution due to concentration of electric current is restrained, and an electropolished surface of the copper plating film with excellent surface smoothness is obtained. A method of producing a metallic film includes the steps of: forming a metallic plating film (copper plating film (15)) by use of a plating solution prepared by adding a plating additive for restraining void generation, bottom-up fill and overfill; and electropolishing the metallic plating film by use of an electropolishing solution prepared by adding a polishing additive capable of reacting or coupling with the plating additive component contained or precipitated in the surface layer of the metallic plating film.

Abstract: Methods for forming an electronic device can include forming a capacitor structure on a portion of a substrate with the capacitor structure including a first electrode on the substrate, a capacitor dielectric on the first electrode, a second electrode on the dielectric, and a hard mask on the second electrode. More particularly, the capacitor dielectric can be between the first and second electrodes, the first electrode and the capacitor dielectric can be between the second electrode and the substrate, and the first and second electrodes and the capacitor dielectric can be between the hard mask and the substrate. An interlayer dielectric layer can be formed on the hard mask and on portions of the substrate surrounding the capacitor structure, and portions of the interlayer dielectric layer can be removed to expose the hard mask while maintaining portions of the interlayer dielectric layer on portions of the substrate surrounding the capacitor structure.

Abstract: The object of the invention is to provide a method of manufacturing a semiconductor device and a processing apparatus for planarization wherein to form copper wiring in multiple layers. The removal of a residue of polishing by local electro polishing, the enhancement of the performance of planarization by using a grindstone and the reduction by small frictional force in electro polishing of damage, are enabled. To achieve the object, the following measures are taken. A residue of polishing of copper is removed by combining the detection of a local area including the residue of polishing of copper and local processing for electro polishing. As small-load processing for planarization is enabled by using electro polishing, multilayer interconnection structure using low-k material as a dielectric interlayer is also enabled.

Abstract: In a feature layer of a semiconductor wafer, dummy tiles which overcome the tendency of dishing and erosion to occur during a CMP process are placed with various sizes and in various positions. An isolation zone is provided around active features. A scanning process of the feature layout surveys oxide density and nitride density over the wafer layer outside of said isolation zone. Values of the ratios of oxide/nitride density for two or more length scales which define tiling zones, are calculated. Tile placement and sizing in the zones is dependent upon the oxide/nitride density ratio values; and further upon an oxide deposition model specific to the oxide used in the fabrication process and upon a polishing model of the CMP process being employed.

Abstract: A method for estimating relative remaining film thickness distribution (CMP pattern ratio distribution) among sparse and dense active regions after CMP on the basis of the layout of a mask pattern in a one-chip mask region. In each mask pattern, a reduced region is created by removing an area of a predetermined width from the mask pattern along the edge of the mask pattern. Then, the one-chip mask region is segmentalized into predetermined regions to create a plurality of segmentalized regions. On each of the segmentalized regions, the area ratio of all reduced regions occupying a region that includes a segmentalized region at a fixed position and has the same size and shape as those of the foregoing one-chip mask region is acquired. Based on the acquired area ratio, the distribution of remaining film thickness of a surface protection film in the one-chip mask region, i.e., the CMP pattern ratio, is acquired.

Abstract: A method of forming contact holes. A dielectric liner is comformally formed on a substrate, parts of the dielectric liner between the second and the third conducting structure are removed, a conductive liner is conformally formed on the substrate, and parts of the metal layer are removed to leave parts thereof between the second and the third conducting structure. An ILD layer is then formed on the entire surface of the substrate, and a patterned photoresist layer is formed on the ILD layer. Finally, the ILD layer is etched using the patterned photoresist layer as a mask to form a first contact hole, a second contact hole, and a third contact hole in the ILD layer at the same time.

Abstract: In one aspect, the invention includes a method of forming a void region associated with a substrate, comprising: a) providing a substrate; b) forming a sacrificial mass over the substrate; c) subjecting the mass to hydrogen to convert a component of the mass to a volatile form; and d) volatilizing the volatile form of the component from the mass to leave a void region associated with the substrate.

Abstract: A method of removing HDP oxide deposition comprises the steps of: (1) etching the HDP oxide deposition by in-side-out model, wherein the etching rate in the center of the substrate is faster than the edges of the substrate; (2) etching the HDP oxide deposition by out-side-in model, wherein the etching rate in the edges of the substrate is faster than the center of the substrate; and (3) removing the remaining silicon oxide layer using chemical-mechanical polishing (CMP). According to the method of the invention, the HDP oxide deposition can be planarized more uniform.

Abstract: A process for planarizing a process layer having structures and has been applied to a working surface of a semiconductor device, includes abrading the process layer down to the working surface using a polishing device. The working surface is planarized, and a defect density in the working surface is minimized and the polishing process is topology-independent.

Abstract: A combination of deposition and polishing steps are used to permit improved uniformity of a film after the combination of steps. Both the deposition and polishing are performed with processes that vary across the substrate. The combination of the varying deposition and etching rates results in a film that is substantially planar after the film has been polished. In some instances, it may be easier to control the variation of one of the two processes than the other so that the more controllable process is tailored to accommodate nonuniformities introduced by the less controllable process.

Abstract: Methods and apparatus for planarizing a substrate surface are provided. In one aspect, a method is provided for planarizing a substrate surface including polishing a first conductive material to a barrier layer material, depositing a second conductive material on the first conductive material by an electrochemical deposition technique, and polishing the second conductive material and the barrier layer material to a dielectric layer. In another aspect, a processing system is provided for forming a planarized layer on a substrate, the processing system including a computer based controller configured to cause the system to polish a first conductive material to a barrier layer material, deposit a second conductive material on the first conductive material by an electrochemical deposition technique, and polish the second conductive material and the barrier layer material to a dielectric layer.

Abstract: A fabrication method for forming a semiconductor device having COB (capacitor-over-bit line) structure is provided. A lower insulating film is formed on a substrate. Bit line patterns are formed on a portion of the lower insulating film. Each of the bit line patterns comprises a conductive bit line, a lower capping strip and an upper capping strip, which are sequentially stacked. Mask-defining layer is formed on the other portion of the lower insulating film. The upper capping strips are removed by wet etching technique to form a recess region. The lower capping strips and a portion of the mask-defining layer is etched isotropically to enlarge the recess region. An insulating mask is formed in the enlarged recess region. BC (buried contact) holes are formed substantially in self-aligned manner to the bit lines by using the mask as an etch mask. According to the present invention, the unfavorable electrical contact between the storage electrodes and the bit lines can be significantly relieved.

Abstract: A process for smoothing a rough surface on a substrate, such as a diamond or silicon carbide substrate, said rough surface including protruding peak portions separated by valleys, said smoothing comprising (a) depositing a coating on said rough surface so as to adhere to and to fill at least the valleys of said rough surface, (b) mechanically polishing the thus coated rough surface so as to achieve a smooth coated surface, and (c) dry etching the smooth coated surface, such as by PACE, so as to remove the remaining coating and at least protruding peak portions of the substrate so as to achieve a smooth surface on the substrate, wherein in the mechanical polishing step (b) the coating is removed at a rate of reduction of thickness greater than the rate at which the substrate is subject to reduction of thickness by the mechanical polishing, and in the dry etching step (c) the coating and substrate are removed at substantially the same or a similar rate of reduction of thickness, and, if necessary, steps (a), (b

Abstract: There is disclosed a post-CMP treating liquid comprising water, and resin particles dispersed in the water and having a functional group at a surface thereof, or comprising water, resin particles dispersed in the water, and an additive having a functional group and incorporated in the water. The post-CMP treating liquid exhibits a polishing rate both of an insulating film and a conductive film of 10 nm/min or less.

Abstract: A polishing method able to easily flatten unevenness formed on the surface of a film to be polished and able to efficiently polish the film flat while suppressing damage to an interlayer insulating film below the film, comprising, when polishing an object having a film such as an interconnection layer formed burying interconnection grooves formed in an insulating film of a substrate, supplying a polishing solution over the surface to be polished at least substantially parallel to the surface to preferentially remove by polishing the projecting portions of the film and flatten the surface by the shear stress of the processing solution or arranging a cathode member facing the surface and supplying an electrolytic solution containing a chelating agent between the surface and cathode member while supplying voltage between the film and the cathode member to preferentially remove by polishing the projecting portions of the film and flatten the surface by the shear stress of the electrolytic solution, and a polishin

Abstract: A method for forming multiple resistors on a substrate. The method initially includes providing a first resistor on the substrate. A first dielectric layer is deposited, patterned, and selectively etched over the first resistor. Second resistor material is provided over the first dielectric layer. Furthermore, landing pad material is provided over the second resistor material. The landing pad material and the second resistor material are then selectively etched. The selective etching forms contacts for the first resistor in a first region, and forms a second resistor and associated contacts in a second region.

Abstract: A method of making a semiconductor device 10 by forming a first dielectric layer 140 on a substrate, etching through the first dielectric layer to form a trench 150 having a channel region 135 on a sidewall 160 of the trench, and laterally removing a portion of the first dielectric layer adjacent to the sidewall of the trench above the channel region for defining a source region 280 of the semiconductor device.

Abstract: Disclosed is a method for forming an isolation region in a semiconductor device. Pad oxide and nitride films are sequentially formed on a silicon substrate. Photoresist pattern is formed on the pad nitride film, the photoresist pattern. Respectively predetermined parts of the pad oxide and nitride films and the silicon substrate are etched by using the photoresist pattern as a mask to form a shallow trench. Field implant process is performed on a lower surface of the shallow trench, by using the photoresist pattern as a mask to form a field stop implant film. Photoresist pattern is removed. The inside of the shallow trench is washed. The inside of the shallow trench is thermally enlarged to form a first oxide film. Second oxide film is deposited on the first oxide film and chemical mechanical polishing process for the second oxide film is performed to form the isolation region.

Abstract: The present invention advantageously provides a substantially planarized semiconductor topography and method for making the same by forming a plurality of dummy features in a dielectric layer between a relatively wide interconnect and a series of relatively narrow interconnect. According to an embodiment, a plurality of laterally spaced dummy trenches are first etched in the dielectric layer between a relatively wide trench and a series of relatively narrow trenches. The dummy trenches, the wide trench, and the narrow trenches are filled with a conductive material, e.g., a metal. The conductive material is deposited to a level spaced above the upper surface of the dielectric layer. The surface of the conductive material is then polished to a level substantially coplanar with that of the upper surface of the dielectric layer. Advantageously, the polish rate of the conductive material above the dummy trenches and the wide and narrow trenches is substantially uniform.

Abstract: A method of forming a fuse structure in which passivating material over the fuse has a controlled, substantially uniform thickness that is provided after C4 metallurgy formation. A laser fuse deletion process for the fuse formed by this method is also disclosed.

Abstract: A method for reducing the surface roughness of a metal layer is provided. In some embodiments, the method may include depositing a fill layer upon a metal layer and subsequently polishing the fill layer. In some cases, the method may form a surface in which an upper surface of the fill layer is substantially level with at least one of the peaks associated with the surface roughness of the metal layer. In some cases, the surface may include portions of the metal layer and portions of the fill layer residing above the metal layer. In other cases, the method may include forming a surface in which the fill layer is arranged above the metal layer-fill layer interface. In either case, a semiconductor topography having a metal layer with a mean surface roughness less than the mean surface roughness obtained during the deposition of the metal layer may be obtained.

Abstract: A method of manufacturing semiconductor devices using an improved planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer using a fixed resilient flexible material member contacting the wafer.

Abstract: A substrate processing apparatus (10) has a substrate holder (12) for detachably holding a substrate (W) so that a surface, to be processed, of the substrate faces downward, and a sealing ring (18) for sealing a peripheral portion of the surface, to be processed, of the substrate (W) held by the substrate holder (12). The substrate processing apparatus (10) also has a plurality of ejection nozzles (40) disposed below the substrate holder (12) for ejecting a treatment solution toward the surface, to be processed, of the substrate (W) held by the substrate holder (12), and a mechanism for rotating and vertically moving the substrate holder (12) and the ejection nozzles (40) relative to each other.

Abstract: A method for making a bit line contact on a substrate is provided. Two gate conductor stacks are formed on a main surface of the substrate in close proximity to each other. A bit line contact forming area is defined above the area between the two gate conductor stacks. A silicon dioxide lining film is deposited on a top surface and sidewalls of the gate conductor stacks. A sacrificing layer is deposited on the silicon dioxide lining film. The sacrificing layer is then polished to expose the top surface of the gate conductor stacks. A spin-on-glass (SOG) film is then coated on the sacrificing layer. A resist pattern masking the bit line contact forming area is formed on the SOG film. The un-masked SOG film, sacrificing layer and silicon dioxide lining film are etched away. A silicon nitride thin film is deposited on the remaining SOG film. A BPSG layer is deposited on the silicon nitride thin film and is then polished to expose the SOG layer.

Abstract: A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion includes a localized non-uniformity. An additional layer is formed on the overburden portion. The additional layer and the overburden portion are planarized. The planarizing process substantially entirely removes the additional layer.

Abstract: A method of forming deep isolation trenches in the fabrication of ICs is disclosed. The substrate is prepared with deep isolation trenches. The isolation trenches are partially filled with a first dielectric material. An etch mask layer is deposited on the substrate and used to remove excess first dielectric material on the surface of the substrate. The isolation trenches are then completely filled with a second dielectric material. Excess second dielectric material is then removed from the surface of the substrate.

Abstract: A method of forming a charge storing layer is disclosed. According to an embodiment, a method may include the steps of forming a first portion of a charge storing layer with a first gas flow rate ratio (step 102), forming at least a second portion of the charge storing layer by changing to a second gas flow rate ratio that is different than the first gas flow rate ratio (step 104), and forming at least a third portion of the charge storing layer by changing to a third gas flow rate ratio that is different than the second gas flow rate ratio (step 106).

Abstract: The manufacturing method of the invention is applied to production of a semiconductor device including a memory area and a logic circuit area. The method first provides a semiconductor substrate, which has a conductive layer to make a word gate of the non-volatile memory device, a stopper layer formed above the conductive layer, and control gates formed as side walls on both side faces of the conductive layer via an ONO membrane, which are all located above a semiconductor layer in the memory area, as well as a gate electrode of an insulated gate field effect transistor formed above a semiconductor layer in the logic circuit area. The method subsequently forms an insulating layer over whole surface of the memory area and the logic circuit area on the semiconductor substrate, and carries out anisotropic etching of an upper portion in a part of the insulating layer.

Abstract: A process for selectively forming a metal barrier layer on a surface of an interconnect of a wiring substrate comprising the steps of abrading the substrate and simultaneously feeding onto the substrate a plating solution having said metal dissolved therein. The abrading step comprises contacting the substrate against an abrasive surface and causing relative linear and/or rotary motion between the abrasive surface and the substrate while the substrate is in contact with the abrasive surface. Growth of the metal barrier layer on a portion of the wiring substrate other than the interconnect layer is suppressed and the metal barrier layer thus formed is thinner, exhibits improved uniformity and superior prevention against Cu diffusion.