Abstract: A method for integrating a thin film resistor into an interconnect process flow where one of the metal layers is used as a hardmask. After a via (42) etch and fill, the thin film resistor material (62) is deposited. The metal interconnect layer (76) is then deposited, including any barrier layers desired. The metal leads (70) are then etched together with the shape of the thin film resistor (60). The metal (76) over the thin film resistor (60) is then removed.

Abstract: A method of planarizing a photoresist coating for a semiconductor device having a plurality of trenches including providing a first layer of photoresist over the plurality of trenches wherein the layer has a thickness and the photoresist is a positive-type photoresist, exposing the first layer to light having a predetermined energy, developing the exposed first layer wherein a portion of the first layer remains within the plurality of trenches, and providing a second layer of photoresist over the developed first layer.

Abstract: A semiconductor device with a multilevel interconnection has hydrogen silsesquioxane films which are made porous by etching action of hydrogen fluoride or by ion-implantation of impurities containing fluorine, as an interlayer insulating film for filling up a space between wires. Consequently, a dielectric constant of HSQ is low and wiring capacitance of the multilayer interconnection can be reduced.

Abstract: Dents are formed on the silicon oxide film 3 formed on a silicon substrate 1; thereon are formed a barrier metal film 4 and a copper plating film 5 in this order. Then, chemical mechanical polishing is conducted for planarization. Polishing is conducted for a given time and, when the barrier metal film 4 has been exposed, a hydrofluoric acid-containing solution is fed. As the hydrofluoric acid-containing solution, a buffered hydrofluoric acid or the like is used.

Abstract: A pattern is formed on a substrate by the process of providing a substrate having a surface with previously patterned features having a non-uniform electromagnetic reflectivity, applying a second image recording material to the surface, employing the features with a non-uniform physical property of reflectivity to delineate a desired pattern in the second image recording material and applying electromagnetic energy to take advantage of the reflectivity features to provide variable processing of the second material.

Abstract: A method of fabricating a preserve layer. A top metallic layer is formed over the substrate. Portions of the metallic layer and the substrate are removed to form a trench. A conformal pad oxide layer is formed over the substrate. A conformal first nitride layer is formed on the pad oxide layer. A spin-on glass layer is formed on the first nitride layer to fill the trench. An etching back step is performed to remove a portion of the spin-on glass layer. The remaining spin-on glass layer fills the trench to the surface of the first nitride layer above the top metallic layer. An oxide layer is formed over the substrate. A second nitride layer is formed on the oxide layer. A preserve layer comprising the pad oxide layer, the first nitride layer, the oxide layer, and the second nitride layer is formed.

Abstract: A method of fabricating bit lines is described. A semiconductor substrate has isolation structures formed therein. Gate structures are formed over the semiconductor substrate. Each gate structure comprises a conducting gate layer and a cap layer on the conducting gate layer. A common source and a drain is formed in the semiconductor substrate. A spacer is formed on the sidewall of each gate structure. A dielectric layer is formed over the semiconductor substrate. The dielectric layer is patterned to form bit line contact holes and bit line trenches, wherein the bit line contact holes expose the common sources, and the bit line trenches expose a part of the cap layer and a part of the isolation structures. The bit line contact holes and the bit line trenches are filled with a conducting layer; consequently, bit line contacts and patterned bit lines are formed.

Abstract: A method and apparatus is presented for planarizing or polishing workpiece surfaces using an ion beam in the presence of a radio frequency generated plasma. A workpiece is placed in a holder within a vacuum chamber equipped with a radio frequency inductive plasma generator. The workpiece surface is exposed to a source of energetic ions, the chamber is filled with gas, and the gas is ionized with radio frequency energy to form inductive plasma that surrounds the workpiece. An ion beam mounted above the workpiece scans the workpiece surface with sufficient energy to remove micro irregularities from the workpiece surface.

Abstract: A multilevel interconnecting structure includes a plurality of interconnecting layers formed on a semiconductor substrate, a fluorine-doped oxide film for burying portions between the interconnecting layers, and an oxide film formed on the fluorine-doped oxide film, having a planarized surface, and not containing fluorine. A method of forming the multilevel interconnecting structure is also disclosed.

Abstract: In the semiconductor wafer manufacturing method of the present invention, a deteriorated layer on the surface of a semiconductor wafer which has been made flat by lapping or polishing is removed by the following dry etching. Plasma which contains a neutral active species is generated within a discharge tube. The neutral active species is separated from the plasma thus generated and is then conveyed to an orifice side of a nozzle portion of the discharge tube. The orifice is opposed to the wafer surface and the nozzle portion moves along the wafer surface while the neutral active species is sprayed from the nozzle orifice toward the wafer surface which is pre-heated. By such dry etching, the deteriorated layer on the wafer surface is removed without the occurrence of any etch pit.

Abstract: The invention provides a method of planarizing an irregular surface of a semiconductor wafer. In one embodiment, the method comprises applying a photoresist material over recessed areas and protruding areas of the irregular surface, etching the photoresist, etching partially into protruding areas of the irregular surface to remove a portion of the irregular surface, and polishing the irregular surface to a substantially planar surface. In some embodiments method may include chemically and mechanically polishing the irregular surface.

Abstract: A wafer flattening process and system enables a reduction of the surface roughness of a wafer resulting from local etching. A silicon wafer W is brought into close proximity to a nozzle portion 20 to feed SF6 gas to an alumina discharge tube 2, a plasma generator 1 is used to cause plasma discharge and spray a first activated species gas from the nozzle portion 20 to the silicon wafer W side, an X-Y drive mechanism 4 is used to make the nozzle portion 20 scan to perform a local etching step. Then the silicon wafer W is moved away from the nozzle portion 20 and O2 gas and CF4 gas are fed to the alumina discharge tube. At this time, the O2 gas is set to be greater in amount than the CF4 gas. When this mixed gas is made to discharge to generate plasma, a second activated species gas diffuses from the nozzle portion 20 to the entire surface of the silicon wafer W.

Abstract: A semiconductor manufacturing method is disclosed, which includes the steps of: forming an interconnect layer, which may include aluminum, on a semiconductor substrate; forming an anti-reflective coating which may comprise titanium; forming a spin on glass layer; selectively etching portions of the spin on glass layer, so that predetermined portions of the interconnect layer are exposed; and applying an EKC solution to predetermined portions of the interconnect layer that are exposed. The semiconductor manufacturing may also include the steps of forming a first tetra-ethyl-ortho-silicate layer, before the step of forming a spin on glass layer; and forming a second tetra-ethyl-ortho-silicate layer, following the step of applying an EKC solution. The EKC solution in the preferred embodiment is applied for at least about a 10 minute process time. Furthermore, the semiconductor manufacturing method may include the step of forming a second interconnect layer.

Abstract: A method for planarizing a semiconductor wafer. An insulation layer is formed over the wafer. A spin-on-glass layer is coated over the insulation layer. Subsequently, the spin-on-glass layer is baked to smooth out its upper surface. A chemical-mechanical polishing process is carried out to planarize the insulation layer. The method eliminates recess cavities in the more loosely packed device region of the insulation layer after a planarization process.

Abstract: A method for making a planar interlevel dielectric (ILD) layer, having improved thickness uniforming across the substrate surface, over a patterned electrically conducting layer is achieved. The method involves forming electrically conducting lines on which is deposited a conformal first insulating layer that is uniformly thick across the substrate. An etch-stop composed of Si3N4 is deposited and a second insulating layer, composed of SiO2 or a low-dielectric-constant insulator, is deposited. The second insulating layer is then partially chemically/mechanically polished back to within a few thousand Angstroms of the etch-stop layer. The remaining second insulating layer is then plasma etched back selectively to the etch-stop layer to form a planar surface having a uniformly thick first insulating layer over the electrically conducting lines. The contact openings or via holes can now etched to a uniform depth in the etch-stop layer and the first insulating layer across the substrate.

Abstract: Methods of oxidizing the surface of a photoresist material on a semiconductor substrate to alter the photoresist material surface to be substantially hydrophillic. Oxidation of the photoresist material surface substantially reduces or eliminates stiction between a planarizing pad and the photoresist material surface during chemical mechanical planarization. This oxidation of the photoresist material may be achieved by oxygen plasma etching or ashing, by immersing the semiconductor substrate in a bath containing an oxidizing agent, or by the addition an oxidizing agent to the chemical slurry used during planarization of the resist material.

Abstract: A method for planarizing a layer of photoresist on a substrate. The layer of photoresist is exposed to wavelengths of radiation that the photoresist is sensitive to. The radiation is directed at the layer of photoresist at an oblique angle with respect to a major dimension of the layer of photoresist. The photoresist is developed.

Abstract: In modern sub-micron technologies with aggressive design rules, it is not always possible to have complete overlap of conductive lines with underlying vias. A process for manufacturing a semiconductor device having metal interconnects reduces or eliminates the recessing of metal in the vias, particularly when the metal in the vias is aluminum or an aluminum alloy. By manipulating the etch chemistry so that the etch rates of the aluminum alloy, the surrounding barrier metals, and the dielectric are comparable, it is possible to perform the metal over etch without forming voids in the exposed portion of the via. By eliminating the voids, thinning of the vias due to the presence of recesses is minimized, and electrical connections are less susceptible to electromigration. Consequently, device yield and reliability are increased.

Abstract: A contact structure between two conductors in a semiconductor device and a method for fabricating the same which can increase alignment margins between the contact plug and overlying conductor are provided. The contact plug includes a lower conductor formed on a semiconductor substrate, an insulating layer formed on the lower conductor and on the semiconductor substrate, the insulating layer having a contact hole, a contact plug recess a predetermined depth from a top surface of the insulating layer in the contact hole, and a sidewall spacer formed on both lateral sidewalls of remainder of the contact hole. The contact plug structure is made by a process of forming a recessed contact plug in the contact hole formed in an insulating layer. Sidewall spacer is formed on both sidewalls of the remainder of the contact hole that has low aspect ratio as compared to that of the contact hole prior to the formation of the recessed contact plug.

Abstract: Transient voltage suppressor semiconductor devices and other semiconductor devices having rigorous requirements for the diffusion and depth of impurities to produce P-N junctions can be fabricated at surprisingly low costs without sacrifice of functional characteristics by subjecting the substrate to a grinding process resulting in a surface short of polishing perfection, thereby to eliminate the time-consuming and hence costly conventional polishing operation, and then diffusing the desired impurity into the substrate from a solid impurity source.

Abstract: A method for insulating metal conductors by spin-on-glass in inter-metal dielectric layers and devices formed by such method are disclosed. In the method, an additional step of scrubber clean is incorporated after an etch-back process on the spin-on-glass layer is conducted. Contaminating metal ions such as those of calcium is thus removed to eliminate formation of voids by such particles. The method can be easily implemented by including the additional scrubber clean step into a total wafer fabrication recipe.

Abstract: The present invention relates to a method for removing a first dielectric layer of a semiconductor wafer. The first dielectric layer is formed on the surface of a second dielectric layer of the semiconductor wafer. The method comprises performing a chemical mechanical polishing (CMP) process on the first dielectric layer to remove a predetermined thickness of the first dielectric layer, measuring the remaining thickness of the first dielectric layer, providing an etching table having a plurality of thickness ranges of the remaining first dielectric layer and corresponding etching back procedure or parameters of each of the thickness ranges, and performing an etching back process to horizontally remove the remaining first dielectric layer according to the etching back procedure or parameters of the thickness range corresponding to the measured thickness of the remaining first dielectric layer.

Abstract: A method for forming a microelectronic layer within a microelectronic fabrication first employs a substrate. There is then formed over the substrate a target microelectronic layer. There is then formed upon the target microelectronic layer a sacrificial smoothing layer. Finally, there is then etched the sacrificial smoothing layer completely from the target microelectronic layer while partially etching the target microelectronic layer to form a partially etched target microelectronic layer with an enhanced surface smoothness in comparison with the target microelectronic layer.

Abstract: A method of manufacturing an inter-metal level dielectric layer for a semiconductor device. The method includes forming spaced conductive lines. Next, a first conformal silicon oxide film (barrier layer) is formed over the spaced conductive lines. Gaps or valleys are between the metal lines covered by the barrier layer. A novel first “gap filling” spin-on-glass layer is formed over the first silicon oxide layer. In a critical step, the first SOG layer is heated to reflow thereby flowing all the first spin-on-glass layer from over the metal lines and leaving all of the first SOG layer in the gaps. Subsequently, a second silicon oxide layer is deposited over the first silicon oxide layer and over the first spin-on-glass layer only in the gaps. A second spin-on-glass layer is then formed over the second silicon oxide layer. An etchback is performed by etching back and removing the entire second spin on glass layer and portions the second silicon oxide layer.

Abstract: The practice of forming self-aligned contacts (SACs) in MOSFETs using a silicon nitride gate sidewall and a silicon nitride gate cap has found wide acceptance, particularly in the manufacture of DRAMs, where bitline contacts are formed between two adjacent wordlines, each having a nitride sidewall. The contact etch requires a an RIE etch having a high oxide/nitride selectivity. In order to etch SACs having widths of less than 0.35 microns at their base, such as are encountered in high density DRAMs, special steps must be taken to prevent polymer bridging across the opening which leaves residual insulative material at the base of the contact. The problem is further complicated when the insulative layer through which the opening is formed comprises a silicate glass such as BPSG over a silicon oxide layer.

Abstract: A method for fabricating an interlayer dielectric layer on a semiconductor substrate with a memory cell region and a periphery circuit region is described, wherein semiconductor devices are formed on the memory cell region and the periphery circuit region so as to result in a height variation therebetween. The present method comprises the steps of forming a first dielectric layer blanket-covering the semiconductor substrate, wherein a first height variation exists between the memory cell region and the periphery circuit region. Then, a stop layer is conformally blanket formed on the first dielectric layer. Next, a second dielectric layer is conformally formed on the stop layer. A chemical mechanical polishing process is executed on the second dielectric layer until the stop layer on the memory cell region is exposed. This formation of the structure of a first dielectric layer/stop layer/second dielectric layer is repeated at least two times to achieve a planarized interlayer dielectric layer.

Abstract: A method for marking a semiconductor wafer without inducing flat edge particles, using a laser scribing technique. The process begins by providing a semiconductor wafer having a marking area with a silicon top layer. The semiconductor wafer is coated with a photoresist layer. A volume of the photoresist layer and a volume of silicon top layer are removed corresponding to the intended marking. Optionally, the marking pattern can be further etched into the silicon top layer by anisotropic etching, using the photoresist layer as an etching mask. In another option, the laser scribing process can be set to scribe the marking pattern in the photoresist layer without scribing the silicon top layer. The marking pattern can then be anisotropically etched into the silicon top layer, using the photoresist layer as an etching mask. Alternatively, the photoresist layer can be patterned to form an opening in the photoresist layer over a marking area, thereby exposing the silicon top layer.

Abstract: The present invention advantageously provides a substantially planarized semiconductor topography and method for making the same by forming a plurality of dummy features in a dielectric layer between a relatively wide interconnect and a series of relatively narrow interconnect. According to an embodiment, a plurality of laterally spaced dummy trenches are first etched in the dielectric layer between a relatively wide trench and a series of relatively narrow trenches. The dummy trenches, the wide trench, and the narrow trenches are filled with a conductive material, e.g., a metal. The conductive material is deposited to a level spaced above the upper surface of the dielectric layer. The surface of the conductive material is then polished to a level substantially coplanar with that of the upper surface of the dielectric layer. Advantageously, the polish rate of the conductive material above the dummy trenches and the wide and narrow trenches is substantially uniform.

Abstract: A method for removing a surface defect from a dielectric layer during the formation of a semiconductor device comprises the steps of forming a dielectric layer having a hole therein, the dielectric also having a surface defect resulting from a previous manufacturing step such as chemical mechanical polish, contact with another surface during production, or from a manufacturing defect. A blanket conductive layer is then formed within the hole, within the surface defect, and over the dielectric layer. The conductive layer is etched from the surface of the dielectric using an etch which removes the conductive layer at a substantially faster rate than it removes the dielectric. This etch is stopped when the level of conductive material in the plug is flush with the upper surface of the dielectric. Next, the conductive and dielectric layers are etched using a dry or plasma etch which removes the conductive and dielectric layers at about the same rate.

Abstract: A new method for planarizing silicon dioxide surfaces in semiconductor structures. Starting with a structure of an underlying layer (for instance a layer of metal lines) a layer of oxide is deposited and profiled by positive tone imaging. A layer of PPMS is deposited. Using the mask of the starting structure, the PPMS layer is exposed changing the PPMS to PPMSO in the exposed regions. The unexposed PPMS is removed, the PPMSO (unexposed regions of the PPMS) are planarized, this planarization can proceed to the point where no more PPMSO is present (the PPMSO “columns” are removed together with the intra-layer of patterned oxide). The surface thus created shows excellent planarity, this surface can be further planarized down to the top level of the underlying pattern, if it is desirable to do so.

Abstract: A method for planarizing a semiconductor substrate uses a difference in etch selectivity of insulators on the semiconductor substrate. The method comprises the steps of wet-etching the second and first insulating layers at upper edges of the elevated region until portions of the first insulating layer are exposed at the upper edges, forming a third insulating layer on the first and second insulating layers, and wet-etching the third and second insulating layers until an upper surface of the first insulating layer is exposed. During the wet-etching, the second insulating layer is etched faster than the third insulating layer. With this method, the semiconductor substrate has an even surface.

Abstract: Methods of oxidizing the surface of a photoresist material on a semiconductor substrate to alter the photoresist material surface to be substantially hydrophillic. Oxidation of the photoresist material surface substantially reduces or eliminates stiction between a planarizing pad and the photoresist material surface during chemical mechanical planarization. This oxidation of the photoresist material may be achieved by oxygen plasma etching or ashing, by immersing the semiconductor substrate in a bath containing an oxidizing agent, or by the addition of an oxidizing agent to the chemical slurry used during planarization of the resist material.

Abstract: A new method of forming shallow trench isolations has been achieved. A semiconductor substrate is provided. A first etch stop layer is deposited. The first etch stop layer and the semiconductor substrate are etched to form trenches. A gap fill layer of high density plasma oxide is deposited overlying the first etch stop layer and filling the trenches. The deposition of the gap fill layer is stopped before the planar top surface of the gap fill layer overlying the trenches reaches the level of the top surface of the first etch stop layer bordering the trenches. The gap fill layer is etched so that the gap fill layer overlying the trenches does not contact the gap fill layer overlying the first etch stop layer. A second etch stop layer is deposited. The deposition of the second etch stop layer is stopped before the planar top surface of the second etch stop layer overlying the trenches reaches the level of the top surface of the first etch stop layer.

Abstract: Disclosed is a MOS transistor having a polysilicon gate structure in which an overlying metal interconnect completely shorts the gate area. In one embodiment, the gate is formed from multiple fingers joined in a serpentine pattern and separated by oxide-filled spaces. Overlying the fingers and oxide-filled spaces is an interconnect comprising a first metal layer and a second metal layer. The first metal layer overlies the fingers and oxide-filled spaces and the second metal layer overlies the first metal layer. Both metal layers form a stack that simultaneously shorts the fingers. Also disclosed is a method of fabricating such a polysilicon gate structure in a MOS transistor using a series of masks. Once the gate and fingers are defined, a conformal oxide is deposited over the fingers and in the spaces between the fingers. The conformal oxide is anisotropically etched to produce a planarized profile of the fingers and oxide-filled spaces.

Abstract: A method to reduce the effective recess in conductive plugs 220 by performing an oxide etch or oxide CMP, selective to the conductive material in question. This method can be used for any conductive plug 220 (e.g. aluminum, tungsten, copper, titanium nitride, etc.). In addition, this method is also applicable in contact, via, and trench (damascene) applications. Furthermore, this process can advantageously be used in logic, SRAM, and DRAM applications.

Abstract: A semiconductor manufacturing process with improved gap fill capabilities is provided by a three step process of FSG deposition/etchback/FSG deposition. A first layer of FSG is partially deposited over a metal layer. An argon sputter etchback step is then carried out to etch out excess deposition material. Finally, a second layer of FSG is deposited to complete the gap fill process.

Abstract: Methods, apparatuses and substrate assembly structures for mechanical and chemical-mechanical planarizing processes used in the manufacturing microelectronic-device substrate assemblies. One aspect of the invention is directed toward a method for planarizing a microelectronic-device substrate assembly by removing material from a surface of the substrate assembly, detecting a first change in drag force between the substrate assembly and a polishing pad indicating that the substrate surface is planar, and identifying a second change in drag force between the substrate assembly and the polishing pad indicating that the planar substrate surface is at the endpoint elevation. After the second change in drag force is identified, the planarization process is stopped.

Abstract: A surface treatment method for use in integrated circuit fabrication includes providing a substrate assembly having a surface. A liquid is provided adjacent the surface resulting in an interface therebetween. An electrical potential difference is applied across the interface and the surface is treated as the electrical potential difference is applied across the interface. The liquid may be a planarization liquid when the treatment of the surface includes planarizing a substrate assembly or the liquid may be a coating material when the treatment of the surface includes applying a coating material on the surface.

Abstract: A planarization method is disclosed to provide improved protection against cracking of the final passivation layer of integrated circuit devices. In one embodiment, such method includes final passivation of an integrated circuit device including at least one integrated circuit chip. Such final passivation includes the step of forming a layer of protective material over a top surface of the integrated circuit chip, and a subsequent step of planarizing such layer of protective material to obtain a protection layer having a substantially flat top surface.

Abstract: In a semiconductor integrated circuit wherein an interlayer insulating film is formed over a semiconductor substrate having a semiconductor device formed thereover; and an interconnection embedded in an interconnection groove in the interlayer insulating film is formed by the deposition of a metal film such as copper and polishing by the CMP method, another interlayer insulating film over the interconnection and interlayer insulating film is formed to have a blocking film, a planarizing film and an insulating film. As the planarizing film, a film having fluidity such as SOG is employed.

Abstract: The invention relates to a process for making an integrated circuit device comprising (i) a substrate, (ii) metallic circuit lines positioned on the substrate, and (iii) a dielectric material positioned on the circuit lines. The dielectric material comprises the condensation product of silsesquioxane in the presence of a photosensitive or thermally sensitive base generator.

Abstract: A method for planarizing DRAM cells comprising the steps of providing a silicon substrate having a field oxide layer, an oxide layer and a capacitor formed thereon, then forming a first dielectric layer over the substrate. Next, portions of the first dielectric layer is etched back to form a spacer layer, and then a second dielectric layer is formed over the spacer layer. Thereafter, an insulating layer is formed over the second dielectric layer. Finally, the insulating layer is fully etched back to form a third dielectric layer.

Abstract: Methods of forming field effect transistors include the steps of forming an insulated gate electrode on a face of a substrate containing a semiconductor region therein extending to the face. A conductive layer of first conductivity type is also formed on the face and on a sidewall and upper surface of the insulated gate electrode. Dopants of first conductivity type are then diffused from the conductive layer into the semiconductor region to define source and drain regions of first conductivity type therein which are self-aligned to the insulated gate electrode. A step is also performed to remove a portion of the conductive layer to thereby define an intermediate source/drain contact (which is also self-aligned to the insulated gate electrode) and expose the upper surface of the insulated gate electrode. An electrode is then formed in contact with the intermediate source/drain contact.

Abstract: A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.

Abstract: In a patterning of a gate electrode by an optical lithography, a narrowing of a pattern and a change in sizes are prevented at a step of a polycrystalline silicon. A silicon nitride 17 is formed, as an impact-absorbing film, on a polycrystalline silicon 16 to be the gate electrode. The silicon nitride 17 is leveled by a chemical mechanical polishing method. A resist 18 is then applied. The optical lithography is performed. The resist 18 is used as a mask so that the polycrystalline silicon 16 is anisotropic etched to form a gate electrode.

Abstract: The process includes the following steps. At first, a masking layer is formed over the semiconductor substrate. A portion of the masking layer is then removed to form an opening to the semiconductor substrate. Sidewall spacers are formed on the opening and a portion of the semiconductor substrate is removed to form a trench, through an aperture defined by the sidewall spacers. The sidewall spacers is then removed and a liner layer is formed conformably over the trench.

Abstract: A process for the formation and planarization of polymeric dielectric films on semiconductor substrates and for achieving high chemical mechanical polish removal rates when planarizing these films. A cured, globally planarized, polymeric dielectric thin film is produced on a semiconductor substrate by (a) depositing a polymeric, dielectric film composition onto a surface of a semiconductor substrate; (b) partially curing the deposited film; (c) performing a chemical mechanical polishing step to said partially cured dielectric film, until said dielectric film is substantially planarized; and (d) subjecting the polished film to an additional curing step. Preferred dielectric films are polyarylene ether and/or fluorinated polyarylene ether polymers which are deposited by a spin coating process onto a semiconductor substrate. A thermal treatment partially cures the polymer. A chemical mechanical polishing step achieves global planarization. Another thermal treatment accomplishes a final cure of the polymer.

Abstract: A method for fabricating a dual damascene structure is provided. The method contains providing a substrate, which has a patterned metal layer on it. A first liner oxide layer, a first seed layer are sequentially formed over the substrate. The first seed layer is patterned to form a first opening above the patterned metal layer to expose the first liner oxide layer. A first dielectric layer is formed over the substrate. The first dielectric layer includes a first porous dielectric layer on the first seed layer, and a first normal dielectric layer on the exposed portion of the first liner oxide layer. A first cap layer is formed over the first dielectric layer, and is planarized. An etching stop layer with a second opening above the first opening to expose the first cap layer is formed on the first cap layer.

Abstract: A method of fabricating kink-effect-free shallow trench isolations is presented in this invention. First, a layer of silicon oxide and a layer of polysilican are sequentially deposited on a substrate, and then shallow trenches are formed, next thermal oxidation is performed to grow a passivation oxide layer on the exposed silicon, and then, a dielectric layer is formed to fill into the shallow trench. Finally, the dielectric layer on the active area is removed by using chemical mechanical polishing and the polysilicon layer provides for the etching end point. The level of shallow trench is higher than the level of active area as soon as stop polishing, because the polysilicon layer is polished faster than dielectric layer. It provides the passivation oxide on the sidewall of shallow trench to form spacers of the active area after removing the polysilicon of active area. It can provide a perfect shallow trench after an oxidation and etching process to avoid the kink effect.

Abstract: A method of manufacturing a semiconductor integrated circuit wherein a patterned wafer polishing machine for uniformly polishing a surface by chemical mechanical polishing is utilized which is provided with a head for holding a wafer and rubbing it on an abrasive surface. A pressure plate provided with vents is held by the head body which is provided with a gas inlet and an elastic film for sealing vents is provided on the end face on the side reverse to the gas inlet side of the pressure plate. A patterned wafer is held by the head as the wafer, pressed by action of the pressure of air from the gas inlet via the elastic film is pressed mechanically by the pressure plate. The polishing surface which is a principal plane on the patterned side of the wafer is mechanochemically polished by the abrasive surface.