Abstract: To provide a method of manufacturing a nano structure having a pattern of 2 ?m or more in depth formed on the surface of a substrate containing Si and a nano structure having a pattern of a high aspect and nano order. A nano structure having a pattern of 2 ?m or more in depth formed on the surface of a substrate containing Si, wherein the nano structure is configured to contain Ga or In on the surface of the pattern, and has the maximum value of the concentration of the Ga or the In positioned within 50 nm of the surface of the pattern in the depth direction of the substrate. Further, its manufacturing method is configured such that the surface of the substrate containing Si is irradiated with a focused Ga ion or In ion beam, and the Ga ions or the In ions are injected, while sputtering away the surface of the substrate, and a layer containing Ga or In is formed on the surface of the substrate, and with this layer taken as an etching mask, a dry etching is performed.

Abstract: Multi-step selective etching. Etching an unmasked region associated with each layer of a plurality of layers, the plurality of layers comprising a stack, wherein the unmasked region of each of the plurality of layers is etched while exposed to a temperature, a pressure, a vacuum, using a plurality of etchants, wherein at least one of the plurality of etchants comprises an inert gas and oxygen, wherein the etchant oxidizes the at least one layer that can be oxidized such that the etching stops, the plurality of etchants leaving substantially unaffected a masked region associated with each layer of the plurality of layers, wherein two or more of the plurality of layers comprises a memory stack, and preventing corrosion of at least one of the plurality of layers comprising a conductive metal oxide by supplying oxygen to the stack after etching the unmasked region without breaking the vacuum.

Abstract: Provided is a method for forming a gate electrode of a semiconductor device which can form a gate electrode having a fine line width. Disclosed method steps include forming a gate oxide film, a polysilicon film for a gate electrode, and a first sacrificial layer on the entire surface of a semiconductor substrate and then forming an opening within the first sacrificial layer. The effective width of the hole is reduced, and an ion implantation layer is formed on the top surface of the polysilicon film in the region exposed through the hole. A gate electrode is formed under the ion implantation layer by using the ion implantation layer as a mask.

Abstract: A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided.

Abstract: This invention provides a pattern reversal process for self aligned imprint lithography (SAIL). The method includes providing a substrate and depositing at least one layer of material upon the substrate. A pattern is then established upon the layer of material, the pattern providing at least one exposed area and at least one covered area of the layer of material. The exposed areas are treated to toughen the material and reverse the pattern. Subsequent etching removes the un-toughened material. A thin-film transistor device provided by the pattern reversal process is also provided.

Abstract: A transistor assembly with semiconductor material vertically introduced into micro holes (4) in a pliable a film laminate consisting of two plastic films (1, 3) with a metal layer (2) located therebetween. Said semiconductor material is provided with contacts (6, 7) by metalizing the top side and bottom side of the film laminate. The assembly is very strong by virtue of the fact that the film can be bent and stretched.

Abstract: A method of forming a TEOS oxide layer over an nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer formed on a substrate. The method includes forming the nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer on a top surface and a top side beveled edge proximate to the top surface of a substrate; removing or preventing formation of a carbon-rich layer on a bottom side bevel edge region proximate to a bottom surface of the substrate or converting the carbon-rich layer to nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide; and forming the TEOS oxide layer on the top surface, the top side beveled edge and the bottom side bevel edge region of the substrate.

Abstract: A semiconductor fabrication method. The method includes providing a semiconductor structure which includes (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, and (iii) a gate electrode region on the gate dielectric layer. The gate dielectric layer is sandwiched between and electrically insulates the semiconductor layer and the gate electrode region. The semiconductor layer and the gate dielectric layer share a common interfacing surface which defines a reference direction perpendicular to the common interfacing surface and pointing from the semiconductor layer to the gate dielectric layer. Next, a resist layer is formed on the gate dielectric layer and the gate electrode region. Next, a cap portion of the resist layer directly above the gate electrode region in the reference direction is removed without removing any portion of the resist layer not directly above the gate electrode region in the reference direction.

Abstract: A method of fabricating a stacked structure for forming a damascene process is described. A doped dielectric layer is formed on a substrate. A surface treatment is performed to the dielectric layer to make the dopant concentration in an upper surface layer of the dielectric layer lower than that in the other portions of the dielectric layer. A metal hard mask is then formed on the dielectric layer. Since the dopant conc. in the upper surface layer of the dielectric layer is lowered, the reaction between the metal hard mask and the dopant in the dielectric layer can be inhibited.

Abstract: Disclosed is a method of forming a bottle shaped trench in a substrate which includes forming at least one trench having an upper portion and a lower portion into a semiconductor substrate, the at least one trench having vertical sidewalls that extend to a common bottom wall; implanting ions into the semiconductor substrate abutting the upper portion of the at least one trench to form an amorphous region in the semiconductor substrate abutting the upper portion of the at least one trench; and etching the lower portion of the at least one trench selective to the amorphous region to provide an elongated bottom portion which extends laterally beyond the upper portion.

Abstract: A method of forming a pattern of a semiconductor device comprises forming a first hard mask film, a first resist film, and a second hard mask film over an underlying layer of a semiconductor substrate; forming a second resist pattern over the second hard mask film; etching the second hard mask film using the second resist pattern as an etching mask to form a second hard mask pattern; performing an ion-implanting process on the first resist film with the second hard mask pattern as an ion implanting mask to form an ion implanting layer in a portion of the first resist film, and selectively etching the first resist film with the second hard mask pattern and an ion implanting layer as an etching mask to form a first resist pattern.

Abstract: A method for manufacturing a semiconductor device includes forming a hard mask pattern and a spacer at both sides of the hard mask pattern. The method also includes forming a spacer pattern, so that the spacer remains in one direction to form a spacer pattern, forming a photoresist pattern having a pad type overlapping a side of the spacer pattern, and etching an underlying layer, with the photoresist pattern and the spacer pattern as a mask, to form an isolated pattern. The method improves resolution and process margins to obtain a highly-integrated transistor.

Abstract: A contact is defined by an opening etched into borophosphosilicate glass (BPSG) down to a silicon substrate. In a contact cleaning process designed to remove native oxide at the bottom of the contact with little effect on the BPSG, the contact is dipped in an etch retardant before being dipped in a cleaning solution containing both the etch retardant and an etchant. The dip in etch retardant modifies the surface of the BPSG, thereby lessening the enhanced etching experienced during the initiation of the dip into the etchant/etch retardant cleaning solution. Results of a etchant/etch retardant clean, both with and without the prepassivation, can be illustrated on a graph depicting the change in contact diameter as a function of dip time. Specifically, the results define “best fit” lines on that graph.

Abstract: Methods of forming a magnetic memory device include oxidizing a top magnetic layer using a conductive capping pattern as a mask. An etch selectivity between an oxidized portion of the top magnetic layer and a tunnel barrier layer may be relatively high. Using the tunnel barrier layer as an etch-stop layer, the oxidized portion of the top magnetic layer is selectively removed to form a top magnetic pattern, and to expose at least a portion of opposite sidewalls of the top magnetic pattern and the tunnel barrier layer. The unoxidized portion of the top magnetic layer forms a top magnetic pattern.

Abstract: A semiconductor device comprising a gate structure on a semiconductor substrate and a recessed-region in the semiconductor substrate. The recessed-region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure.

Abstract: Methods of manufacturing a semiconductor device, apparatus and etch chamber for the manufacturing of semiconductor devices are provided. Embodiments are related to the rotating of a semiconductor substrate round an axis perpendicular to its surface during etching or reactive deposition processes, and irradiating a semiconductor substrate non-uniformly during etching or reactive deposition processes.

Abstract: A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.

Abstract: The invention provides a method for producing a quartz glass jig for use in semiconductor industries, which enables increasing the surface layer cleanliness simply and surely at low cost; it also provides a quartz glass jig improved in surface layer cleanliness. The inventive means for resolution are a method comprising processing a quartz glass raw material into a desired shape by a treatment inclusive of fire working, annealing for stress removal, and cleaning treatment to obtain the final product, the method is characterized by that it comprises performing gas phase etching step and gas phase purification step on the surface layer of the quartz glass jig after applying the annealing treatment for stress removal but before the cleaning treatment, wherein the gas phase purification step is carried out continuously after the gas phase etching step.

Abstract: A high K layer, such as aluminum oxide or hafnium oxide, may be formed with a deposition process that uses an ion implantation to damage portions of the high K material that are to be later etched. More particularly, in one implementation, a semiconductor device is manufactured by forming a first dielectric over a substrate, forming a charge storage element over the first dielectric, forming a second dielectric above the charge storage element, implantation ions into select portions of the second dielectric, and etching the ion implanted select portions of the second dielectric.

Abstract: A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to the range of implantation-induced damage. By using the ion implantation, the variation in vertical etch depth can be reduced by a factor approximately equal to the etch rate of the damaged material divided by the etch rate of the undamaged material. The vertical etch depth can be used to provide a vertical dimension of a non-planar semiconductor device. Minimizing vertical device dimension variations on a wafer can reduce device and circuit performance variations, which is highly desirable.

Abstract: A method of etching semiconductor structures is disclosed. The method may include etching an SRAM portion of a semiconductor device, the method comprising: providing a silicon substrate layer, a nitride layer thereover, an optical dispersive layer over the nitride layer, and a silicon anti-reflective coating layer thereover; etching the silicon anti-reflective coating layer using an image layer; removing the image layer; etching the optical dispersive layer while removing the silicon anti-reflective coating layer; etching the optical dispersive layer and the nitride layer simultaneously; and etching the optical dispersive layer, the nitride layer, and the silicon substrate simultaneously.

Abstract: A semiconductor substrate includes: a first semiconductor layer; an oxide layer that is formed on the first semiconductor layer; a second semiconductor layer that is formed on the oxide layer; a first recess that is formed in the second semiconductor layer with extending from an upper face of the second semiconductor layer toward the first semiconductor layer, the first recess being formed at a position where an alignment mark for determining a forming position of an element which is to be built in the semiconductor substrate is to be formed; and an etching prevention layer that is inwardly formed from a position of an upper face of the first semiconductor layer, the position corresponding to the recess, the layer comprising a material that is prevented from being etched during etching of the first semiconductor layer.

Abstract: A method for forming a semiconductor device on a substrate having a first major surface lying in a plane and the semiconductor device are disclosed. In one aspect, the method comprises, after patterning the substrate to form at least one structure extending from the substrate in a direction substantially perpendicular to a major surface of the substrate, forming locally modified regions at locations in the substrate not covered by the structure, thus locally increasing etching resistance of these regions. Forming locally modified regions may prevent under-etching of the structure during further process steps in the formation of the semiconductor device.

Abstract: A method for selectively removing nano-crystals on an insulating layer. The method includes providing an insulating layer with nano-crystals thereon; exposing the nano-crystals to a high density plasma comprising a source of free radical chlorine, ionic chlorine, or both to modify the nano-crystals; and removing the modified nano-crystals with a wet etchant.

Abstract: A method for the plasma-free etching of silicon using the etching gas ClF3 or XeF2 and its use are provided. The silicon is provided having one or more areas to be etched as a layer on the substrate or as the substrate material itself. The silicon is converted into the mixed semiconductor SiGe by introducing germanium and is etched by supplying the etching gas ClF3 or XeF2. The introduction of germanium and the supply of the etching gas ClF3 or XeF2 may be performed at the same time or alternatingly. In particular, it is provided that the introduction of germanium be performed by implanting germanium ions in silicon.

Abstract: A semiconductor device comprises a semiconductor layer including a plurality of paralleled linear straight sections extending in a first direction. The layer also includes a plurality of connecting sections each having a width in the first direction sufficient to form a wire-connectable contact therein and arranged to connect between adjacent ones of the straight sections in a second direction. The connecting sections have respective ends formed aligned with a first straight line parallel to the second direction.

Abstract: An improved solution for producing nitride-based heterostructure(s), heterostructure device(s), integrated circuit(s) and/or Micro-Electro-Mechanical System(s) is provided. A nitride-based etch stop layer that includes Indium (In) is included in a heterostructure. An adjacent layer of the heterostructure is selectively etched to expose at least a portion of the etch stop layer. The etch stop layer also can be selectively etched. In one embodiment, the adjacent layer can be etched using reactive ion etching (RIE) and the etch stop layer is selectively etched using a wet chemical etch. In any event, the selectively etched area can be used to generate a contact or the like for a device.

Abstract: One embodiment of the present invention relates to a method of processing a semiconductor device. During the method an amorphization implant is performed to amorphize a selected region of a semiconductor structure. The amorphized selected region is then removed by performing a recess etch that is selective thereto. Other methods and systems are also disclosed.

Abstract: Replacement metal gates may be formed by removing a polysilicon layer from a gate structure. The gate structure may be formed by patterning the polysilicon layer and depositing a spacer layer over the gate structure such that the spacer layer has a first polish rate. The spacer layer is then etched to form a sidewall spacer. An interlayer dielectric is applied over the gate structure with the sidewall spacer. The interlayer dielectric has a second polish rate higher than the first polish rate. A hard mask may also be applied over the gate structure and implanted so that the hard mask may be more readily removed.

Abstract: A porous dielectric layer is formed on a substrate. Aluminum is incorporated in the porous dielectric layer with a pattern process using an Aluminum gas precursor. The incorporated Aluminum improves the mechanical properties of the porous dielectric layer.

Abstract: A method using an etchant and a laser for localized precise heating enables precise etching and release of MEMS devices with improved process control while expanding the number of materials used to make MEMS, including silicon-dioxide patterned films buried in and subsequently released from bulk silicon, as a direct write method of release of patterned structures that enables removal of only that material needed to allow the device to perform to be precisely released, after which, the bulk material can be further processed for additional electrical or packaging functions.

Abstract: A method for fabricating a semiconductor device with a borderless via/wiring structure includes the steps of performing borderless via etching using a resist mask to form a contact hole in an interlevel dielectric layer over a semiconductor substrate so as to expose two different metal materials of lower layer patterns in the contact hole; and performing plasma irradiation using an H2O-containing gas prior to a wet process when removing the resist mask.

Abstract: A method of fabricating a semiconductor device includes the steps of modifying a damaged layer containing carbon and formed at a semiconductor surface by exposing the damaged layer to oxygen radicals to form a modified layer, and removing the modified layer by a wet etching process, wherein the modifying step is conducted by adding an active specie of an element that would obstruct formation of double bond between a Si atom and an oxygen atom by causing a chemical bond with Si atoms on the semiconductor surface.

Abstract: The invention provides a method of manufacture of a display device which can achieve a reduction of the manufacturing process. In the manufacturing method, a semiconductor layer is formed over an upper surface of a substrate. An insulation film is formed over an upper surface of the semiconductor layer. Using a mask which covers a first region and exposes a second region, an implantation of impurities into the semiconductor layer is performed in the second region through the insulation film. After the mask is removed, a surface of the insulation film is etched in the first region and the second region to an extent that the insulation film in the second region remains, whereby the film thickness of the insulation film in the second region is set to be smaller than the film thickness of the insulation film in the first region.

Abstract: A polishing inhibiting layer forming additive for a slurry, the slurry so formed, and a method of chemical mechanical polishing are disclosed. The polishing inhibiting layer is formed through application of the slurry to the surface being polished and is removable at a critical polishing pressure. The polishing inhibiting layer allows recessed or low pattern density locations to be protected until a critical polishing pressure is exceeded based on geometric and planarity considerations, rather than slurry or polishing pad considerations. With the additive, polishing rate is non-linear relative to polishing pressure in a recessed/less pattern dense location. In one embodiment, the additive has a chemical structure: [CH3(CH2)xN(R)]M, wherein M is selected from the group consisting of: Cl, Br and I, x equals an integer between 2 and 24, and the R includes three carbon-based functional groups, each having less than eight carbon atoms.

Abstract: A novel, in-situ plasma treatment method for eliminating or reducing striations caused by standing waves in a photoresist mask, is disclosed. The method includes providing a photoresist mask on a BARC (bottom anti-reflective coating) layer that is deposited on a feature layer to be etched, etching the BARC layer and the underlying feature layer according to the pattern defined by the photoresist mask, and subjecting the photoresist mask to a typically argon or hydrogen bromide plasma before, after, or both before and after etching of the BARC layer prior to etching of the feature layer. Preferably, the photoresist mask is subjected to the plasma both before and after etching of the BARC layer.

Abstract: A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.

Abstract: The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate compensating for imprint mask critical dimension error(s). An aspect of the invention generates feedback information that facilitates control of imprint mask critical dimension via employing a scatterometry system to detect imprint mask critical dimension error, and mitigating the error via a spacer etchback procedure.

Abstract: The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that modify an imprint mask. An aspect of the invention generates feedback information that facilitates control of imprint mask feature height via employing a scatterometry system to detect topography variation and, decreasing imprint mask feature height in order to compensate for topography variation.

Abstract: A method for structuring a laterally extending first layer in a semiconductor device with the aid of a reactive second layer, which together with the first layer to be structured forms first reaction products, which products are removed by material removal that acts selectively on the first reaction products, whereby the structuring takes place in a vertical direction.

Abstract: A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect layer. An etch rate of the first dielectric layer is altered. A second dielectric layer is formed on the first dielectric layer. An etch rate of the second dielectric layer is then altered. A trench etch is performed to form a trench cavity within the second dielectric layer. A via etch is performed to form a via cavity within the first dielectric layer. The cavities are filled with conductive material and then planarized to remove excess fill material.

Abstract: A structure in a substrate for the manufacturing of a semiconductor device, wherein a first material and at least one second material are to be etched by at least one etching medium, wherein the at least one second material has a higher etch rate for the at least one etching medium relative to the first material. The at least one second material occupies a space which is at least at one side adjacent to the first material so that an additional etching access to the first material is prepared when at least one etching medium etches the first and the second material.

Abstract: A method for forming a recess. The method includes providing a substrate with two protrusions having a first side wall and a second side wall opposite to the first side wall disposed above the substrate, conformally forming a mask layer on the substrate and the protrusions, tilt implanting the mask layer using a first implanting mask adjacent to the first side wall of the protrusions, removing implanted portions of the mask layer to form a patterned mask layer, and etching the substrate using the patterned mask layer, thereby forming a recess.

Abstract: A method of forming at least one undercut structure in a semiconductor substrate. The method comprises providing a semiconductor substrate, forming at least one doped region in the semiconductor substrate, and removing the at least one doped region to form at least one undercut structure in the semiconductor substrate. The at least one undercut structure may include at least one substantially vertical shelf, at least one substantially horizontal shelf, and at least one faceted surface. The at least one doped region may be formed by implanting an impurity in the semiconductor substrate, which is, optionally, annealed. The at least one doped region may be removed selective to the undoped portion of the semiconductor substrate by at least one of wet etching or dry etching. An intermediate semiconductor structure that comprises a single crystalline silicon substrate and at least one undercut structure formed in the single crystalline silicon substrate is also disclosed.

Abstract: Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing an implant stopping layer over the substrate; depositing a photoresist over the implant stopping layer, the implant stopping layer having a density greater than the photoresist; forming a pattern in the photoresist by removing a portion of the photoresist to expose the implant stopping layer; and transferring the pattern into the implant stopping layer by etching to form the mask. The implant stopping layer may include: hydrogenated germanium carbide, nitrogenated germanium carbide, fluorinated germanium carbide, and/or amorphous germanium carbon hydride (GeHX), where X includes carbon. The methods/mask reduce scattering during implanting because the mask has higher density than conventional masks.

Abstract: A semiconductor device fabrication method comprises (1) forming a patterned mask layer on an oxide layer of a Mn-containing perovskite type oxide; (2) heat-treating the oxide layer; and (3) patterning the oxide layer with an etching solution containing at least one of hydrochloric acid, sulfuric acid, and nitric acid after the heat treatment of the oxide layer.

Abstract: A method for manufacturing an electronic device comprising the steps of: dry-etching a Ti-containing metal film formed on a substrate with a gas containing fluorine; and treating the substrate with a chemical solution containing fluorine ions after the dry etching step.

Abstract: A method of fabricating polycrystalline silicon thin film transistor according to the present invention includes: depositing a buffer layer on a substrate; depositing an amorphous silicon layer on the buffer layer with a predetermined thickness; crystallizing the deposited amorphous silicon layer by using a laser to form a polycrystalline silicon layer; etching the crystallized polycrystalline silicon layer to a predetermined thickness; curing the etched polycrystalline silicon layer; and patterning the cured polycrystalline silicon layer to form a semiconductor layer.

Abstract: A process for defining a chalcogenide material layer using a chlorine based plasma and a mask, wherein the portions of the chalcogenide material layer that are not covered by the mask are etched away. In a phase change memory cell having a stack of a chalcogenide material layer and an AlCu layer, the AlCu layer is etched first using a chlorine based plasma at a higher temperature; then the lateral walls of the AlCu layer are passivated; and then the chalcogenide material layer is etched at a lower temperature.

Abstract: A system and method for selectable area laser treatment of a substrate, such as thin film transistors, the system including a holder holding a substrate in proximity to reactant, and laser beams each addressing independently selectable mutually set apart locations on the substrate to induce a reaction between the substrate and the reactant.