Utilizing Multiple Gas Energizing Means Patents (Class 438/711)
  • Patent number: 12237155
    Abstract: In some examples, a magnetic shield for a plasma source is provided. An example magnetic shield comprises a back-shell. The back-shell includes a cage defined, at least in part, by an arrangement of bars of ferro-magnetic material. The cage is sized and configured to at least extend over a top side of an RF source coil for the plasma source.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: February 25, 2025
    Assignee: Lam Research Corporation
    Inventors: Hema Swaroop Mopidevi, Neil Martin Paul Benjamin, John Pease, Thomas Anderson
  • Patent number: 12237367
    Abstract: A method for forming a semiconductor structure includes: providing a semiconductor substrate, the surface of the semiconductor substrate having a plurality of active areas and shallow trench isolation areas arranged in a first direction; etching the active areas and the shallow trench isolation areas in a direction perpendicular to the first direction to form first recesses and second recesses; covering the surfaces of the first recesses and the second recesses with an adhesive layer and a metal layer; and secondarily etching the metal layer and the adhesive layer in the direction perpendicular to the first direction to form a contact hole, the depth of the adhesive layer in the contact hole being defined as H2.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: February 25, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Junchao Zhang, Cheng Yeh Hsu
  • Patent number: 12163911
    Abstract: Embodiments disclosed herein include a sensor assembly. In an embodiment, the sensor assembly comprises a sensor module and a housing assembly. In an embodiment, the sensor module comprises a substrate, a capacitor with a first electrode and a second electrode on the substrate, and a capacitive-to-digital converter (CDC) electrically coupled to the first electrode and the second electrode. In an embodiment, the housing assembly is attached to the sensor module and comprises a shaft, wherein the shaft is hollow, and a cap over a first end of the shaft, wherein the cap has an opening to expose the capacitor.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: December 10, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Yaoling Pan, Patrick John Tae, Leonard Tedeschi, Michael D. Willwerth, Daniel Thomas McCormick
  • Patent number: 12154790
    Abstract: An etching method includes (a) disposing a substrate having a silicon oxide film on a substrate support in a chamber. The substrate includes a plurality of etching stop layers arranged inside the silicon oxide film. The plurality of etching stop layers are arranged at different positions in a thickness direction of the silicon oxide film. Each of the plurality of etching stop layers is formed of at least one of tungsten and molybdenum. The etching method (b) supplying a processing gas into the chamber, the processing gas including a gas containing at least one of tungsten and molybdenum, a gas containing carbon and fluoride, and an oxygen-containing gas; and (c) generating plasma from the processing gas to etch the silicon oxide film, thereby forming a plurality of recesses that reach the plurality of etching stop layers, respectively, in the silicon oxide film.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: November 26, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Seiichi Watanabe, Manabu Sato, Masayuki Sawataishi, Hiroki Yamada, Shinji Orimo
  • Patent number: 12148633
    Abstract: The invention provides a plasma processing apparatus which includes a processing chamber, a radio frequency power source to supply a radio frequency power for plasma generation, a sample stage equipped with an electrostatic chuck electrode of a sample, a DC power source to apply a DC voltage to the electrode, and a control unit to change the DC voltage from a predetermined value to almost 0 V when a predetermined time elapses since the supplying of the radio frequency power is stopped. The predetermined value is a predetermined value indicating that a potential of the sample when the DC voltage is almost 0 V becomes almost 0 V. The predetermined time is a time defined on the basis of a time when charged particles generated by the plasma processing disappear or a time when an afterglow discharge disappears.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: November 19, 2024
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Masaki Ishiguro, Masahiro Sumiya
  • Patent number: 12100609
    Abstract: One or more embodiments described herein generally relate to methods for chucking and de-chucking a substrate to/from an electrostatic chuck used in a semiconductor processing system. Generally, in embodiments described herein, the method includes: (1) applying a first voltage from a direct current (DC) power source to an electrode disposed within a pedestal; (2) introducing process gases into a process chamber; (3) applying power from a radio frequency (RF) power source to a showerhead; (4) performing a process on the substrate; (5) stopping application of the RF power; (6) removing the process gases from the process chamber; and (7) stopping applying the DC power.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: September 24, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Sarah Michelle Bobek, Venkata Sharat Chandra Parimi, Prashant Kumar Kulshreshtha, Kwangduk Douglas Lee
  • Patent number: 11996293
    Abstract: A semiconductor device includes a substrate, a first semiconductor fin and a second semiconductor fin protruding from the substrate, an isolation feature disposed on the substrate and on sidewalls of the first and second semiconductor fins, a gate structure disposed on the isolation feature. The semiconductor device also includes a dielectric fin disposed on the isolation feature and sandwiched between the first and second semiconductor fins. A middle portion of the dielectric fin separates the gate structure into a first gate structure segment engaging the first semiconductor fin and a second gate structure segment engaging the second semiconductor fin.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Yu Wang, Zhi-Chang Lin, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 11955322
    Abstract: A device for a plasma processing chamber includes a base, an upper portion attached to the base and extending transverse to the base, and one or more first through holes defined in the base. The one or more first through holes correspond to one or more openings defined in the plasma processing chamber for attaching the device. The device further includes a second through hole defined in the upper portion, and a gauge located in the second through hole, the gauge configured for recording a position of the plasma processing chamber and a shift in the position of the plasma processing chamber.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming Che Chen, Wei-Chen Liao
  • Patent number: 11881379
    Abstract: In a mask pattern forming method, a resist film is formed over a thin film, the resist film is processed into resist patterns having a predetermined pitch by photolithography, slimming of the resist patterns is performed, and an oxide film is formed on the thin film and the resist patterns after an end of the slimming step in a film deposition apparatus by supplying a source gas and an oxygen radical or an oxygen-containing gas. In the mask pattern forming method, the slimming and the oxide film forming are continuously performed in the film deposition apparatus.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: January 23, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Shigeru Nakajima, Jun Ogawa, Hiroki Murakami
  • Patent number: 11854773
    Abstract: A method of cleaning a chamber for an electronics manufacturing system includes flowing a gas mixture comprising oxygen and a carrier gas into a remote plasma generator. The method further includes generating a plasma from the gas mixture by the remote plasma generator and performing a remote plasma cleaning of the chamber by flowing the plasma into an interior of the chamber, wherein the plasma removes a plurality of organic contaminants from the chamber.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: December 26, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Yuanhong Guo, Sheng Guo, Marek Radko, Steve Sansoni, Xiaoxiong Yuan, See-Eng Phan, Yuji Murayama, Pingping Gou, Song-Moon Suh
  • Patent number: 11721530
    Abstract: Provided herein are approaches for controlling radicals in proximity to a wafer. In some embodiments, a system may include a radical source operable to generate radicals in proximity to the wafer, and a filter positioned between the radical source and the wafer, wherein the filter includes a first plate operable to control radicals generated by the radical source. The system may further include an ion source operable to deliver an ion beam to the wafer, wherein the ion beam passes outside the filter.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: August 8, 2023
    Assignee: Applied Materials, Inc.
    Inventor: Christopher R. Hatem
  • Patent number: 11615964
    Abstract: An etching method in accordance with the present disclosure includes providing a substrate, which includes a silicon-containing film, in a chamber; and etching the silicon-containing film with a chemical species in plasma generated from a process gas supplied in the chamber. The process gas includes a phosphorus gas component and a fluorine gas component.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: March 28, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takahiro Yokoyama, Maju Tomura, Yoshihide Kihara, Ryutaro Suda, Takatoshi Orui
  • Patent number: 11594444
    Abstract: The present disclosure relates to a susceptor having a generally circular body having a face with a radially inward section and a radially outward section which includes a substrate supporting surface elevated relative to the radially inward section. A sidewall surrounds the substrate supporting surface which upon retention of a substrate on the radially outward section, the sidewall surrounds the substrate. The sidewall includes a plurality of humps which protrude from the top surface of the sidewall. Advantageously, the plurality of humps may aid in even thickness of deposition of material at the edge of the substrate.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: February 28, 2023
    Assignee: ASM IP Holding, B.V.
    Inventors: Matthew Goodman, Thomas John Kirschenheiter, Kevin Eugene Quinn
  • Patent number: 11424128
    Abstract: A substrate etching apparatus for etching a substrate, the substrate etching apparatus includes a treatment container configured to accommodate a substrate, a stage on which the substrate is placed, the stage being disposed in the treatment container, a gas supply configured to supply a treatment gas from an upper space above the stage toward the stage, and a gas exhauster configured to evacuate an interior of the treatment container. The gas supply includes a central region facing a central part of the stage and an outer peripheral region having a same central axis as the central region and configured to surround the central region. The gas supply is capable of supplying the treatment gas to each of the central region and the outer peripheral region.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: August 23, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yuji Asakawa, Nobuhiro Takahashi
  • Patent number: 11373875
    Abstract: There is provided a plasma processing method for forming shallow trench isolation (STI) on a silicon substrate, the plasma processing method including: a trench forming step of forming a trench in the silicon substrate by using plasma generated by pulse-modulated radio frequency power; and an oxidation step of oxidizing the silicon substrate by using only oxygen gas which is performed after the trench forming step, in which the trench forming step and the oxidizing step are repeated a plurality of times.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: June 28, 2022
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Yusuke Nagamitsu, Takeshi Shima, Takeshi Shimada, Hayato Watanabe
  • Patent number: 11264209
    Abstract: Plasma processing systems and methods are disclosed. The system may include at least one modulating supply that modulates plasma properties where the modulation of the plasma properties has a repetition period, T. A synchronization module configured to send a synchronization signal with a synchronization-signal-repetition-period that is an integer multiple of T to at least one piece of equipment connected to the plasma processing system. A waveform-communication module communicates characteristics of a characterized waveform to at least one piece of equipment connected to the plasma system to enable synchronization of pieces of equipment connected to the plasma processing system. The characterized waveform may contain information about the modulation of the plasma or information about a desired waveform of a piece of equipment connected to the plasma processing system.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: March 1, 2022
    Assignee: Advanced Energy Industries, Inc.
    Inventors: Gideon Van Zyl, Kevin Fairbairn, Denis Shaw
  • Patent number: 10781515
    Abstract: There is provided a method of forming a predetermined film by alternately supplying a film-forming raw material gas and a reaction gas onto a workpiece by an atomic layer deposition (ALD), the method including: beginning an ALD-based film formation at a first temperature at which an adsorption of the film-forming raw material gas occurs; continuing the ALD-based film formation while increasing the first temperature; and completing the ALD-based film formation at a second temperature at which a decomposition of the film-forming raw material gas occurs.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: September 22, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kyungseok Ko, Hiromi Shima, Eiji Kikama, Keisuke Suzuki
  • Patent number: 10577690
    Abstract: Embodiments disclosed herein generally relate to a gas distribution assembly for providing improved uniform distribution of processing gases into a semiconductor processing chamber. The gas distribution assembly includes a gas distribution plate, a blocker plate, and a dual zone showerhead. The gas distribution assembly provides for independent center to edge flow zonality, independent two precursor delivery, two precursor mixing via a mixing manifold, and recursive mass flow distribution in the gas distribution plate.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: March 3, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Anh N. Nguyen, Dmitry Lubomirsky, Mehmet Tugrul Samir
  • Patent number: 10304668
    Abstract: Plasma processing conditions may be changed for localized regions of a substrate. A reactive gas may be maintained in a localized region of a substrate while other regions of the substrate are not exposed to the reactive gas. Thus, plasma conditions may be generated at specific regions of the substrate. A multi-zoned gas injection system may be utilized to direct certain gases in certain regions of the plasma space. Techniques may be provided to maintain these gases in the desired regions, as opposed to the gases spreading across the substrate surface. Reactive gases may be provided in one region while a flow of inert gas is provided in other regions in which it is desired to restrict the effects of the reactive gases. Localized control of the plasma process may be provided as a separate plasma processing step. The localized region of the substrate may be the substrate edge.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: May 28, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Brian J. Coppa, Vaidya Bharadwaj
  • Patent number: 10157750
    Abstract: The present invention provides a plasma processing method and a plasma processing apparatus. The plasma processing method enables consistent processing by realizing a high selectivity and a high etching rate when etching a laminated film using a boron-containing amorphous carbon film, realizes high throughput including prior and post processes by simplifying a mask forming process, and has shape controllability of vertical processing. In the present invention, in a plasma processing method for forming a mask by plasma-etching a laminated film including an amorphous carbon film containing boron, the boron-containing amorphous carbon film is plasma-etched by using a mixed gas of an oxygen gas, a fluorine-containing gas, a halogen gas, and a silicon tetrafluoride gas, or a mixed gas of an oxygen gas, a fluorine-containing gas, a halogen gas, and a silicon tetrachloride gas.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: December 18, 2018
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Satoshi Terakura, Masahito Mori, Takao Arase, Taku Iwase
  • Patent number: 10141329
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: November 27, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Hirotaka Tsuda, Yusuke Oshiki
  • Patent number: 10023960
    Abstract: Embodiments related to hardware and methods for processing a semiconductor substrate are disclosed. One example film deposition reactor includes a process gas distributor including a plasma gas-feed inlet located to supply plasma gas to a plasma generation region within the film deposition reactor and a precursor gas-feed inlet located to supply film precursor gas downstream of the plasma generation region; an insulating confinement vessel configured to maintain a plasma generation region at a reduced pressure within the film deposition reactor and an inductively-coupled plasma (ICP) coil arranged around a portion of a sidewall of the insulating confinement vessel and positioned so that the sidewall separates the plasma generation region from the ICP coil; and a susceptor configured to support the semiconductor substrate so that a film deposition surface of the semiconductor substrate is exposed to a reaction region formed downstream of the process gas distributor.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: July 17, 2018
    Assignee: ASM IP Holdings B.V.
    Inventors: Fred Alokozai, Robert Brennan Milligan
  • Patent number: 9613825
    Abstract: Provided herein are methods and apparatus of hydrogen-based photoresist strip operations that reduce dislocations in a silicon wafer or other substrate. According to various embodiments, the hydrogen-based photoresist strip methods can employ one or more of the following techniques: 1) minimization of hydrogen budget by using short processes with minimal overstrip duration, 2) providing dilute hydrogen, e.g., 2%-16% hydrogen concentration, 3) minimization of material loss by controlling process conditions and chemistry, 4) using a low temperature resist strip, 5) controlling implant conditions and concentrations, and 6) performing one or more post-strip venting processes. Apparatus suitable to perform the photoresist strip methods are also provided.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: April 4, 2017
    Assignee: Novellus Systems, Inc.
    Inventors: Roey Shaviv, Kirk Ostrowski, David Cheung, Joon Park, Bayu Thedjoisworo, Patrick J. Lord
  • Patent number: 9324575
    Abstract: In a plasma etching method for forming a hole in an etching target film, a process of generating a plasma of a processing gas containing at least CxFy gas and a rare gas having a mass smaller than a mass of Ar gas into the processing chamber in the processing chamber by switching on a high frequency power application unit under a first condition and a process of extinguishing the plasma of the processing gas in the processing chamber by switching off the high frequency power application unit under a second condition are alternately repeated. A negative DC voltage from a DC power supply is applied such that an absolute value of the negative DC voltage of the second condition becomes greater than an absolute value of the negative DC voltage of the first condition.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: April 26, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Akira Nakagawa
  • Patent number: 9318340
    Abstract: A method of manufacturing a semiconductor device including a wafer using a plasma etching device which includes a chamber, a chuck provided in the chamber to dispose a wafer to be processed thereon, a focus ring disposed at a peripheral edge portion of the chuck, and a gas supplying mechanism configured to supply various types of gases depending a radial position of the wafer. The method includes: placing a wafer formed with an organic film on the chuck; introducing an etching gas which etches the organic film on the wafer from the process gas supplying mechanism to a central portion of the wafer; introducing an etching inhibiting factor gas having a property of reacting with the etching gas to the peripheral edge portion of the wafer from the gas supplying mechanism; and performing plasma etching on the wafer using the etching gas.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: April 19, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takayuki Katsunuma, Masanobu Honda, Kazuhiro Kubota, Hironobu Ichikawa
  • Patent number: 9066413
    Abstract: A plasma generation apparatus includes a vacuum container, dielectrics connected to through-holes formed in the vacuum container, RF coils of the same structure disposed in the vicinity of the respective dielectrics and electrically connected in parallel, an RF power source to supply power to the RF coils, an impedance matching circuit disposed between the RF power source and the RF coils, and a power distribution unit disposed between the impedance matching circuit and one ends of the RF coils to distribute the power of the RF power source to the RF coils. The power distribution unit includes a power distribution line and a conductive outer cover enclosing the power distribution line. Distance between an input end of the power distribution unit and the RF coils are equal to each other, and the other ends of the RF coils are connected to the conductive outer cover to be grounded.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: June 23, 2015
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Hong-Young Chang, Sanghyuk An, Jinwon Lee
  • Patent number: 9039911
    Abstract: Methods for etching a substrate in a plasma processing chamber having at least a primary plasma generating region and a secondary plasma generating region separated from said primary plasma generating region by a semi-barrier structure. The method includes generating a primary plasma from a primary feed gas in the primary plasma generating region. The method also includes generating a secondary plasma from a secondary feed gas in the secondary plasma generating region to enable at least some species from the secondary plasma to migrate into the primary plasma generating region. The method additionally includes etching the substrate with the primary plasma after the primary plasma has been augmented with migrated species from the secondary plasma.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: May 26, 2015
    Assignee: Lam Research Corporation
    Inventors: Eric A. Hudson, Andrew D. Bailey, III, Rajinder Dhindsa
  • Publication number: 20150126037
    Abstract: This disclosure relates to a plasma processing system for controlling plasma density across a substrate and maintaining a tight ion energy distribution within the plasma. In one embodiment, this may include using a dual plasma chamber system including a non-ambipolar plasma chamber and a DC plasma chamber adjacent to the non-ambipolar system. The DC plasma chamber provide power to generate the plasma by rotating the incoming power between four inputs from a VHF power source. In one instance, the power to each of the four inputs are at least 90 degrees out of phase from each other.
    Type: Application
    Filed: November 6, 2014
    Publication date: May 7, 2015
    Inventors: Lee Chen, Zhiying Chen
  • Publication number: 20150079797
    Abstract: A method of etching silicon nitride on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and a nitrogen-and-oxygen-containing precursor. Plasma effluents from two remote plasmas are flowed into a substrate processing region where the plasma effluents react with the silicon nitride. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon nitride while very slowly removing silicon, such as polysilicon. The silicon nitride selectivity results partly from the introduction of fluorine-containing precursor and nitrogen-and-oxygen-containing precursor using distinct (but possibly overlapping) plasma pathways which may be in series or in parallel.
    Type: Application
    Filed: September 8, 2014
    Publication date: March 19, 2015
    Inventors: Zhijun Chen, Zihui Li, Anchuan Wang, Nitin K. Ingle, Shankar Venkataraman
  • Patent number: 8956980
    Abstract: A method of etching silicon nitride on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and a nitrogen-and-oxygen-containing precursor. Plasma effluents from two remote plasmas are flowed into a substrate processing region where the plasma effluents react with the silicon nitride. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon nitride while very slowly removing silicon, such as polysilicon. The silicon nitride selectivity results partly from the introduction of fluorine-containing precursor and nitrogen-and-oxygen-containing precursor using distinct (but possibly overlapping) plasma pathways which may be in series or in parallel.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: February 17, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Zhijun Chen, Zihui Li, Anchuan Wang, Nitin K. Ingle, Shankar Venkataraman
  • Publication number: 20150024603
    Abstract: In a plasma etching method for etching a metal layer of a substrate to be processed through a hard mask by using a plasma etching apparatus, a first step in which a first etching gas comprising a mixed gas of O2, CF4 and HBr is used as an etching gas, and a second step in which a second etching gas comprising a mixed gas of O2 and CF4 is used as an etching gas, are continuously and alternately repeated a plurality of times. At this time, a first high-frequency power of a first frequency and a second high-frequency power of a second frequency, which is lower than the first frequency, are applied to a lower electrode, and the first high-frequency power is applied in a pulse form.
    Type: Application
    Filed: January 31, 2013
    Publication date: January 22, 2015
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Akinori Kitamura, Kenta Yasuda, Shunsuke Ishida
  • Patent number: 8927435
    Abstract: A load lock includes a chamber including an upper portion, a lower portion, and a partition between the upper portion and the lower portion, the partition including an opening therethrough. The load lock further includes a first port in communication with the upper portion of the chamber and a second port in communication with the lower portion of the chamber. The load lock includes a rack disposed within the chamber and a workpiece holder mounted on a first surface of the rack, wherein the rack and the workpiece holder are movable by an indexer that is capable of selectively moving wafer slots of the rack into communication with the second port. The indexer can also move the rack into an uppermost position, at which the first surface of the boat and the partition sealingly separate the upper portion and the lower portion to define an upper chamber and a lower chamber. Auxiliary processing, such as wafer pre-cleaning, or metrology can be conducted in the upper portion.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: January 6, 2015
    Assignee: ASM America, Inc.
    Inventors: Ravinder K. Aggarwal, Jeroen Stoutjesdijk, Eric R. Hill, Loring G. Davis, John T. DiSanto
  • Patent number: 8921234
    Abstract: Methods of etching exposed titanium nitride with respect to other materials on patterned heterogeneous structures are described, and may include a remote plasma etch formed from a fluorine-containing precursor. Precursor combinations including plasma effluents from the remote plasma are flowed into a substrate processing region to etch the patterned structures with high titanium nitride selectivity under a variety of operating conditions. The methods may be used to remove titanium nitride at faster rates than a variety of metal, nitride, and oxide compounds.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: December 30, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Jie Liu, Jingchun Zhang, Anchuan Wang, Nitin K. Ingle, Seung Park, Zhijun Chen, Ching-Mei Hsu
  • Publication number: 20140363977
    Abstract: In a plasma processing apparatus including a first radio-frequency power supply which supplies first radio-frequency power for generating plasma in a vacuum chamber, a second radio-frequency power supply which supplies second radio-frequency power to a sample stage on which a sample is mounted, and a matching box for the second radio-frequency power supply, the matching box samples information for performing matching during a sampling effective period which is from a point of time after elapse of a prescribed time from a beginning of on-state of the time-modulated second radio-frequency power until an end of the on-state and maintains a matching state attained during the sampling effective period from after the end of the on-state until a next sampling effective period.
    Type: Application
    Filed: February 19, 2014
    Publication date: December 11, 2014
    Applicant: Hitachi High-Technologies Corporation
    Inventors: Michikazu Morimoto, Naoki Yasui, Yasuo Ohgoshi
  • Patent number: 8900402
    Abstract: A semiconductor substrate processing system includes a substrate support defined to support a substrate in exposure to a processing region. The system also includes a first plasma chamber defined to generate a first plasma and supply reactive constituents of the first plasma to the processing region. The system also includes a second plasma chamber defined to generate a second plasma and supply reactive constituents of the second plasma to the processing region. The first and second plasma chambers are defined to be independently controlled.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: December 2, 2014
    Assignee: Lam Research Corporation
    Inventors: John Patrick Holland, Peter L. G. Ventzek, Harmeet Singh, Richard Gottscho
  • Publication number: 20140329390
    Abstract: A plasma treatment device includes a dielectric window containing SiO2. The insulating film to be etched comprises silicon carbonitride. In a first plasma treatment step, a processing gas which contains no oxygen gas and contains CH2F2, etc, is used to deposit a protective film. In a second plasma treatment step, a processing gas which contains oxygen gas and contains CH3F, etc. is used to etch away the top and other portions of a part having a convex cross-sectional shape.
    Type: Application
    Filed: December 7, 2012
    Publication date: November 6, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Masaki Inoue, Kazuhisa Ishii, Motoki Noro, Shinji Kawada
  • Patent number: 8871647
    Abstract: A group III nitride substrate in one embodiment has a surface layer. The surface layer contains 3 at. % to 25 at. % of carbon and 5×1010 atoms/cm2 to 200×1010 atoms/cm2 of a p-type metal element. The group III nitride substrate has a stable surface.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: October 28, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Keiji Ishibashi
  • Publication number: 20140302682
    Abstract: The present invention provides a plasma processing method that uses a plasma processing apparatus including a plasma processing chamber in which a sample is plasma processed, a first radio-frequency power supply that supplies a first radio-frequency power for generating plasma, and a second radio-frequency power supply that supplies a second radio-frequency power to a sample stage on which the sample is mounted, wherein the plasma processing method includes the steps of modulating the first radio-frequency power by a first pulse; and controlling a plasma dissociation state to create a desired dissociation state by gradually controlling a duty ratio of the first pulse as a plasma processing time elapses.
    Type: Application
    Filed: August 7, 2013
    Publication date: October 9, 2014
    Applicant: Hitachi High-Technologies Corporation
    Inventors: Satoru MUTO, Tetsuo ONO, Yasuo OHGOSHI, Hirofumi EITOKU
  • Publication number: 20140199848
    Abstract: A method and apparatus for tailoring the formation of active species using one or more electron beams to improve gap-fill during an integrated circuit formation process is disclosed herein. The energy of the electron beams may be decreased to maximize electrons leading to radicals or increased to maximize electrons leading to ions, depending on the fill application. An apparatus comprising multiple impinging jets of gas perpendicular to one or more electron beams is also disclosed.
    Type: Application
    Filed: March 14, 2014
    Publication date: July 17, 2014
    Applicant: Applied Materials, Inc.
    Inventor: Matthew S. ROGERS
  • Patent number: 8772182
    Abstract: A semiconductor device manufacture method has the steps of: (a) coating a low dielectric constant low-level insulating film above a semiconductor substrate formed with a plurality of semiconductor elements; (b) processing the low-level insulating film to increase a mechanical strength of the low-level insulating film; (c) coating a low dielectric constant high-level insulating film above the low-level insulating film; and (d) forming a buried wiring including a wiring pattern in the high-level insulating film and a via conductor in the low-level insulating film. The low-level insulating film and high-level insulating film are made from the same material. The process of increasing the mechanical strength includes an ultraviolet ray irradiation process or a hydrogen plasma applying process.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: July 8, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshiyuki Ohkura
  • Patent number: 8772171
    Abstract: A gas switching system for a gas distribution system for supplying different gas compositions to a chamber, such as a plasma processing chamber of a plasma processing apparatus, is provided. The chamber can include multiple zones, and the gas switching section can supply different gases to the multiple zones. The switching section can switch the flows of one or more gases, such that one gas can be supplied to the chamber while another gas can be supplied to a by-pass line, and then switch the gas flows.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: July 8, 2014
    Assignee: Lam Research Corporation
    Inventor: Dean J. Larson
  • Patent number: 8759227
    Abstract: A method for processing a target object includes arranging a first electrode and a second electrode for supporting the target object in parallel to each other in a processing chamber and processing the target object supported by the second electrode by using a plasma of a processing gas supplied into the processing chamber, the plasma being generated between the first electrode and the second electrode by applying a high frequency power between the first electrode and the second electrode. The target object includes an organic film and a photoresist layer formed on the organic film. The processing gas contains H2 gas, and the organic film is etched by a plasma containing H2 by using the photoresist layer as a mask while applying a negative DC voltage to the first electrode.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: June 24, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Kazuki Narishige, Kazuo Shigeta
  • Publication number: 20140162462
    Abstract: A plasma-assisted etch process for the manufacture of semiconductor or MEMS devices employs an RF source to generate a plasma that is terminated through an electrode. The termination is designed as a “short” at the frequency of the RF source to minimize voltage fluctuations on the electrode due to the RF source energy. The electrode voltage potential can then be accurately controlled with a bias source, resulting in improved control of etch depth of a semiconductor substrate disposed on the electrode.
    Type: Application
    Filed: July 18, 2013
    Publication date: June 12, 2014
    Applicant: APPLIED MATERIALS INC.
    Inventors: Yuri Trachuck, Robert Chebi, Carl Almgren
  • Publication number: 20140141619
    Abstract: Techniques disclosed herein include apparatus and processes for generating a plasma having a uniform electron density across an electrode used to generate the plasma. An upper electrode (hot electrode), of a capacitively coupled plasma system can include structural features configured to assist in generating the uniform plasma. Such structural features define a surface shape, on a surface that faces the plasma. Such structural features can include a set of concentric rings having an approximately rectangular cross section, and protruding from the surface of the upper electrode. Such structural features can also include nested elongated protrusions having a cross-sectional size and shape, with spacing of the protrusions selected to result in a system that generates a uniform density plasma.
    Type: Application
    Filed: November 19, 2012
    Publication date: May 22, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Ikuo Sawada
  • Patent number: 8728948
    Abstract: A method of manufacturing a semiconductor device is disclosed. The method may comprise: forming a gate stack on a substrate; depositing a first dielectric layer and a second dielectric layer sequentially on the substrate and the gate stack; and etching the second dielectric layer and the first dielectric layer sequentially with an etching gas containing helium to form a second spacer and a first spacer, respectively. According to the method disclosed herein, a dual-layer complex spacer configuration is achieved, and two etching operations where the etching gas comprises the helium gas are performed. As a result, it is possible to reduce damages to the substrate and also to reduce the process complexity. Further, it is possible to optimize a threshold voltage, effectively reduce an EOT, and enhance a gate control capability and a driving current.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: May 20, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Lingkuan Meng
  • Patent number: 8722542
    Abstract: A method for patterning a layer at a bottom of a high aspect ratio feature of a substrate is described. The method includes providing the substrate having a first layer with a feature pattern overlying a second layer. The feature pattern is characterized with an initial critical dimension (CD), an initial corner profile, and an aspect ratio of 5:1 or greater. The method further includes etching through at least a portion of the second layer at the bottom of the feature pattern to extend the feature pattern at least partially into the second layer while retaining a final CD within a threshold of the initial CD and a final corner profile within a threshold of the initial corner profile using a gas cluster ion beam (GCIB) etching process.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 13, 2014
    Assignee: TEL Epion Inc.
    Inventors: Christopher K. Olsen, Luis Fernandez
  • Patent number: 8664122
    Abstract: The present invention discloses a method of fabricating a semiconductor device. In the present invention, after the formation of a photo-resist mask on a substrate, the photo-resist is subjected to a plasma pre-treatment, and then etch is conducted. With the plasma pre-treatment, a line width roughness of a linear pattern of the photo-resist can be improved, and thus much better linear patterns can be formed on the substrate during the subsequent etching steps.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: March 4, 2014
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Minda Hu, Dongjiang Wang, Haiyang Zhang
  • Publication number: 20140057447
    Abstract: Semiconductor processing systems are described including a process chamber. The process chamber may include a lid assembly, grid electrode, conductive insert, and ground electrode. Each component may be coupled with one or more power supplies operable to produce a plasma within the process chamber. Each component may be electrically isolated through the positioning of a plurality of insulation members. The one or more power supplies may be electrically coupled with the process chamber with the use of switching mechanisms. The switches may be switchable to electrically couple the one or more power supplies to the components of the process chamber.
    Type: Application
    Filed: March 14, 2013
    Publication date: February 27, 2014
    Applicant: Applied Materials, Inc.
    Inventor: Applied Materials, Inc.
  • Patent number: 8658048
    Abstract: The present invention aims to prevent decreases in etching rate due to adhesion of an etched film to a substrate holder. A method of manufacturing a magnetic recording medium includes: forming a first film on a substrate holder not yet having a substrate mounted thereon; mounting a substrate on the substrate holder having the first film formed thereon, the substrate having a resist layer formed on a multilayer film including a magnetic film layer, the resist layer having a predetermined pattern; and processing the magnetic film layer into a shape based on the predetermined pattern by performing dry etching on the substrate. The first film is a film that is not etched as easily as the films in the multilayer film to be removed by the dry etching.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: February 25, 2014
    Assignee: Canon Anelva Corporation
    Inventors: Kazuto Yamanaka, Shogo Hiramatsu
  • Patent number: 8647990
    Abstract: Methods of patterning low-k dielectric films are described.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: February 11, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Yifeng Zhou, Srinivas D. Nemani, Khoi Doan, Jeremiah T. Pender