Abstract: A method for etching a conductive layer through a mask with wider and narrower features is provided. A steady state etch gas is flowed. A steady state RF power is provided to form a plasma from the etch gas. A pulsed bias voltage is provided during the steady state etch gas flow, wherein the pulsed bias voltage has a frequency between 1 to 10,000 Hz. Wider and narrower features are etched into the conductive layer using the plasma formed from the etch gas.

Abstract: A method and system for fabricating a substrate is disclosed. First, a plurality of process chambers are provided, at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate and at least one of the plurality of process chambers containing a plasma filtering plate library. A plasma filtering plate is selected and removed from the plasma filtering plate library. Then, the plasma filtering plate is inserted into at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate. Subsequently, an etching process is performed in the substrate.

Abstract: A wafer-scale assembly circuit including a plurality of metal interconnect layers, where each metal layer includes patterned metal portions and where at least some of the patterned metal portions are RF signal lines. The circuit further includes at least one benzocyclobutene layer provided between two metal interconnect layers that includes at least one trench via formed around a perimeter of the benzocyclobutene layer at a circuit sealing ring, where the trench via provides a hermetic seal at the sealing ring. The benzocyclobutene layer also includes a plurality of stabilizing post vias formed through the benzocyclobutene layer adjacent to the trench via proximate to the sealing ring and extending around the perimeter of the benzocyclobutene layer, where the stabilizing vias operate to prevent the benzocyclobutene layer from shrinking in size.

Abstract: Etching equipment and methods are disclosed herein for more efficient etching of sacrificial material from between permanent MEMS structures. An etching head includes an elongate etchant inlet structure, which may be slot-shaped or an elongate distribution of inlet holes. A substrate is supported in proximity to the etching head in a manner that defines a flow path substantially parallel to the substrate face, and permits relative motion for the etching head to scan across the substrate.

Abstract: Different gases are separately exposed to RF energy in different zones in inlets to a processing chamber. Plasma is activated in the gases in each of the zones separately and the activated gases are then introduced into the plasma processing chamber where they may undergo mutual interaction within a processing zone. Control of the active species distribution within the processing chamber is provided by control of the energizing of the gases in the separate inlet zones before they are combined in the processing zone. An ICP source energizes gas in each zone through an antenna having one or more conductors, each of which is coupled to a plurality of the zones. This allows gases to be brought together in their active states, rather than being combined and then activated, and allows the same or different parameters to be applied in different inlet zones.

Abstract: In a process for forming trenches having M different widths in a substrate, a passivation step and an etching step are alternately performed. The passivation step includes depositing a passivation layer on a bottom of the trenches by converting gas introduced in a chamber into plasma. The etching step includes removing the passivation layer on the bottom of the trenches and applying reactive ion etching to the bottom to increase a depth of the trenches. The etching step further includes setting energy for the reactive ion etching to a predetermined value when the passivation layer on the bottom of the trench having the Nth smallest width is removed. The value allows the etching amount of the trench having the Nth smallest width to be equal to or greater than the etching amount of the trench having the (N+1)th smallest width.

Abstract: A system, method and apparatus for increasing an energy level of the ions emitted from a plasma include a plasma chamber, including a top electrode and a bottom electrode, a multiple RF sources, at least one of the RF sources being coupled to the bottom electrode. A phase locking circuit is coupled to at least two of the RF sources hereafter designated the first RF source and the second RF source. A controller is coupled to the plasma chamber, each of the RF sources and the phase locking circuit. The controller including operating system software, multiple logic circuits and a process recipe.

Abstract: A large surface substrate (5, 5a) is Rf vacuum plasma treated with the help of an electrode arrangement (9) consisting of an even number of electrode strips (9a, 9b). At least one of the strips is Rf supplied at least two distinct loci (P1, P2) along the central axis (A) of the addressed strip (9a).

Abstract: Embodiments for processing a substrate in a pulsed plasma chamber are provided. A processing apparatus with two chambers, separated by a plate fluidly connecting the chambers, includes a continuous wave (CW) controller, a pulse controller, and a system controller. The CW controller sets the voltage and the frequency for a first radio frequency (RF) power source coupled to a top electrode. The pulse controller is operable to set voltage, frequency, ON-period duration, and OFF-period duration for a pulsed RF signal generated by a second RF power source coupled to the bottom electrode. The system controller is operable to set parameters to regulate the flow of species between the chambers to assist in the negative-ion etching, to neutralize excessive positive charge on the wafer surface during afterglow in the OFF period, and to assist in the re-striking of the bottom plasma during the ON period.

Abstract: A method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, includes the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. The present invention further provides a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region, and a method for planarizing an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate.

Abstract: A method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, includes the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. The present invention further provides a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region, and a method for planarizing an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate.

Abstract: A method of forming a contact hole includes loading a substrate into a plasma chamber, the substrate including an etch stop layer, an insulation interlayer, a mask layer and a photoresist pattern sequentially disposed thereon, applying a DC voltage to an upper electrode and applying a first high frequency power and a second high frequency power to a lower electrode to generate plasma in the chamber, the first frequency power and second high frequency powers having different frequency levels, supplying a reaction gas to the chamber to etch the mask layer and the insulation interlayer, wherein the chamber is maintained at a temperature of 100° C. to 200° C.

Abstract: The present invention relates to a plasma etching method and apparatus for preparing high-aspect-ratio structures. The method includes the steps of placing the substrate into a plasma etching apparatus, wherein the plasma etching apparatus includes an upper electrode plate and a lower electrode plate; continuously supplying an upper source RF power and a DC power to the upper electrode plate; and discontinuously supplying a bias RF power to the lower electrode plate. When the bias RF power is switched to the off state, a large amount of secondary electrons pass through the bulk plasma and reach the substrate to neutralize the positive ions during the duration time of the off state (Toff).

Abstract: A significantly improved low-k dielectric patterning method is described herein using plasma comprising an oxygen radical source and a silicon source to remove the photo-resist layer.

Abstract: A semiconductor substrate processing system includes a chamber that includes a processing region and a substrate support. The system includes a top plate assembly disposed within the chamber above the substrate support. The top plate assembly includes first and second sets of plasma microchambers each formed into the lower surface of the top plate assembly. A first network of gas supply channels are formed through the top plate assembly to flow a first process gas to the first set of plasma microchambers to be transformed into a first plasma. A set of exhaust channels are formed through the top plate assembly. The second set of plasma microchambers are formed inside the set of exhaust channels. A second network of gas supply channels are formed through the top plate assembly to flow a second process gas to the second set of plasma microchambers to be transformed into a second plasma.

Abstract: A semiconductor substrate processing system includes a substrate support defined to support a substrate in exposure to a processing region. The system also includes a first plasma chamber defined to generate a first plasma and supply reactive constituents of the first plasma to the processing region. The system also includes a second plasma chamber defined to generate a second plasma and supply reactive constituents of the second plasma to the processing region. The first and second plasma chambers are defined to be independently controlled.

Abstract: The present invention generally provides a method of forming a high efficiency solar cell device by preparing a surface and/or forming at least a part of a high quality passivation layer on a silicon containing substrate. Embodiments of the present invention may be especially useful for preparing a surface of a p-type doped region formed on a silicon substrate so that a high quality passivation layer can be formed thereon. In one embodiment, the methods include exposing a surface of the solar cell substrate to a plasma to clean and modify the physical, chemical and/or electrical characteristics of the surface.

Abstract: A substrate plasma processing apparatus includes a chamber of which an interior is evacuated under a predetermined vacuum condition; an RF electrode which is disposed in the chamber and configured so as to hold a substrate to be processed on a main surface thereof; an opposing electrode which is disposed opposite to the RF electrode in the chamber; an RF voltage applying device for applying an RF voltage with a predetermined frequency to the RF electrode; and a pulsed voltage applying device for applying a pulsed voltage to the RF electrode so as to be superimposed with the RF voltage and which includes a controller for controlling a timing in application of the pulsed voltage and defining a pause period of the pulsed voltage.

Abstract: A method to further adjust the final CD of a material to be etched during an etching process, and after a photolithographic patterning process can include patterning a semiconductor substrate using a mask layer. The mask layer can comprise a hardmask material having a protruding feature with an initial width. A first plasma comprising carbon and fluorine can be introduced into a chamber, where residual carbon and fluorine is deposited on at least the chamber wall. A portion of the mask layer can then be removed with a second plasma incorporating the residual carbon and fluorine, whereby remaining hardmask material forms a feature pattern where the protruding feature has a final width different from the initial width. The feature pattern can then be transferred to the semiconductor substrate using the final width of the at least one protruding feature provided by the remaining hardmask material.

Abstract: Methods for etching substrates using a pulsed DC voltage are provided herein. In some embodiments, a method for method for etching a substrate disposed on a substrate support within a process chamber may include providing a process gas to the process chamber; forming a plasma from the process gas; applying a pulsed DC voltage to a first electrode disposed within the process chamber; and etching the substrate while applying the pulsed DC voltage.

Abstract: A method for etching high-aspect-ratio features is disclosed. The method is applicable in forming a nanoscale deep trench having a smooth and angle-adjustable sidewall. The method includes: forming a patterned photoresist layer on a surface of a silicon substrate for exposing a part of the silicon substrate; and supplying a process gas simultaneously containing sulfur hexafluoride (SF6) and fluorinated carbon composition into a chamber in which the substrate in positioned for carrying out a deep reactive ion etching operation to etch the part of the silicon substrate for forming the deep trench. The method forms a nanoscale deep trench with a high silicon-to-photoresist etching selectivity.

Abstract: The invention provides a plasma treatment apparatus or a plasma treatment method having a high productivity while maintaining a stable treatment performance.

Abstract: In a plasma etching method, a substrate including an underlying film, an insulating film and a resist mask is plasma etched to thereby form a number of holes in the insulating film including a dense region and a sparse region by using a parallel plate plasma etching apparatus for applying a plasma-generating high frequency electric power to a space between an upper and a lower electrode and a biasing high frequency electric power to the lower electrode. The plasma etching method includes mounting the substrate on a mounting table; supplying a first process gas containing carbon and fluorine to form the holes in the insulating film to a depth close to the underlying film; and supplying a second process gas including an inert gas and another gas contain carbon and fluorine to have the holes reach the underlying film while applying a negative DC voltage to the upper electrode.

Abstract: A method of etching recesses into silicon prior to formation of embedded silicon alloy source/drain regions. The recess etch includes a plasma etch component, using an etch chemistry of a primary fluorine-based or chlorine-based etchant, in combination with a similar concentration of hydrogen bromide. The concentration of both the primary etchant and the hydrogen bromide is relatively low; a diluent of an inert gas or oxygen is added to the reactive species. Loading effects on the undercut of the recess etch are greatly reduced, resulting in reduced transistor performance variation.

Abstract: The present invention relates to a plasma etching method with which a wide-gap semiconductor substrate can be etched with high accuracy. An inert gas is supplied into a processing chamber and plasma is generated from the inert gas, a bias potential is applied to a platen on which a wide-gap semiconductor substrate is placed, thereby making ions generated by the generation of plasma from the inert gas incident on the semiconductor substrate on the platen to thereby heat the semiconductor substrate. After the temperature of the semiconductor substrate reaches an etching temperature between 200° C. and 400° C., an etching gas is supplied into the processing chamber and plasma is generated from the etching gas and a bias potential is applied to the platen, thereby etching the semiconductor substrate while maintaining the temperature of the semiconductor substrate at the etching temperature.

Abstract: Methods of decreasing the effective dielectric constant present between two conducting components of an integrated circuit are described. The methods involve the use of a gas phase etch which is selective towards the oxygen-rich portion of the low-K dielectric layer. The etch rate attenuates as the etch process passes through the relatively high-K oxygen-rich portion and reaches the low-K portion. The etch process may be easily timed since the gas phase etch process does not readily remove the desirable low-K portion.

Abstract: A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to be etched is exposed first to plasma under a low power strike and subsequently to a conventional high power strike. CD loss has been found to be reduced by about 400 Angstroms and striations formed in the contact holes are reduced.

Abstract: A multi-step etching process produces trench openings in a silicon substrate that are immediately adjacent transistor structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms an opening bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The aggressive undercut produces a desirable stress in the etched silicon surface. The openings are then filled with a suitable source/drain material and SSD transistors with desirable Idsat characteristics may then be formed.

Abstract: The current invention provides methods for performing a cleaning process that provides greater cleaning efficiency with less damage to device structures. After etching and photoresist stripping, a first plasma clean is performed. The first plasma clean may comprise one or more steps. Following the first plasma clean, a first HO based clean is performed. The first HO based clean may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. Following the first HO based clean, a second plasma clean is performed, which may comprise one or more steps. A second HO based clean follows the second plasma clean, and may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. For plasma processes, an RF, generated plasma, a microwave generated plasma, an inductively coupled plasma, or combination may be used.

Abstract: The present invention pertains to methods for removing unwanted material from a semiconductor wafer during wafer manufacturing. More specifically, the invention pertains to stripping photo-resist material and removing etch-related residues from a semiconductor wafer. Methods involve implementing a plasma operation using hydrogen and a weak oxidizing agent, such as carbon dioxide. The invention is effective at stripping photo-resist and removing residues from low-k dielectric material used in Damascene devices.

Abstract: There is provide a method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, including the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. there are also provided a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region by improving the etching uniformity of sidewalls and bottom surface of the shallow trench, and a method for planarizating an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate.

Abstract: A plasma processing method, which enables the etching controllability for a high-dielectric-constant insulating film to be improved. A substrate having a high-dielectric-constant gate insulating film and a hard mask formed thereon is subjected to etching processing using a plasma of a processing gas containing a noble gas and a reducing gas.

Abstract: The present invention generally provides a method of forming a high efficiency solar cell device by preparing a surface and/or forming at least a part of a high quality passivation layer on a silicon containing substrate. Embodiments of the present invention may be especially useful for preparing a surface of a p-type doped region formed on a silicon substrate so that a high quality passivation layer can be formed thereon. In one embodiment, the methods include exposing a surface of the solar cell substrate to a plasma to clean and modify the physical, chemical and/or electrical characteristics of the surface.

Abstract: A method of etching a material that includes comprising germanium, antimony, and tellurium encompasses exposing said material to a plasma-enhanced etching chemistry comprising Cl2 and CH2F2. A method of forming a variable resistance memory cell includes forming a conductive inner electrode material over a substrate. A variable resistance chalcogenide material comprising germanium, antimony, and tellurium is formed over the conductive inner electrode material. A conductive outer electrode material is formed over the chalcogenide material. The germanium, antimony, and tellurium-comprising material is plasma etched using a chemistry comprising Cl2 and CH2F2.

Abstract: A method of producing a semiconductor element includes the steps of forming a wiring portion layer on a substrate; forming an interlayer insulation layer over the substrate and the wiring portion layer, in which a third insulation film, a second insulation film, and a first insulation film are laminated in this order from the substrate; forming a mask pattern on the first insulation film; removing a contact hole forming area of the first insulation film through a wet etching process; removing a contact hole forming area of the second insulation film through an etching process; removing a contact hole forming area of the third insulation film through an etching process; and a contact hole forming step of forming a contact hole in the interlayer insulation layer so that a surface of the wiring portion layer is exposed.

Abstract: A method for forming a trench includes providing a substrate, and forming the trench in the substrate using a gas containing chlorine (Cl2) gas as a main etch gas and SiFX gas as an additive gas, wherein a sidewall of the trench has a substantially vertical profile by virtue of reaction of the Cl2 gas and the SiFX gas.

Abstract: A method of forming a conformal dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD) includes: introducing a nitrogen- and hydrogen-containing reactive gas and a rare gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space; and introducing a hydrogen-containing silicon precursor as a first precursor and a hydrocarbon gas as a second precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a conformal dielectric film doped with carbon and having Si—N bonds on the substrate.

Abstract: A high density plasma dep/etch/dep method of depositing a dielectric film into a gap between adjacent raised structures on a substrate disposed in a substrate processing chamber. The method deposits a first portion of the dielectric film within the gap by forming a high density plasma from a first gaseous mixture flown into the process chamber, etches the deposited first portion of the dielectric film by flowing an etchant gas comprising CxFy, where a ratio of x to y is greater than or equal to 1:2 and then deposits a second portion of the dielectric film over the first portion by forming a high density plasma from a second gaseous mixture flown into the process chamber.

Abstract: A manufacturing method of a semiconductor device using a semiconductor manufacturing unit comprising a reaction chamber, a substrate mounting stage, and a high frequency power supply coupled to the substrate mounting stage, a blocking capacitor interposed between the substrate mounting stage and the high-frequency power supply to continuously perform a plurality of dry etching processing with respect to the same substrate in the same reaction chamber, the method includes: disposing a substrate on a substrate mounting stage, and applying high-frequency powers to the substrate mounting stage while introducing a fluorocarbon-based first gas to perform a first dry etching processing with respect to the substrate, the substrate including an organic material film and a silicon compound film sequentially deposited on a surface thereof and a resist film patterned on the silicon compound film, the first dry etching processing including processing the silicon compound film with the resist film being used as a mask; and

Abstract: A rework method of a gate insulating layer of a thin film transistor includes the following steps. First, a substrate including a silicon nitride layer, which serves as a gate insulating layer, disposed thereon. Subsequently, a first film removal process is performed to remove the silicon nitride layer. The first film removal process includes an inductively coupled plasma (ICP) etching process. The ICP etching process is carried out by introducing gases including sulfur hexafluoride and oxygen. The ICP etching process has an etching selectivity ratio of the silicon nitride layer to the substrate, which is substantially between 18 and 30.

Abstract: A method of forming a conformal dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD) includes: introducing a nitrogen- and hydrogen-containing reactive gas and an additive gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space; and introducing a hydrogen-containing silicon precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a conformal dielectric film having Si—N bonds on the substrate.

Abstract: A method of manufacturing a semiconductor device in which a source contact plug and a drain contact plug are formed. The method includes the steps of etching part of the semiconductor substrate to form a step, thus forming an overlay vernier, and forming a hard mask on the step so that the step is maintained.

Abstract: A method for processing a target object includes arranging a first electrode and a second electrode for supporting the target object in parallel to each other in a processing chamber and processing the target object supported by the second electrode by using a plasma of a processing gas supplied into the processing chamber, the plasma being generated between the first electrode and the second electrode by applying a high frequency power between the first electrode and the second electrode. The target object includes an organic film and a photoresist layer formed on the organic film. The processing gas contains H2 gas, and the organic film is etched by a plasma containing H2 by using the photoresist layer as a mask while applying a negative DC voltage to the first electrode.

Abstract: A semiconductor wafer includes a substrate, a conductive layer, a dielectric layer having a via, a hard mask defined a trench pattern, and a sacrificial layer. Then a sequential of etching processes is performed upon the semiconductor wafer in a chamber to form a trench and expose the conductive layer. By operating all procedures within one chamber, manufacturing time is efficiently shortened and yield is thus increased.

Abstract: Etch selectivity enhancement during electron beam activated chemical etch (EBACE) is disclosed. A target or portion thereof may be exposed to a gas composition of a type that etches the target when the gas composition and/or target are exposed to an electron beam. By directing an electron beam toward the target in the vicinity of the gas composition, an interaction between the electron beam and the gas composition etches a portion of the target exposed to both the gas composition and the electron beam. Selectivity of etching of the target due to interaction between the electron beam and gas composition may be enhanced in a number of ways.

Abstract: A manufacturing method of a semiconductor device using a semiconductor manufacturing unit comprising a reaction chamber, a substrate mounting stage, and a high frequency power supply coupled to the substrate mounting stage, a blocking capacitor interposed between the substrate mounting stage and the high-frequency power supply to continuously perform a plurality of dry etching processing with respect to the same substrate in the same reaction chamber, the method includes: disposing a substrate on a substrate mounting stage, and applying high-frequency powers to the substrate mounting stage while introducing a fluorocarbon-based first gas to perform a first dry etching processing with respect to the substrate, the substrate including an organic material film and a silicon compound film sequentially deposited on a surface thereof and a resist film patterned on the silicon compound film, the first dry etching processing including processing the silicon compound film with the resist film being used as a mask; and

Abstract: Formation of a bottom electrode for an MTJ device on a silicon nitride substrate is facilitated by including a layer of ruthenium near the silicon nitride surface. The ruthenium is a good electrical conductor and it responds differently from Ta and TaN to certain etchants. Adhesion to SiN is enhanced by using a TaN/NiCr bilayer as “glue”. Thus, said included layer of ruthenium may be used as an etch stop layer during the etching of Ta and/or TaN while the latter materials may be used to form a hard mask for etching the ruthenium without significant corrosion of the silicon nitride surface.

Abstract: A method of etching a material that includes comprising germanium, antimony, and tellurium encompasses exposing said material to a plasma-enhanced etching chemistry comprising Cl2 and CH2F2. A method of forming a variable resistance memory cell includes forming a conductive inner electrode material over a substrate. A variable resistance chalcogenide material comprising germanium, antimony, and tellurium is formed over the conductive inner electrode material. A conductive outer electrode material is formed over the chalcogenide material. The germanium, antimony, and tellurium-comprising material is plasma etched using a chemistry comprising Cl2 and CH2F2.

Abstract: Methods of preventing photoresist scum formation for etch processes for patterning material layers of semiconductor device material layers are disclosed. A treatment of N2 and O2 is used to prevent the formation of photoresist scum. The treatment may be performed in-situ, and may be performed during the etch process, after the etch process, or both. The treatment is particularly beneficial when implemented during the patterning of low dielectric constant material layers, and when used for the formation of isolated via patterns.

Abstract: A process of cleaning a semiconductor manufacturing system, and a method of manufacturing a semiconductor device. The cleaning process includes, for example, positioning a ceramic cover on the electrostatic chuck in tight contact with the chuck, and feeding a fluoride-based cleaning gas into a chamber. After the cleaning process, a process of forming a semiconductor film (deposition process) is performed. It is possible to prevent fluorine degasification from a substrate-supporting electrode (electrostatic chuck) during the deposition process. A semiconductor film can be formed without causing a temperature drop near the substrate. This prevents irregular film thickness, defective etching, film flaking, etc.