Abstract: A semiconductor device manufacturing method includes a plasma etching process for selectively plasma etching a silicon nitride film against a silicon oxide film formed under the silicon nitride film in a substrate to be processed. The plasma etching process uses an etching gas including a CmFn gas (m, n represent integers of 1 or greater) added to a gaseous mixture of a CHxFy gas (x, y represent integers of 1 or greater) and O2 gas, wherein the flow rate of the CmFn gas is not greater than 10% of that of the O2 gas. The etching gas may further include a rare gas.

Abstract: Methods of filling trenches/gaps defined by circuit elements on an integrated circuit substrate are provided. The methods include forming a first high-density plasma layer on an integrated circuit substrate including at least one trench thereon using a first reaction gas. The first high-density plasma layer is etched using an etch gas including nitrogen fluoride gas (NF3). A second high-density plasma layer is formed on the etched first high-density plasma layer using a second reaction gas including nitrogen fluoride.

Abstract: A method and apparatus for removing residue, such as etch reside, from a substrate with substantially reduced damage to the substrate in a plasma processing system is described. A plasma ashing process comprising carbon dioxide (CO2) and optionally a passivation gas, such as a hydrocarbon gas, i.e., CxHy, wherein x, y represent integers greater than or equal to unity, is used to remove residue while reducing damage to underlying dielectric layers. Additionally, the process chemistry can further comprise the addition of an inert gas, such as a Noble gas (i.e., He, Ne, Ar, Kr, Xe, Rn).

Abstract: The present invention pertains to methods for removing unwanted material from a semiconductor wafer during wafer manufacturing. More specifically, the invention pertains to stripping photo-resist material and removing etch-related residues from a semiconductor wafer. Methods involve implementing a plasma operation using hydrogen and a weak oxidizing agent, such as carbon dioxide. The invention is effective at stripping photo-resist and removing residues from low-k dielectric material used in Damascene devices.

Abstract: A method of etching organic low-k dielectric materials is provided herein. In one embodiment, a method of etching organic low-k dielectric materials includes placing a substrate comprising an exposed organic low-k dielectric material in an etch reactor; supplying a process gas comprising an oxygen-containing gas, a nitrogen-containing gas, and methane (CH4); and forming a plasma from the process gas to etch the organic low-k dielectric material. The organic low-k dielectric material may include polymer-based low-k dielectric materials, photoresists, or organic polymers. The oxygen-containing gas may be oxygen (O2) and the nitrogen-containing gas may be nitrogen (N2).

Abstract: The present invention provides an upper electrode used in an etching apparatus and the etching apparatus including the upper electrode, both of which can properly reduce intensity of electric field of plasma around a central portion of a substrate to be processed, thus enhancing in-plane uniformity of a plasma process. In this apparatus, a recess, serving as a space for allowing a dielectric to be injected therein, is provided around a central portion of the upper electrode. A dielectric supply passage configured for supplying the dielectric into the space and a dielectric discharge passage configured for discharging the dielectric from the space are connected with the space, respectively.

Abstract: A method of pre-treating a mask layer prior to etching an underlying thin film is described. A thin film, such as a dielectric film, is etched using plasma that is enhanced with a ballistic electron beam. In order to reduce the loss of pattern definition, such as line edge roughness effects, the mask layer is treated with an electron beam in the absence of an atomic halogen specie prior to proceeding with the etching process.

Abstract: Embodiments of the present invention relate to methods and systems for making a microelectromechanical system MEMS device comprising supplying an etchant to etch one or more sacrificial structures of the system in a chamber. A process parameter relating to the pressure within the chamber is monitored as a function of time to provide an indication of the extent of the etching of the one or more sacrificial structures.

Abstract: The current invention provides methods for performing a cleaning process that provides greater cleaning efficiency with less damage to device structures. After etching and photoresist stripping, a first plasma clean is performed. The first plasma clean may comprise one or more steps. Following the first plasma clean, a first HO based clean is performed. The first HO based clean may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. Following the first HO based clean, a second plasma clean is performed, which may comprise one or more steps. A second HO based clean follows the second plasma clean, and may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. For plasma processes, an RF generated plasma, a microwave generated plasma, an inductively coupled plasma, or combination may be used.

Abstract: Process and apparatus provide reactive radicals generated from a remote plasma source which contact a portion of a substrate surface simultaneous with a contact of the same substrate surface with a light source which locally activates the portion of the substrate surface in contact with said radicals.

Abstract: A gate hard mask is deposited on a gate structure using low pressure chemical vapor deposition (LPCVD). By doing so, the wet etch removal ratio (WERR) of the gate hard mask relative to the underlying polysilicon gate layer is increased when compared to prior art hard masks. The LPCVD gate hard mask will not only etch faster than prior art hard masks, but it will also reduce undercutting of the gate oxide. To provide additional control of the wet etch rate, the LPCVD hard mask can be annealed. The annealing can be tailored to achieve the desired etching rate.

Abstract: A method for treating a substrate with plasma over a wide pressure range is described. The method comprises exposing the substrate to a low pressure plasma in a process chamber. Further, the method comprises exposing the substrate to a high pressure plasma in the process chamber.

Abstract: A method of processing a wafer in a plasma, in which target values of two different plasma process parameters are simultaneously realized under predetermined process conditions by setting respective power levels of VHF and HF power simultaneously coupled to the wafer to respective optimum levels.

Abstract: A dry etching method is provided, in which dry etching is performed in such a manner that a conductor to which an insulative substrate is attached is brought in electric, intimate contact with an electrode. In the dry etching method, the insulative substrate is attached to the conductor by means of a conductive grease. A diffractive optical element manufactured with the dry etching method is also provided.

Abstract: A method and system for processing a substrate includes providing the substrate in a process chamber, where the substrate contains an oxide layer formed thereon, exciting a hydrogen-containing gas in a remote plasma source coupled to the process chamber, and exposing the substrate to a flow of the excited hydrogen-containing gas at a first substrate temperature lower than about 900° C. to remove the oxide layer from the substrate. The substrate is then maintained at a second temperature different than the first substrate temperature, and a silicon-containing film is formed on the substrate at the second substrate temperature.

Abstract: Methods of forming electrical interconnect structures include forming a dielectric layer on a semiconductor substrate and forming a hard mask layer on the dielectric layer. A photoresist layer is patterned on an upper surface of the hard mask layer. This patterned photoresist layer is used as an etching mask during a step to selectively etch the hard mask layer and define an opening therein. This opening exposes the first dielectric layer. The patterned photoresist layer is then stripped from the hard mask layer using an ashing process that exposes the upper surface of the hard mask layer. Following this ashing process, a portion of the first dielectric layer extending opposite the opening is selectively etched using the hard mask layer as an etching mask. During this selective etching step, polymer residues are accumulated directly on the upper surface of the hard mask layer.

Abstract: A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps.

Abstract: Disclosed are embodiments relating to a method of manufacturing a semiconductor device that may improve the yield rate of the semiconductor device. In embodiments, the method may include preparing a substrate including a plurality of conductive patterns, forming first and second insulating layers on the substrate, forming a plurality of via holes by selectively etching the first and second insulating layers, forming a plurality of trenches by selectively etching the second insulating layer in such a manner that the trenches are communicated with the trenches, and forming metal interconnections in the via holes and the trenches. The width ratio of the trench to the insulating layer positioned between adjacent trenches may be in a range of 0.45 to 0.55.

Abstract: In the method for microstructuring flat glass substrates a substrate surface of a glass substrate is coated with at least one structured mask layer and subsequently exposed to a chemically reactive ion etching process (RIE) with at least one chemical etching gas. In order to provide the same or a higher quality etching and etching rate even for economical types of glass the chemical etching gas is mixed with at least one noble gas, so that the proportion of sputtering etching in the ion etching process is significantly increased.

Abstract: A technology for inhibiting the dielectric breakdown occurred in a semiconductor device is provided. A semiconductor device includes a semiconductor substrate (not shown), an interlayer insulating film 102 formed on the semiconductor substrate and a multiple-layered insulating film 140 provided on the interlayer insulating film 102. The semiconductor device also includes an electric conductor that extends through the multiple-layered insulating film 140 and includes a Cu film 120 and a barrier metal film 118. The barrier metal film 118 is covers side surfaces and a bottom surface of the Cu film 120. An insulating film 116 is disposed between the multiple-layered insulating film 140 and the electric conductor (i.e., Cu film 120 and barrier metal film 118).

Abstract: A plasma processing method includes providing a substrate in a processing chamber, the substrate having a surface, and generating a plasma in the processing chamber. The plasma provides at least two regions that exhibit different plasma densities. The method includes exposing at least some of the surface to both of the at least two regions. Exposing the surface to both of the at least two regions may include rotating the plasma and may cyclically expose the surface to the plasma density differences. Exposing to both of the at least two regions may modify a composition and/or structure of the surface. The plasma may include a plasmoid characterized by a steady state plasma wave providing multiple plasma density lobes uniformly distributed about an axis of symmetry and providing plasma between the lobes exhibiting lower plasma densities. Depositing the layer can include ALD and exposure may remove an ALD precursor ligand.

Abstract: An oxygen-free hydrogen plasma ashing process particularly useful for low-k dielectric materials based on hydrogenated silicon oxycarbide materials. The main ashing step includes exposing a previously etched dielectric layer to a plasma of hydrogen and optional nitrogen, a larger amount of water vapor, and a yet larger amount of argon or helium. Especially for porous low-k dielectrics, the main ashing plasma additionally contains a hydrocarbon gas such as methane. The main ashing may be preceded by a short surface treatment by a plasma of a hydrogen-containing reducing gas such as hydrogen and optional nitrogen.

Abstract: A method for removing at least one photoresist defect is disclosed. The photoresist defect is exposed to a plasma produced from a source gas including oxygen and a non-oxidizing gas in a plasma reactor, wherein the oxygen is present in the source gas at from 1% by volume to about 89% by volume. The non-oxidizing gas includes a mixture of hydrogen and nitrogen, ammonia or combinations thereof. A method for processing a semiconductor device structure is also disclosed, as are embodiments of the source gas.

Abstract: An improved solution for producing nitride-based heterostructure(s), heterostructure device(s), integrated circuit(s) and/or Micro-Electro-Mechanical System(s) is provided. A nitride-based etch stop layer that includes Indium (In) is included in a heterostructure. An adjacent layer of the heterostructure is selectively etched to expose at least a portion of the etch stop layer. The etch stop layer also can be selectively etched. In one embodiment, the adjacent layer can be etched using reactive ion etching (RIE) and the etch stop layer is selectively etched using a wet chemical etch. In any event, the selectively etched area can be used to generate a contact or the like for a device.

Abstract: A plasma processing method for processing a target substrate uses a plasma processing apparatus which includes a vacuum evacuable processing vessel for accommodating the target substrate therein, a first electrode disposed in the processing vessel and connected to a first RF power supply for plasma generation and a second electrode disposed to face the first electrode. The method includes exciting a processing gas containing fluorocarbon in the processing vessel to generate a plasma while applying a negative DC voltage having an absolute value ranging from about 100 V to 1500 V or an RF power of a frequency lower than about 4 MHz to the second electrode. The target layer is etched by the plasma, thus forming recesses on the etching target layer based on the pattern of the resist layer.

Abstract: By providing an additional silicon dioxide based etch stop layer, a corresponding etch process for forming contact openings for directly connecting polysilicon lines and active areas may be controlled in a highly reliable manner. In another aspect, the etch selectivity of the contact structure may be increased by a modification of the etch behavior of the exposed portion of the contact etch stop layer.

Abstract: The current invention provides methods for performing a cleaning process that provides greater cleaning efficiency with less damage to device structures. After etching and photoresist stripping, a first plasma clean is performed. The first plasma clean may comprise one or more steps. Following the first plasma clean, a first HO based clean is performed. The first HO based clean may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. Following the first HO based clean, a second plasma clean is performed, which may comprise one or more steps. A second HO based clean follows the second plasma clean, and may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. For plasma processes, an RF generated plasma, a microwave generated plasma, an inductively coupled plasma, or combination may be used.

Abstract: A plasma processing device comprising a gas injection system is described, wherein the gas injection system comprises a gas injection assembly body, a consumable gas inject plate coupled to the gas injection assembly body, and a pressure sensor coupled to a gas injection plenum formed by the gas injection system body and the consumable gas inject plate. The gas injection system is configured to receive a process gas from at least one mass flow controller and distribute the process gas to the processing region within the plasma processing device, and the pressure sensor is configured to measure a gas injection pressure within the gas injection plenum. A controller, coupled to the pressure sensor, is configured to receive a signal from the pressure sensor and to determine a state of the consumable gas inject plate based upon the signal.

Abstract: A method for finishing a metal line for a semiconductor device is disclosed, in which polymer generated when forming the metal line including aluminum and its alloy is effectively removed and the metal line is prevented from being eroded. A chlorine radical and a chlorine compound remaining on a surface of the metal line are removed using H2O plasma and the polymer is removed using H2O gas and HF gas not plasma. Therefore, it is possible to improve reliability and yield of the semiconductor device.

Abstract: An apparatus and a method for fabricating a semiconductor device are provided. The method can efficiently remove by-products from a foreline connected to a process chamber. The apparatus includes a remote plasma source, which generates a plasma gas. The plasma gas is guided to the foreline, so as to remove impurities formed on an inner wall of the foreline.

Abstract: A semiconductor wafer is processed while being supported without mechanical contact. Instead, the wafer is supported by gas streams emanating from a large number of passages in side sections positioned very close to the upper and lower surface of the wafer. The gas heated by the side sections and the heated side sections themselves quickly heat the wafer to a desired temperature. Process gas directed to the “device side” of the wafer can be kept at a temperature that will not cause deposition on that side section, but yet the desired wafer temperature can be obtained by heating non-process gas from the other side section to the desired temperature. A plurality of passages around the periphery of the wafer on the non-processed side can be employed to provide purge gas flow that prevents process gas from reaching the non-processed side of the wafer and the adjacent area of that side section.

Abstract: A method for etching features in a silicon oxide based dielectric layer over a substrate, comprising performing an etch cycle. A lag etch partially etching features in the silicon oxide based dielectric layer is performed, comprising providing a lag etchant gas, forming a plasma from the lag etchant gas, and etching the etch layer with the lag etchant gas, so that smaller features are etched slower than wider features. A reverse lag etch further etching the features in the silicon oxide based dielectric layer is performed comprising providing a reverse lag etchant gas, which is different from the lag etchant gas and is more polymerizing than the lag etchant gas, forming a plasma from the reverse lag etchant gas, and etching the silicon oxide based dielectric layer with the plasma formed from the reverse lag etchant gas, so that smaller features are etched faster than wider features.

Abstract: The present invention pertains to methods for removing unwanted material from a semiconductor wafer during wafer manufacturing. More specifically, the invention pertains to stripping photo-resist material and removing etch-related residues from a semiconductor wafer. Methods involve implementing a plasma operation using hydrogen and a weak oxidizing agent, such as carbon dioxide. The invention is effective at stripping photo-resist and removing residues from low-k dielectric material used in Damascene devices.

Abstract: A method and a device suitable for its execution are provided for the anisotropic plasma etching of a substrate, especially a silicon element. The device has a chamber and a plasma source for generating a high-frequency electromagnetic alternating field and a reaction region for generating a plasma having reactive species inside the chamber, the reactive species being created by the action of the alternating field upon an etching gas, and a passivating gas that is especially simultaneously introduced but spatially separated from it. Furthermore, an arrangement is provided, by the use of which, in the reaction region, at least a first zone that has etching gas applied to it, and at least a second zone that has passivating gas applied to it, are defined.

Abstract: A plasma etch process etches high aspect ratio openings in a dielectric film on a workpiece in a reactor having a ceiling electrode overlying the workpiece and an electrostatic chuck supporting the workpiece. The process includes injecting a polymerizing etch process gas through an inner annular zone of gas injection orifices in the ceiling electrode, and evacuating gas from the reactor through a pumping annulus surrounding an edge of the workpiece. The high aspect ratio openings are etched in the dielectric film with etch species derived from the etch process gas while depositing a polymer derived from the etch process gas onto the workpiece, by generating a plasma in the reactor by applying VHF source power to the ceiling electrode and HF and/or LF bias power to an electrode within the electrostatic chuck.

Abstract: A process is provided for substrate ashing following the etching of features in a low dielectric constant (low-k) layer. The low-k layer can include ultra-low-k material, or a porous low-k material. The process may be configured to remove etch byproducts while preserving feature critical dimension. The ashing process comprises the use of a nitrogen and hydrogen containing chemistry with a passivation chemistry that includes oxygen, such as O2, CO, or CO2, or any combination thereof.

Abstract: A method for printing contacts utilizes photolithographic pattern reversal. A negative of the contact is printed on a resist layer. Unexposed portions of the resist layer are stripped to expose a first layer. The first layer is etched to remove exposed portions of the first layer not covered by the negative of the contact and to expose a second layer. A pattern reversal is performed to cure exposed portions of the second layer not covered by the first layer.

Abstract: A method and apparatus for etching material layers with high uniformity of a lateral etch rate across a substrate using a gas mixture that includes a passivation gas. The passivation gas is provided to a peripheral region of the substrate to passivate sidewalls of the structures being etched.

Abstract: Methods for forming a protective polymeric coating on a silicon or silicon-carbide electrode of a plasma processing chamber are provided. The polymeric coating provides protection to the underlying surface of the electrode with respect to exposure to constituents of plasma and gaseous reactants. The methods can be performed during a process of cleaning the chamber, or during a process for etching a semiconductor substrate in the chamber.

Abstract: A method of plasma etching a layer of dielectric material having a dielectric constant that is greater than four (4). The method includes exposing the dielectric material layer to a plasma comprising a hydrocarbon gas and a halogen containing gas.

Abstract: The invention relates to controlling a semiconductor processing system. Among other things, the invention relates to a run-to-run controller to create virtual modules to control a multi-pass process performed by a multi-chamber tool during the processing of a semiconductor wafer.

Abstract: A semiconductor process exposes metal in anticipation of an additional processing step that includes a deposition of a layer. Between the two processing steps, the exposed metal is exposed to ambient conditions that may include humidity. The effect of the humidity is potentially to cause corrosion of the exposed metal causing a yield loss. In order to withstand the various time periods that may occur between processing steps, an inhibitor is applied to the exposed surface causing the formation of a very thin protective layer on the exposed metal, which greatly inhibits corrosion. This thin protective layer does not cause any problems with the subsequent step because the typical following steps all, by their very nature, remove the protective layer. Thus, the time period between the processing step that exposes the metal and the next step is no longer critical due to the protective layer.

Abstract: A low-k dielectric film is deposited on the wafer. A metal layer is then deposited over the low-k dielectric film. A resist pattern is formed over the metal layer. The resist pattern is then transferred to the underlying metal layer to form a metal pattern. The resist pattern is stripped off. A through hole is plasma etched into the low-k dielectric film by using the metal pattern as a hard mask. The plasma etching causes residues to deposit within the through hole. A first wet treatment is then performed to soften the residues. A plasma dry treatment is carried out to crack the residues. A second wet treatment is performed to completely remove the residues.

Abstract: A mask material layer 102 of a desired pattern is formed on a silicon oxide film 101. The exposed parts of the silicon oxide film 101 is etched in accordance with the pattern of the mask material layer 102 by plasma etching by using a mixed gas fed at a rate such that the ratio (C5F8+O2/Ar) of the total flow rate of C5F8+O2 to the flow rate of Ar is 0.02 (2%) or less. Thus, a generally vertical right-angled portion is formed in the silicon oxide film 101. Therefore, no microtrenches are formed, and etching into a desired pattern is precisely effected.

Abstract: Methods and systems for preparing a substrate for analysis are provided. One method includes removing a portion of a copper structure on the substrate using an etch chemistry in combination with an electron beam. The etch chemistry is substantially inert with respect to the copper structure except in the presence of the electron beam. Other methods involve forming masking layers on a substrate that will protect the substrate during etching. For example, one method includes exposing a first portion of the substrate to an electron beam. A second portion of the substrate not exposed to the electron beam includes a copper structure. The method also includes exposing the substrate to a fluorine containing chemical. The fluorine containing chemical bonds to the first portion but not the second portion to form a fluorine containing layer on the first portion.

Abstract: A method of etching a barrier layer in an integrated circuit (IC) wherein said barrier layer is composed of silicon nitride or silicon carbide. The method comprises receiving an etched IC structure having an exposed barrier layer. The method then proceeds to apply an etchant gas mixture comprising a nitrous oxide (N2O) gas and a fluoromethane (CH3F) gas. The etchant gas mixture provides a relatively high selectivity between the barrier layer to an adjacent dielectric layer.

Abstract: The invention includes methods of processing semiconductor substrates. In one implementation, a semiconductor substrate is provided which has an outer surface. Such surface has a peripheral region received about a peripheral edge of the semiconductor substrate. A layer including amorphous carbon is provided over the substrate outer surface. A masking layer is provided outwardly of the amorphous carbon-including layer. A resist layer is provided outwardly of the masking layer. At least a portion of the peripheral region of the outer surface includes the amorphous carbon-including layer and the resist layer, but is substantially void of the masking layer. The amorphous carbon-including layer is patterned using the resist layer and the masking layer effective to form a mask over the semiconductor substrate. After the patterning, the semiconductor substrate is processed inwardly of the mask through openings formed in the mask.

Abstract: A Si etching method etches a Si wafer held on a susceptor placed in a processing vessel by a plasma-assisted etching process. A mixed etching gas prepared by mixing fluorosulfur gas, such as SF6 gas, or fluorocarbon gas, O2 gas and fluorosilicon gas, such as SiF4 gas is supplied into the processing vessel. RF power of 40 MHz or above is applied to the mixed etching gas to generate a plasma. The Si wafer is etched with radicals and ions contained in the plasma.

Abstract: A system and method for distributing gas to a substrate in a dry etch chamber make use of different flow channels to distribute the gas to different portions of a substrate. A first flow channel can be oriented to distribute gas to an inner portion of the substrate. A second flow channel can be oriented to distribute gas to an outer portion of the substrate. With different flow channels, the system and method enable separate control of gas distribution for different portions of the substrate. In particular, the flow channels allow separate control of gas flow rate, concentration, and flow time for different areas of the substrate. In this manner, gas distribution can be selectively controlled to compensate for different etch rates across the substrate surface. Also, gas distribution can be controlled as a function of etch rate patterns exhibited by different etch gasses used in successive process steps.

Abstract: To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.