Abstract: A memory gate stack in a high density memory core has spaces on the order of less than 0.25 microns using conventional deep ultraviolet (DUV) lithography techniques by depositing a layer of silicon oxynitride over a plurality of layers, and a thin resist layer overlying on the silicon oxynitride layer. The resist layer has a thickness sufficient to withstand removal during etching of the silicon oxynitride layer, for example about 3,000 Angstroms to about 4,000 Angstroms. The silicon oxynitride layer has a sacrificial portion having a thickness at least about 500 Angstroms, and a stop-layer thickness, used for spacer formation following etching of the memory gate, of at least 1,000 Angstroms. The use of silicon oxynitride as an antireflective coating layer in combination with the thin resist optimizes the resolution of DUV lithography, enabling formation of spacers having widths less than about 0.24 microns.

Abstract: An improved etch of thick protective topside stack films, which cover metal pads of a semiconductor device. The invention uses a downstream plasma isotropic etch to etch the topside stack film. In one embodiment, the downstream plasma isotropic etch is used to etch only part of the topside stack films. A subsequent anisotropic oxide plasma etch is used to etch the remaining topside stack film to the metal pads. In another embodiment, the downstream plasma isotropic etch is used to etch completely through the topside stack films to the metal pad. The invention allows the etching through topside stack films greater than 5 microns.

Abstract: Method for fabrication of damascene interconnects and related structures is disclosed. A sacrificial layer is formed over a low-k dielectric. Trenches are then etched inside the sacrificial layer and the low-k dielectric. The trenches are then filled with metal. During a first CMP process, excess metal over the sacrificial layer is removed. During a second CMP process, the sacrificial layer over the low-k dielectric and any remaining excess metal are removed. By the end of the second CMP process substantially all of the sacrificial layer and all of the excess metal are removed. In this manner, the trenches in the low-k dielectric are filled with metal where the metal surface is substantially flush with the surface of the low-k dielectric.

Abstract: A gate oxide film and a polysilicon layer are formed on a silicon substrate, and a pattern of photoresist is formed on the polysilicon layer. A silicon layer is etched halfway using a CF type gas such as CF4, CHF3, CH2F2 and C4F8 or a mixed gas including the same with the photoresist serving as a mask. This leaves fluorocarbon type deposition on sides of the etched hole. Then, any residue of the silicon film is etched using the gas of Cl2, HBr, SF6 or O2. This makes it possible to provide a configuration having inclined sides after etching.

Abstract: In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions.

Abstract: A method for forming void free tungsten plug contacts (56a-56c) begins by etching a contact opening (55a-55c) using a C2F6 and CHF3 chemistry. The etch chemistry is then changed to an O2 and CH3F chemistry in order to insitu remove the contact photoresist while tapering an upper portion of the contact opening. A tungsten deposition process is then performed whereby the tapered portion of the contact reduces the effects of nonconformal and step-coverage-inconsistent tungsten deposition wherein voids in the contact are either substantially reduced or totally avoided within the contact structure. The reduction of or total elimination of voids (22) within the tungsten contact will increase yield, increase reliability, and reduce electromigration failures within integrated circuit devices.

Abstract: Memory gate stacks having widths of about 0.18 microns to 0.15 microns are formed by trimming a resist mask pattern, having line widths of about 0.25 microns, to a width of about 0.20 microns. An antireflective coating layer such as silicon oxynitride underlying the resist pattern is then etched to form etched silicon oxynitride pattern lines having widths of about 0.18 to 0.15 microns. The etched silicon oxynitride layer is then used for self-aligned etching of underlying layers to form the memory gate stack. Hence, a memory gate can be formed that has a width substantially less than the current photolithography limit during formation of the resist mask pattern.

Abstract: A semiconductor device has a floating gate having a side wall with a generally vertical upper section and a tapered lower section and a first insulation film formed on the side wall of the floating gate by thermal oxidation. The first insulation film has an upper section and a lower section that is thicker than the upper section. The semiconductor device also has a second insulation film formed on the first insulation film, and a control gate formed on the second insulation film. As a result, an insulation film between the control gate and the floating gate has a sufficient thickness difference between the upper section and the lower section of the floating gate.

Abstract: A method of forming a small contact hole uses a bright field mask to form a small cylinder in a positive resist layer. A negative resist layer is formed around the small cylinder, and then etched or polished back to leave a top portion of the small cylinder exposed above the negative resist layer. The negative resist layer and the small cylinder (positive resist) are flood exposed to light, and then subject to a developer. What remains is a small contact hole located where the small cylinder was previously located.

Abstract: An oxide etching method, particularly applicable to forming through an oxide layer a wineglass shaped contact or via hole of controlled shape. The wineglass hole is particularly useful for eased metal hole filling. The bowl is etched by first etching an anisotropic hole through a mask aperture, and then isotropically etching through the same mask aperture. The relative periods of the anisotropic and isotropic etch determine the lateral-to-vertical dimensions of the bowl. The stem is then etched through the same mask aperture with a strongly anisotropic etch. The isotropic etch may be performed in the same chamber as the anisotropic etch or may advantageously be performed in a separate etch chamber having a remote plasma source.

Abstract: Retrograde openings in thin films and the process for forming the same. The openings may include conductive materials formed within the openings to serve as a wiring pattern which includes wires having tapered cross sections. The process involves a two-step etching procedure for forming a retrograde opening within a film having a gradient of a characteristic that influences the etch rate for a chosen etchant species. An opening is first formed within the film by an anisotropic etch process. The opening is then converted to an opening including retrograde features by an isotropic etch process which is selective to the characteristic. Thereafter, the retrograde opening is filled with a conductive material, in one case, by electroplating or other deposition techniques.

Abstract: Using sub-micron technology, silicon on insulator (SOI) rows and islands are formed in a silicon substrate. Trenches are directionally-etched in the silicon substrate, leaving rows of silicon between the trenches. Silicon nitride is then deposited over the trenches, extending partly down the sides of the trenches. An isotropic chemical etch is then used to partially undercut narrow rows of silicon in the substrate. A subsequent oxidation step fully undercuts the rows of silicon, isolating the silicon rows from adjacent active areas. Devices, such as transistors for CMOS and DRAMs, are then formed in active areas, wherein the active areas are defmed on the silicon rows by LOCal Oxidation of Silicon (LOCOS).

Abstract: A system and method for performing plasma etch on a spherical shaped device is disclosed. The system includes a processing tube for providing a reactive chamber for the spherical shaped substrate and a plasma jet is located adjacent to the processing tube. The plasma jet includes a pair of electrodes, such as a central cathode and a surrounding anode, for producing a plasma flame directed towards the reactive chamber. The central cathode may, for example, be powered by a radio frequency power source. As a result, the reactive chamber supports non-contact etching of the spherical shaped substrate by the plasma flame.

Abstract: In a method for manufacturing a conductive pattern layer, a conductive layer is deposited on a substrate, and an etching mask layer is coated onto the conductive layer. First, the conductive layer is etched by a first etching solution using the etching mask layer to expose the substrate a sidewall of the conductive layer. Then, the conductive layer is etched by a second etching solution using the etching mask to retard the sidewall of the conductive layer.

Abstract: A method and apparatus for improving the accuracy of a contact to an underlying layer comprises the steps of forming a first photoresist layer over the underlying layer, forming a mask layer over the first photoresist layer, then forming a patterned second photoresist layer over the mask layer. The mask layer is patterned using the second photoresist layer as a pattern then the first photoresist layer is patterned using the mask layer as a pattern. A tapered hole is formed in the first photoresist layer, for example using an anisotropic etch. The tapered hole has a bottom proximate the underlying layer and a top distal the underlying layer with the top of the hole being wider than the bottom of the hole.

Abstract: An improved apparatus and method for manufacturing semiconductor devices, and, in particular, for depositing material at the bottom of a contact hole, comprises sputtering a material onto a semiconductor substrate; applying a first bias voltage to the substrate, simultaneously removing the material surrounding the contact hole to form a facet at the top of the recess; and applying a second bias voltage to the substrate, simultaneously sputter-depositing the first material onto the bottom of the recess. A further embodiment of the invention utilizes an electrically isolated collimator for the sputtering apparatus. Another embodiment of the invention resputters a first material onto sidewalls of a contact hole during physical vapor deposition.

Abstract: A method for fabricating a Y-gate structure is provided. The method comprises the steps of providing a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer, a first sacrificial layer over the protection layer and a second sacrificial layer over the first sacrificial layer. An inwardly sloping opening is formed in the second sacrificial layer and the opening is extended vertically in the first sacrificial layer. A contact material is deposited over the second sacrificial layer filling the opening with the contact material and forming a contact layer and portions of the contact material outside a gate region are removed. The first sacrificial layer and the second sacrificial layer are then removed.

Abstract: Semiconductor processing methods of forming conductive projections and methods of increasing alignment tolerances are described. In one implementation, a conductive projection is formed over a substrate surface area and includes an upper surface and a side surface joined therewith to define a corner region. The corner region of the conductive projection is subsequently beveled to increase an alignment tolerance relative thereto. In another implementation, a conductive plug is formed over a substrate node location between a pair of conductive lines and has an uppermost surface. Material of the conductive plug is unevenly removed to define a second uppermost surface, at least a, portion of which is disposed elevationally higher than a conductive line. In one aspect, conductive plug material can be removed by facet etching the conductive plug.

Abstract: A method to fabricate bottle-shaped deep trench into a semiconductor substrate. After a neck profile is formed, the chlorine gas at a predetermined flow rate is added to the etching plasma gas composition, while the flow rates of the plasma gases are increased by about 30% by volume, to create an enlarged lower portion of the deep trench. Preferably, the neck portion is etched using an etching composition which contains HBr, NF3, and (He/O2) provided at flow rates of about 87:13:35 sccm. The enlarged lower portion is etched using an etching composition which contains HBr, NF3, and (He/O2) provided at flow rates of about 113±12:17±2:46±5 sccm, and Cl2 provided at a flow rate between 10 and 40 sccm. It was found that the width of the lower portion of the deep trench can be increased by 100% with minimum side effects such as polymer deposition in the plasma chamber, which could occur as result of substantially increased flow rate of HBr and/or NF3.

Abstract: A method of fabricating a wide-based boxed-structured capacitor containing hemi-spherical silicon grains. A substrate is provided with a source/drain and a first dielectric layer is formed on the substrate with a node contact opening. Then a doped polysilicon layer and a doped amorphous silicon layer are formed sequentially on the first dielectric layer. An etching step is performed to etch the doped amorphous silicon layer and the doped polysilicon layer and a wide-based lower electrode is formed by adjusting flow speeds of chlorine and of hydrogen bromide. Hemi-spherical silicon grains are formed on the surface of the doped amorphous silicon layer in the lower electrode. A second dielectric layer and an upper electrode are formed sequentially on the lower electrode and the capacitor is completed.

Abstract: A fabrication method for a self-aligned contact opening involves using polysilicon to protect a cap layer above a conductive line or even a corner of a spacer on a sidewall of the conductive line. A silicon oxide layer is then etched using a conventional silicon oxide etching recipe to form a self-aligned contact opening. This conventional silicon oxide etching recipe not only has a higher etching selectivity for silicon oxide to silicon nitride, but also yields a higher etching selectivity ratio for silicon oxide to polysilicon.

Abstract: A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e., <30:1) is described. The method forms a passivation film to the extent necessary for preventing isotropic etching of the substrate, hence maintaining the required profile and the shape of the DT within the substrate. The RIE process described provides a partial DT etched into a substrate to achieve the predetermined depth. The passivation film is allowed to grow to a certain thickness still below the extent that it would close the opening of the deep trench. Alternatively, the passivation film is removed by a non-RIE etching process. The non-RIE process that removes the film can be wet etched with chemicals, such as hydrofluoric acid (buffered or non buffered) or, alternatively, using vapor phase and/or non-ionized chemicals, such as anhydrous hydrofluoric acid.

Abstract: A method to fabricate a floating gate with a sloping sidewall for a Flash Memory is described. Field oxide isolation regions are provided in the substrate. A silicon oxide layer is provided overlying the isolation regions and the substrate. A first polysilicon layer is deposited overlying the silicon oxide layer. A photoresist layer is deposited overlying the first polysilicon layer. The photoresist layer is etched to remove sections of the photoresist as defined by photolithographic process. The photoresist layer, the first polysilicon layer, and the silicon oxide layer are etched in areas uncovered by the photoresist layer to create structures with sloping sidewall edges. The photoresist layer is etched away. An interpoly dielectric layer is deposited overlying the structures, the sloping sidewall edges, and the isolation regions. A second polysilicon layer is deposited overlying the interpoly dielectric and the fabrication of the integrated circuit device is completed.

Abstract: A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

Abstract: A new method is provided for the creation of the trenches or line patterns of damascene structures. Under the first embodiment of the invention, the trenches that are created for the copper interconnect lines are sputter etched as a result of which the corners of the trenches around the top elevation of the trenches are rounded. Under the second embodiment of the invention a disposable hard mask is created over the surface of the dielectric after which the trenches for the interconnect lines are created. The surface of the hard mask layer including the created trenches are rf sputter etched resulting in a sharp reduction of the angle of incidence between sidewalls of the trenches around the perimeter of the trenches and the surface of the layer of dielectric. The barrier and seed layers are deposited over the surface of the disposable hard mask including the created trenches, the deposited copper is polished down to the surface of the dielectric.

Abstract: A semiconductor device comprising a semiconductor substrate, a trench formed in the substrate and having an inner wall including a sidewall and a bottom surface, a silicon oxide film deposited on the inner wall, and a buried oxide film deposited on the silicon oxide film to bury the trench, wherein the sidewall has portions of a sidewall sloped at a first profile angle A1, a second profile angle A2 and a third profile angle A3 from a surface of the substrate toward the bottom surface of the trench, and the profile angles have a relationship of A1<A2, A3<A2 and A1<83°.

Abstract: An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having gradual doping profiles and reduced process complexity is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles and the sloped profiles are used as masks during the ion implantation of the LDD structures to space the resultant LDD structures away from the edges of second polysilicon gates to be formed subsequently with substantially vertical profiles. Since the LDD structures are spaced away from the edges of the second polysilicon gates, the lateral diffusion of the LDD structures into the channel due to rapid thermal annealing is reduced.

Abstract: An interconnection substrate comprises an uppermost interconnection layer having a plurality of terminal pads located at positions corresponding to a plurality of solder bumps (external connection terminals) provided on a semiconductor element which is to be mounted on the interconnection substrate. The interconnection substrate also has a metal column formed on each of the terminal pads and has a resin film covering a side surface of the metal column. The interconnection substrate further has an insulating layer formed on the uppermost interconnection layer so that a gap is formed between the insulating layer and an outer peripheral surface of the resin film.

Abstract: A metal is formed at a rear surface of a substrate, the substrate also having a front surface at which a molded semiconductor chip is mounted. The metal pattern is covered with an insulating film, except for at a connecting area. A solder ball is bonded to the connecting area. The area of the metal pattern other than the connecting area inclines toward the substrate and gradually becomes thinner toward the outside thereof. Stress, which is applied to the solder ball, is imparted in a diagonal direction and is dispersed. As a result, the number of occurrences of cracks is reduced, and the solder ball which is used to achieve connection with an external substrate, is effectively prevented form becoming electrically disconnected.

Abstract: Under the first embodiment of the invention, a three layer composite layer of insulation is deposited. The trench is etched into this composite layer of insulation followed by a hard bake. The via etch is performed, completing the formation of the dual damascene profile. The created dual damascene profile is transferred into the underlying substrate; the layer of photoresist is removed. Under the second embodiment of the invention, a two layer composite layer of insulation is deposited over a semiconductor surface. The trench is etched into this composite layer of insulation. A layer of positive photoresist is deposited over the second layer of cross-linked negative resist and masked for the via etch. The via etch is performed, the created dual damascene profile is transferred into the underlying substrate. The removal of the layers of patterned photoresist completes the formation of the dual damascene structure.

Abstract: The invention provides an integrated circuit containing at least a portion of a first, horizontal, conductive or semiconductive layer covered by a first electrically insulating layer. A first conductive member is vertically provided through the first electrically insulating layer in electrical contact with the first, horizontal layer. The first conductive member includes a lower, substantially cylindrical portion, and an upper portion comprising an enlarged head. An upper surface of the upper portion is substantially coplanar with an upper surface of the first electrically insulating layer. A second electrically insulating layer is deposited over the upper surface of the upper portion of the first conductive member and the upper surface of the first electrically insulating layer. A second conductive member is provided through the second electrically insulating layer.

Abstract: A process for selectively introducing a dopant into the bottom of a trench formed in a semiconductor material layer includes depositing a barrier layer by a process of deposition over the semiconductor material layer to form a deposited barrier layer. The deposited barrier layer has, over lateral walls and a bottom wall of the trench, a thickness which is lower than a nominal thickness of the deposited barrier layer over a planar surface of the semiconductor material layer. The method also including implanting a dopant using the deposited barrier layer as an implant mask.

Abstract: There is disclosed a method of manufacturing a heterojunction bipolar transistor.

Abstract: The invention describes a self-aligned etching process. A conductive layer and a first insulating layer are formed on a substrate in sequence, and then the conductive layer and the first insulating layer are patterned to form a plurality of stacks on desired regions. Subsequently, spacers are formed on sidewalls of each stack, and a stop layer is then formed on the substrate. A second insulating layer is formed on the substrate and is planarized. Portions of the second insulating layer are removed to form a plurality of openings and to expose portions of the stop layer located between spacers. The exposed stop layer is removed.

Abstract: The invention defines a method for fabricating a semiconductor insulation layer: A semiconductor substrate is first provided; an insulation layer is applied by way of region-by-region or whole-area application to the semiconductor substrate; impurity ions are selectively implanted into at least one predetermined zone of the insulation layer; then the insulation layer is selectively etched, and the insulation layer is thereby patterned in accordance with the zone or zones of the selectively implanted impurity ions. Likewise, the present invention provides a method for fabricating a semiconductor component containing this semiconductor insulation layer.

Abstract: A method of forming a self-aligned dual damascene structure in a semiconductor device arrangement forms an oxide dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the oxide dielectric layer, and a low k dielectric layer is formed on the nitride etch stop layer. A trench is etched into the low k dielectric layer, followed by the etching of a via into the oxide dielectric layer. The oxide dielectric material and low k dielectric material are selected so that they have different sensitivity to at least one etchant chemistry. Undercutting in the second dielectric layer caused by overetching is thereby prevented during the etching of the via in the second dielectric layer by employing an etch chemistry that etches only the oxide dielectric material and not the low k dielectric material.

Abstract: A method of manufacturing semiconductor device that improves the alignment margin between a contact hole and a device pattern includes a layer having an upper vertically shaped portion and a lower symmetrically inclined shaped portion. That is, the lower portion is tapered.

Abstract: A method of making a capacitor includes the steps of forming an interconnection line above a substrate, depositing a first dielectric layer on the interconnection line, and etching a via in the first dielectric layer. The via has a tapered width which increases in a direction toward the substrate. Further, the method includes filling the via with a conductive metal to form a metal plug, and etching a trench in the first dielectric layer around an upper portion of the metal plug. The metal plug has a tapered width which secures it into the dielectric layer. A second dielectric layer is deposited adjacent the metal plug and an upper electrode is deposited on the second dielectric layer. Preferably, a lower electrode is deposited to line the trench and contact the metal plug.

Abstract: A method for forming a shallow trench isolation used to isolate a device is provided. A pad oxide and a mask layer are formed on a substrate and patterned. A trench is formed within the substrate under the patterned region and the trench is filled with insulator to form an insulation plug, which is a shallow trench isolation. A dielectric layer is formed on the whole substrate surface to cover the device region and the insulation plug.

Abstract: An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having reduced polysilicon gate length, reduced parasitic capacitance and gradual doping profiles is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a polysilicon gate, wherein the polysilicon gate comprises sidewalls with re-entrant profiles, and implanting the semiconductor substrate with a dopant to penetrate portions of the sidewalls to form one or more graded shallow junctions with gradual doping profiles. The gradual doping profiles reduce parasitic capacitance and minimize hot carrier injections.

Abstract: In order to provide a method for manufacturing a semiconductor device in which, in a trench isolation process of the semiconductor device, any void is not formed in trenches and a repeating pitch of the trench isolation can be reduced to the limitations of a lithography technique, the method of the present invention comprises, in the trench isolation process, a step of etching a silicon substrate through a hard mask to form trenches, and a step of processing the hard mask so that its upper portion may be tapered.

Abstract: A semiconductor device and a manufacturing method for a hyperfine structure wherein contact of a gate electrode with a side-wall composed of a silicon nitride layer within a contact hole due to an alignment deviation may be prevented. The semiconductor device is structured such that the contact hole is formed in an inter-layer insulating layer and the side-wall is formed along a wall surface within the contact hole. A bottom of the side-wall is composed of a silicon oxide layer or a silicon oxide nitride layer, and an upper portion of the side-wall is formed of a silicon nitride layer.

Abstract: A method for forming a stacked capacitor includes the steps of providing a first insulating layer having a conductive access path therethrough, forming a second insulating layer on the first insulating layer, forming a trench in the second insulating layer, the trench having tapered sidewalls, forming a first electrode in the trench and on the trench sidewalls, the first electrode being electrically coupled to the conductive access path, forming a dielectric layer on the first electrode and forming a second electrode on the dielectric layer. A stacked capacitor having increased surface area includes a first electrode formed in a trench provided in a dielectric material. The first electrode has tapered surfaces forming a conically shaped portion of the first electrode, the first electrode for accessing a capacitively coupled storage node.

Abstract: A semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material includes, a) providing a node within a mass of insulating dielectric material; b) first stage etching into the insulating dielectric material over the node in a manner substantially selective relative to the node; c) after the first stage etching, second stage etching the dielectric material in a manner which increases a degree of sidewall polymerization over that occurring in the first stage etching and in a manner substantially selective relative to the node; and d) after the second stage etching, third stage etching the dielectric material with a degree of sidewall polymerization which is less than that of the second stage etching and in a manner substantially selective relative to the first node. An alternate method provides an etch stop annulus cap 70 overlying an electrically conductive ring 62 which projects from a primary insulating layer 54.

Abstract: A method for forming void free tungsten plug contacts (56a-56c) begins by etching a contact opening (55a-55c) using a C.sub.2 F.sub.6 and CHF.sub.3 chemistry. The etch chemistry is then changed to an O.sub.2 and CH.sub.3 F chemistry in order to insitu remove the contact photoresist while tapering an upper portion of the contact opening. A tungsten deposition process is then performed whereby the tapered portion of the contact reduces the effects of nonconformal and step-coverage-inconsistent tungsten deposition wherein voids in the contact are either substantially reduced or totally avoided within the contact structure. The reduction of or total elimination of voids (22) within the tungsten contact will increase yield, increase reliability, and reduce electromigration failures within integrated circuit devices.

Abstract: A post-etch structure resulting in the inverse of a sidewall spacer etch, i.e. removal of the spacer. A vertical portion of a film is removed while leaving horizontal portions substantially intact. A facet is left in the film in register with an upper corner formed by the vertical and horizontal portions of the underlying body.

Abstract: A method for forming a via opening includes first an oxide layer formed over a metal layer. Next, a first stage via opening is formed on the oxide layer by photolithography and dry etching. Then, a wet etching process is performed on the first stage via opening to form a completed via opening to just exposes the metal layer and widen the width of the via opening.

Abstract: A method and apparatus provide for etching a semiconductor wafer using a two step physical etching and a chemical etching process in order to create vertical sidewalls required for high density DRAMs and FRAMs.

Abstract: The reliability of in-laid metallization patterns, e.g., of copper or a copper-based alloy is significantly enhanced by voidlessly filling recesses formed in the dielectric layer surface by an electroplating process. Embodiments of the present invention include preventing "pinching-off" of the recess opening due to formation of overhanging nucleation/seed layer deposits at the corners of the opening as a result of locally increased rates of deposition. Embodiments of the present invention also include providing a dual-layered dielectric layer comprising dielectric materials having different lateral etching rates when subjected to a preselected etching process, for selectively tapering the width of the recess mouth opening to provide a wider opening at the substrate surface, which tapered width profile effectively prevents formation of overhanging deposits, which overhanging deposits can result in occlusion and void formation during electroplating to fill the recesses.

Abstract: In-laid metallization patterns, e.g., of copper or copper alloy, are formed in the surface of a dielectric layer with significantly improved reliability by voidlessly filling recesses formed in the dielectric layer surface by electroplating. Embodiments include preventing "pinching-off" of the recess opening due overhanging nucleation/seed layer deposits at the corners of the opening as a result of localized increased rates of deposition. Embodiments also include providing a dual-layered dielectric layer comprising different dielectric materials and performing a first, isotropic etching process of the upper (sacrificial) lamina of the dielectric layer for selectively tapering the width of the recess mouth opening to provide a wider opening at the substrate surface, followed by a second, anisotropic etching process for extending the recess at a substantially constant width for a predetermined depth into the lower lamina of the dielectric layer.